1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License, v.1, (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://opensource.org/licenses/CDDL-1.0.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright 2014-2017 Cavium, Inc.
24 * The contents of this file are subject to the terms of the Common Development
25 * and Distribution License, v.1, (the "License").
26
27 * You may not use this file except in compliance with the License.
28
29 * You can obtain a copy of the License at available
30 * at http://opensource.org/licenses/CDDL-1.0
31
32 * See the License for the specific language governing permissions and
33 * limitations under the License.
34 */
35
36 /****************************************************************************
37 *
38 * Name: mcp_private.h
39 *
40 * Description: MCP private data. Located in HSI only to provide debug access
41 * for diag.
42 *
43 ****************************************************************************/
44
45 #ifndef MCP_PRIVATE_H
46 #define MCP_PRIVATE_H
47
48 #if (!defined MFW_SIM) && (!defined RECOVERY)
49 #include "eth.h"
50 #include "pmm.h"
51 #include "ah_eth.h"
52 #endif
53 #include "mcp_public.h"
54
55 typedef enum active_mf_mode {
56 MF_MODE_SF = 0,
57 MF_MODE_MF_ALLOWED,
58 MF_MODE_MF_SWITCH_INDEPENDENT,
59 MF_MODE_NIV
60 } active_mf_mode_t;
61
62 enum ov_current_cfg {
63 CURR_CFG_NONE = 0,
64 CURR_CFG_OS,
65 CURR_CFG_VENDOR_SPEC,
66 CURR_CFG_OTHER,
67 CURR_CFG_VC_CLP,
68 CURR_CFG_CNU,
69 CURR_CFG_DCI,
70 CURR_CFG_HII,
71 };
72
73 struct dci_info_global {
74 enum ov_current_cfg current_cfg;
75 u8 pci_bus_num;
76 u8 boot_progress;
77 };
78
79 /* Resource allocation information of one resource */
80 struct resource_info_private {
81 u16 size; /* number of allocated resources */
82 u16 offset; /* Offset of the 1st resource */
83 u8 flags;
84 };
85
86 /* Cache for resource allocation of one PF */
87 struct res_alloc_cache {
88 u8 pf_num;
89 struct resource_info_private res[RESOURCE_MAX_NUM];
90 };
91
92 struct pf_sb_t {
93 u8 sb_for_pf_size;
94 u8 sb_for_pf_offset;
95 u8 sb_for_vf_size;
96 u8 sb_for_vf_offset;
97 };
98
99 /**************************************/
100 /* */
101 /* P R I V A T E G L O B A L */
102 /* */
103 /**************************************/
104 struct private_global {
105 active_mf_mode_t mf_mode; /* TBD - require initialization */
106 u32 exp_rom_nvm_addr;
107
108 /* The pmm_config structure holds all active phy/link configuration */
109 #ifndef RECOVERY
110 #ifdef b900
111 struct pmm_config eth_cfg;
112 #else
113 struct ah_eth eth_cfg;
114 #endif
115 #endif
116
117 u32 lldp_counter;
118
119 u32 avs_init_timestamp;
120
121 u32 seconds_since_mcp_reset;
122
123 u32 last_malloc_dir_used_timestamp;
124 #define MAX_USED_DIR_ALLOWED_TIME (3) /* Seconds */
125
126 u32 drv_nvm_state;
127 /* Per PF bitmask */
128 #define DRV_NVM_STATE_IN_PROGRESS_MASK (0x0000ffff)
129 #define DRV_NVM_STATE_IN_PROGRESS_OFFSET (0)
130
131 u32 storm_fw_ver;
132
133 /* OneView data*/
134 struct dci_info_global dci_global;
135
136 /* Resource allocation cached data */
137 struct res_alloc_cache res_alloc;
138 #define G_RES_ALLOC_P (&g_spad.private_data.global.res_alloc)
139 u32 resource_max_values[RESOURCE_MAX_NUM];
140 };
141
142 /**************************************/
143 /* */
144 /* P R I V A T E P A T H */
145 /* */
146 /**************************************/
147 struct private_path {
148 u32 recovery_countdown; /* Counting down 2 seconds, using TMR3 */
149 #define RECOVERY_MAX_COUNTDOWN_SECONDS 2
150
151 u32 drv_load_vars; /* When the seconds_since_mcp_reset gets here */
152 #define DRV_LOAD_TIMEOUT_MASK 0x0000ffff
153 #define DRV_LOAD_TIMEOUT_SHIFT 0
154 #define DRV_LOAD_NEED_FORCE_MASK 0xffff0000
155 #define DRV_LOAD_NEED_FORCE_SHIFT 16
156 struct load_rsp_stc drv_load_params;
157 };
158
159
160 /**************************************/
161 /* */
162 /* P R I V A T E P O R T */
163 /* */
164 /**************************************/
165 struct drv_port_info_t {
166 u32_t port_state;
167 #define DRV_STATE_LINK_LOCK_FLAG 0x00000001
168 #define DRV_WAIT_DBG_PRN 0x00000002
169
170 /* There are maximum 8 PFs per port */
171 #define DRV_STATE_LOADED_MASK 0x0000ff00
172 #define DRV_STATE_LOADED_SHIFT 8
173
174 #define DRV_STATE_PF_TRANSITION_MASK 0x00ff0000
175 #define DRV_STATE_PF_TRANSITION_SHIFT 16
176
177 #define DRV_STATE_PF_PHY_INIT_MASK 0xff000000
178 #define DRV_STATE_PF_PHY_INIT_SHIFT 24
179 };
180
181 typedef enum _lldp_subscriber_e {
182 LLDP_SUBSCRIBER_MANDATORY = 0,
183 LLDP_SUBSCRIBER_DCBX_IEEE,
184 LLDP_SUBSCRIBER_DCBX_CEE,
185 LLDP_SUBSCRIBER_EEE,
186 LLDP_SUBSCRIBER_DCI,
187 MAX_SUBSCRIBERS
188 } lldp_subscriber_e;
189
190 typedef struct {
191 u16 valid;
192 u16 type_len;
193 #define LLDP_LEN_MASK (0x01ff)
194 #define LLDP_LEN_SHIFT (0)
195 #define LLDP_TYPE_MASK (0xfe00)
196 #define LLDP_TYPE_SHIFT (9)
197 u8 *value_p;
198 } tlv_s;
199
200 typedef u16(*lldp_prepare_tlv_func)(u8 port, lldp_agent_e lldp_agent, u8 *buffer);
201
202 typedef struct {
203 u16 valid;
204 lldp_prepare_tlv_func func;
205 } subscriber_callback_send_s;
206
207 typedef u8(*lldp_process_func)(u8 port, u8 num, u8 **tlvs);
208
209 #define MAX_NUM_SUBTYPES 4
210 typedef struct {
211 u8 valid;
212 u8 oui[3];
213 u8 subtype_list[MAX_NUM_SUBTYPES];
214 u8 num_subtypes;
215 lldp_process_func func;
216 } subscriber_callback_receive_s;
217
218 #define MAX_ETH_HEADER 14 /* TODO: to be extended per requirements */
219 #define MAX_PACKET_SIZE (1516) /* So it can be devided by 4 */
220 #define LLDP_CHASSIS_ID_TLV_LEN 7
221 #define LLDP_PORT_ID_TLV_LEN 7
222 #define MAX_TLV_BUFFER 128 /* In dwords. 512 in bytes*/
223 typedef struct {
224 u16 len;
225 u8 header[MAX_ETH_HEADER];
226 } lldp_eth_header_s;
227
228 typedef struct {
229 struct lldp_config_params_s lldp_config_params;
230 u16 lldp_ttl;
231 u8 lldp_cur_credit;
232 subscriber_callback_send_s subscriber_callback_send[MAX_SUBSCRIBERS];
233 lldp_eth_header_s lldp_eth_header;
234 u32 lldp_time_to_send;
235 u32 lldp_ttl_expired;
236 u32 lldp_sent;
237 u8 first_lldp;
238 subscriber_callback_receive_s subscriber_callback_receive[MAX_SUBSCRIBERS];
239 } lldp_params_s;
240
241 #define MAX_TLVS 20
242 typedef struct {
243 u8 current_received_tlv_index;
244 u8 *received_tlvs[MAX_TLVS];
245 } lldp_receive_data_s;
246
247 #define MAX_REGISTERED_TLVS 6
248
249 typedef struct {
250 u32 config; /* Uses same defines as local config plus some more below*/
251 #define DCBX_MODE_MASK 0x00000010
252 #define DCBX_MODE_SHIFT 4
253 #define DCBX_MODE_DRIVER 0
254 #define DCBX_MODE_DEFAULT 1
255 #define DCBX_CHANGED_MASK 0x00000f00
256 #define DCBX_CHANGED_SHIFT 8
257 #define DCBX_CONTROL_CHANGED_MASK 0x00000100
258 #define DCBX_CONTROL_CHANGED_SHIFT 8
259 #define DCBX_PFC_CHANGED_MASK 0x00000200
260 #define DCBX_PFC_CHANGED_SHIFT 9
261 #define DCBX_ETS_CHANGED_MASK 0x00000400
262 #define DCBX_ETS_CHANGED_SHIFT 10
263 #define DCBX_APP_CHANGED_MASK 0x00000800
264 #define DCBX_APP_CHANGED_SHIFT 11
265
266 u32 seq_no;
267 u32 ack_no;
268 u32 received_seq_no;
269 u8 tc_map[8];
270 u8 num_used_tcs;
271 } dcbx_state_s;
272
273 #ifdef CONFIG_HP_DCI_SUPPORT
274 struct dci_info_port {
275 u32 config;
276 #define DCI_PORT_CFG_ENABLE_SHIFT (0)
277 #define DCI_PORT_CFG_ENABLE_MASK (1 << DCI_PORT_CFG_ENABLE_SHIFT)
278 #define DCI_PORT_CFG_ENABLE_DIAG_SHIFT (1)
279 #define DCI_PORT_CFG_ENABLE_DIAG_MASK (1 << DCI_PORT_CFG_ENABLE_DIAG_SHIFT)
280 #define DCI_PORT_CFG_DIAG_L_LOOP_SHIFT (2)
281 #define DCI_PORT_CFG_DIAG_L_LOOP_MASK (1 << DCI_PORT_CFG_DIAG_L_LOOP_SHIFT)
282 #define DCI_PORT_CFG_DIAG_R_LOOP_SHIFT (3)
283 #define DCI_PORT_CFG_DIAG_R_LOOP_MASK (1 << DCI_PORT_CFG_DIAG_R_LOOP_SHIFT)
284
285 };
286 #endif
287
288 struct private_port {
289 struct drv_port_info_t port_info;
290 active_mf_mode_t mf_mode;
291 u32 prev_link_change_count;
292 /* LLDP structures */
293 lldp_params_s lldp_params[LLDP_MAX_LLDP_AGENTS];
294 lldp_receive_data_s lldp_receive_data[MAX_SUBSCRIBERS];
295
296 /* DCBX */
297 dcbx_state_s dcbx_state;
298
299 u32 net_buffer[MAX_PACKET_SIZE / 4]; /* Buffer to send any packet to network */
300
301 /* time stamp of the end of NIG drain time for the TX drain */
302 u32 nig_drain_end_ts;
303 /* time stamp of the end of NIG drain time for the TC pause drain, this timer is used togther for all TC */
304 u32 nig_drain_tc_end_ts;
305 u32 tc_drain_en_bitmap;
306 u32 recv_lldp_tlvs[LLDP_MAX_LLDP_AGENTS][MAX_TLV_BUFFER];
307 tlv_s lldp_core_tlv_desc[LLDP_MAX_LLDP_AGENTS][MAX_REGISTERED_TLVS];
308 u8 current_core_tlv_num[LLDP_MAX_LLDP_AGENTS];
309 struct mcp_mac lldp_mac;
310 #ifdef CONFIG_HP_DCI_SUPPORT
311 struct dci_info_port dci_port;
312 #endif
313 u32 temperature;
314
315 };
316
317 /**************************************/
318 /* */
319 /* P R I V A T E F U N C */
320 /* */
321 /**************************************/
322 struct drv_func_info_t {
323 u32_t func_state;
324 #define DRV_STATE_UNKNOWN 0x00000000
325 #define DRV_STATE_UNLOADED 0x00000001
326 #define DRV_STATE_D3 0x00000004
327
328 #define DRV_STATE_PRESENT_FLAG 0x00000100
329 #define DRV_STATE_RUNNING (0x00000002 | DRV_STATE_PRESENT_FLAG)
330
331 #define DRV_STATE_NOT_RESPONDING 0x00000003 /* Will result with non-zero value when compared with DRV_STATE_RUNNING or with DRV_STATE_UNLOADED */
332 #define DRV_STATE_BACK_AFTER_TO (DRV_STATE_NOT_RESPONDING | DRV_STATE_PRESENT_FLAG)
333
334 #define DRV_STATE_DIAG (0x00000010 | DRV_STATE_PRESENT_FLAG)
335
336 #define DRV_STATE_TRANSITION_FLAG 0x00001000
337 #define DRV_STATE_LOADING_TRANSITION (DRV_STATE_TRANSITION_FLAG | DRV_STATE_PRESENT_FLAG)
338 #define DRV_STATE_UNLOADING_TRANSITION (DRV_STATE_TRANSITION_FLAG | DRV_STATE_PRESENT_FLAG | DRV_STATE_UNLOADED)
339
340 u32_t driver_last_activity;
341
342 u32_t wol_mac_addr[2];
343 u32_t drv_feature_support; /* See DRV_MB_PARAM_FEATURE_SUPPORT_FUNC_* */
344
345 u8_t unload_wol_param; /* See drv_mb_param */
346 u8_t eswitch_mode;
347 };
348
349 struct dci_info_func {
350 u8 config;
351 #define DCI_FUNC_CFG_FNIC_ENABLE_SHIFT (0)
352 #define DCI_FUNC_CFG_FNIC_ENABLE_MASK (1 << DCI_FUNC_CFG_FNIC_ENABLE_SHIFT)
353 #define DCI_FUNC_CFG_OS_MTU_OVERRIDE_SHIFT (1)
354 #define DCI_FUNC_CFG_OS_MTU_OVERRIDE_MASK (1 << DCI_FUNC_CFG_OS_MTU_OVERRIDE_SHIFT)
355 #define DCI_FUNC_CFG_DIAG_WOL_ENABLE_SHIFT (2)
356 #define DCI_FUNC_CFG_DIAG_WOL_ENABLE_MASK (1 << DCI_FUNC_CFG_DIAG_WOL_ENABLE_SHIFT)
357
358 u8 drv_state;
359 u16 fcoe_cvid;
360 u8 fcoe_fabric_name[8];
361 };
362
363 struct private_func {
364 struct drv_func_info_t func_info;
365 u32 init_hw_page;
366 u32 num_of_msix;
367 struct pf_sb_t sb;
368 struct dci_info_func dci_func;
369 };
370
371
372 /**************************************/
373 /* */
374 /* P R I V A T E D A T A */
375 /* */
376 /**************************************/
377 struct mcp_private_data {
378 /* Basically no need for section offsets here, since this is private data.
379 * TBD - should consider adding section offsets if we want diag to parse this correctly !!
380 */
381 struct private_global global;
382 struct private_path path[MCP_GLOB_PATH_MAX];
383 struct private_port port[MCP_GLOB_PORT_MAX];
384 struct private_func func[MCP_GLOB_FUNC_MAX];
385
386 };
387 #endif /* MCP_PRIVATE_H */