1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License, v.1, (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://opensource.org/licenses/CDDL-1.0.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright 2014-2017 Cavium, Inc.
24 * The contents of this file are subject to the terms of the Common Development
25 * and Distribution License, v.1, (the "License").
26
27 * You may not use this file except in compliance with the License.
28
29 * You can obtain a copy of the License at available
30 * at http://opensource.org/licenses/CDDL-1.0
31
32 * See the License for the specific language governing permissions and
33 * limitations under the License.
34 */
35
36 /*
37 * mcp_fio definition
38 * offset: 0x80000000
39 */
40 #ifndef MCP_FIO_H
41 #define MCP_FIO_H
42
43 typedef struct mcp_fio
44 {
45 u32_t mcpf_events_bits;
46 #define MCPF_EVENTS_BITS_BMB_WRITE_DONE (1L<<0)
47 #define MCPF_EVENTS_BITS_BMB_READ_RDY (1L<<1)
48 #define MCPF_EVENTS_BITS_P2M_ATTN (1L<<2)
49 #define MCPF_EVENTS_BITS_SMBUS_EVENT (1L<<3)
50 #define MCPF_EVENTS_BITS_FLASH_EVENT (1L<<4)
51 #define MCPF_EVENTS_BITS_RESERVED0 (1L<<5)
52 #define MCPF_EVENTS_BITS_MAIN_TEMPERATURE_RESET (1L<<6)
53 #define MCPF_EVENTS_BITS_MGMT_TEMPERATURE_RESET (1L<<7)
54 #define MCPF_EVENTS_BITS_EXP_ROM (1L<<8)
55 #define MCPF_EVENTS_BITS_VPD (1L<<9)
56 #define MCPF_EVENTS_BITS_FLASH (1L<<10)
57 #define MCPF_EVENTS_BITS_SMB0 (1L<<11)
58 #define MCPF_EVENTS_BITS_CNIG (1L<<12)
59 #define MCPF_EVENTS_BITS_PGLUE_MISC_MCTP_ATTN (1L<<13)
60 #define MCPF_EVENTS_BITS_RESERVED1 (1L<<14)
61 #define MCPF_EVENTS_BITS_GPIO0 (1L<<15)
62 #define MCPF_EVENTS_BITS_GPIO1 (1L<<16)
63 #define MCPF_EVENTS_BITS_GPIO2 (1L<<17)
64 #define MCPF_EVENTS_BITS_GPIO3 (1L<<18)
65 #define MCPF_EVENTS_BITS_GPIO4 (1L<<19)
66 #define MCPF_EVENTS_BITS_GPIO5 (1L<<20)
67 #define MCPF_EVENTS_BITS_GPIO6 (1L<<21)
68 #define MCPF_EVENTS_BITS_GPIO7 (1L<<22)
69 #define MCPF_EVENTS_BITS_SW_TMR_1 (1L<<23)
70 #define MCPF_EVENTS_BITS_SW_TMR_2 (1L<<24)
71 #define MCPF_EVENTS_BITS_SW_TMR_3 (1L<<25)
72 #define MCPF_EVENTS_BITS_SW_TMR_4 (1L<<26)
73 #define MCPF_EVENTS_BITS_PERST_N_ASSERT (1L<<27)
74 #define MCPF_EVENTS_BITS_PERST_N_DEASSERT (1L<<28)
75 #define MCPF_EVENTS_BITS_GP_EVENT (1L<<29)
76 #define MCPF_EVENTS_BITS_NOT_ENABLED (1L<<30)
77 #define MCPF_EVENTS_BITS_ATTENTIONS_VALID (1L<<31)
78
79 u32_t mcpf_attentions_bits;
80 /* Added by Yaniv on 18/5/15. Can add additional interrupts by setting AEU to MCP output 0..7.
81 * When adding new field, here, need to add also define to INUM_ATTENTION_XXX, and add new function to
82 * mcp_attention_handler array in the INUM_ATTENTION_XXX location.
83 */
84 #define MCPF_ATTENTIONS_BITS_PARITY_ERROR (1L<<0)
85 #define MCPF_ATTENTIONS_BITS_ATTN (0xffL<<0)
86
87 u32_t mcpf_event_enable;
88 u32_t mcpf_attention_enable;
89 u32_t mcpf_fio_status;
90 #define MCPF_FIO_STATUS_ENABLED (1L<<0)
91 #define MCPF_FIO_STATUS_FORCE_ENA (1L<<1)
92
93 u32_t mcpf_interrupt_status;
94 #define MCPF_INTERRUPT_STATUS_EVENT0_E0 (1L<<0)
95 #define MCPF_INTERRUPT_STATUS_ATTN0_E0 (1L<<1)
96 #define MCPF_INTERRUPT_STATUS_EVENT1_E0 (1L<<2)
97 #define MCPF_INTERRUPT_STATUS_ATTN1_E0 (1L<<3)
98 #define MCPF_INTERRUPT_STATUS_EVENT0_E1 (1L<<4)
99 #define MCPF_INTERRUPT_STATUS_ATTN0_E1 (1L<<5)
100 #define MCPF_INTERRUPT_STATUS_EVENT1_E1 (1L<<6)
101 #define MCPF_INTERRUPT_STATUS_ATTN1_E1 (1L<<7)
102 #define MCPF_INTERRUPT_STATUS_EVENT2_E0 (1L<<8)
103 #define MCPF_INTERRUPT_STATUS_ATTN2_E0 (1L<<9)
104 #define MCPF_INTERRUPT_STATUS_EVENT3_E0 (1L<<10)
105 #define MCPF_INTERRUPT_STATUS_ATTN3_E0 (1L<<11)
106 #define MCPF_INTERRUPT_STATUS_SOFT_INTERRUPT (1L<<31)
107
108 u32_t mcpf_unused_a[2];
109 u32_t mcpf_unused_b[16];
110 u32_t mcpf_unused_c[4];
111 u32_t mcpf_free_counter_value;
112 u32_t mcpf_timesync_clock_e0_0;
113 u32_t mcpf_timesync_clock_e0_1;
114 u32_t mcpf_timesync_clock_e1_0;
115 u32_t mcpf_timesync_clock_e1_1;
116 u32_t mcpf_soft_interrupt;
117 #define MCPF_SOFT_INTERRUPT_INTERRUPT (1L<<31)
118
119 u32_t mcpf_program_counter;
120 #define MCPF_PROGRAM_COUNTER_INTERRUPT (0xffffffffL<<0)
121
122 u32_t mcpf_mcp_doorbell_status;
123 #define MCPF_MCP_DOORBELL_STATUS_STATUS (0xffffL<<0)
124
125 u32_t mcpf_dbg_mux_message;
126 #define MCPF_DBG_MUX_MESSAGE_DATA (0xffffffffL<<0)
127
128 u32_t mcpf_unused_d[10];
129 u32_t mcpf_mcp_vfid;
130 #define MCPF_MCP_VFID_VFID (0xffL<<0)
131 #define MCPF_MCP_VFID_VFID_VALID (1L<<16)
132 #define MCPF_MCP_VFID_PATHID (1L<<20)
133 #define MCPF_MCP_VFID_FIO_REG_EN (1L<<30)
134 #define MCPF_MCP_VFID_PATH_FORCE (1L<<31)
135
136 u32_t mcpf_unused_e[80];
137 u32_t mcpf_mult_status;
138 #define MCPF_MULT_STATUS_MULTIPLY_DONE (1L<<0)
139
140 u32_t mcpf_mult_result;
141 u32_t mcpf_mult_a;
142 #define MCPF_MULT_A_VALUE (0xffffL<<0)
143
144 u32_t mcpf_mult_b;
145 #define MCPF_MULT_B_VALUE (0xffffL<<0)
146
147 u32_t mcpf_unused_f[39036];
148 u32_t mcpf_nvm_command;
149 #define MCPF_NVM_COMMAND_RST (1L<<0)
150 #define MCPF_NVM_COMMAND_DONE (1L<<3)
151 #define MCPF_NVM_COMMAND_DOIT (1L<<4)
152 #define MCPF_NVM_COMMAND_WR (1L<<5)
153 #define MCPF_NVM_COMMAND_ERASE (1L<<6)
154 #define MCPF_NVM_COMMAND_FIRST (1L<<7)
155 #define MCPF_NVM_COMMAND_LAST (1L<<8)
156 #define MCPF_NVM_COMMAND_ADDR_INCR (1L<<9)
157 #define MCPF_NVM_COMMAND_WREN (1L<<16)
158 #define MCPF_NVM_COMMAND_WRDI (1L<<17)
159 #define MCPF_NVM_COMMAND_ERASE_ALL (1L<<18)
160 #define MCPF_NVM_COMMAND_RD_ID (1L<<20)
161 #define MCPF_NVM_COMMAND_RD_STATUS (1L<<21)
162 #define MCPF_NVM_COMMAND_MODE_256 (1L<<22)
163
164 u32_t mcpf_nvm_status;
165 #define MCPF_NVM_STATUS_SPI_FSM_STATE (0x1fL<<0)
166 #define MCPF_NVM_STATUS_SPI_FSM_STATE_SPI_IDLE (0L<<0)
167 #define MCPF_NVM_STATUS_SPI_FSM_STATE_SPI_CMD0 (1L<<0)
168 #define MCPF_NVM_STATUS_SPI_FSM_STATE_SPI_CMD1 (2L<<0)
169 #define MCPF_NVM_STATUS_SPI_FSM_STATE_SPI_CMD_FINISH0 (3L<<0)
170 #define MCPF_NVM_STATUS_SPI_FSM_STATE_SPI_CMD_FINISH1 (4L<<0)
171 #define MCPF_NVM_STATUS_SPI_FSM_STATE_SPI_ADDR0 (5L<<0)
172 #define MCPF_NVM_STATUS_SPI_FSM_STATE_SPI_WRITE_DATA0 (6L<<0)
173 #define MCPF_NVM_STATUS_SPI_FSM_STATE_SPI_WRITE_DATA1 (7L<<0)
174 #define MCPF_NVM_STATUS_SPI_FSM_STATE_SPI_WRITE_DATA2 (8L<<0)
175 #define MCPF_NVM_STATUS_SPI_FSM_STATE_SPI_WRITE_DATA3 (9L<<0)
176 #define MCPF_NVM_STATUS_SPI_FSM_STATE_SPI_READ_DATA0 (10L<<0)
177 #define MCPF_NVM_STATUS_SPI_FSM_STATE_SPI_READ_DATA1 (11L<<0)
178 #define MCPF_NVM_STATUS_SPI_FSM_STATE_SPI_READ_DATA2 (12L<<0)
179 #define MCPF_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID0 (13L<<0)
180 #define MCPF_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID1 (14L<<0)
181 #define MCPF_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID2 (15L<<0)
182 #define MCPF_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID3 (16L<<0)
183 #define MCPF_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID4 (17L<<0)
184 #define MCPF_NVM_STATUS_SPI_FSM_STATE_SPI_CHECK_BUSY (18L<<0)
185 #define MCPF_NVM_STATUS_SPI_FSM_STATE_SPI_FIRST_WR (19L<<0)
186 #define MCPF_NVM_STATUS_SPI_FSM_STATE_SPI_ERASE (20L<<0)
187 #define MCPF_NVM_STATUS_SPI_FSM_STATE_SPI_WAIT (21L<<0)
188 #define MCPF_NVM_STATUS_SPI_FSM_STATE_SPI_WAIT1 (22L<<0)
189 #define MCPF_NVM_STATUS_SPI_FSM_STATE_SPI_LOAD_BUFFER (23L<<0)
190 #define MCPF_NVM_STATUS_SPI_FSM_STATE_SPI_RDATA_2_BUFFER0 (24L<<0)
191 #define MCPF_NVM_STATUS_SPI_FSM_STATE_SPI_RDATA_2_BUFFER1 (25L<<0)
192 #define MCPF_NVM_STATUS_SPI_FSM_STATE_SPI_RDATA_2_BUFFER2 (26L<<0)
193 #define MCPF_NVM_STATUS_SPI_FSM_STATE_SPI_RDATA_2_BUFFER3 (27L<<0)
194 #define MCPF_NVM_STATUS_SPI_FSM_STATE_SPI_STORE_BUFFER0 (28L<<0)
195 #define MCPF_NVM_STATUS_SPI_FSM_STATE_SPI_STORE_BUFFER1 (29L<<0)
196 #define MCPF_NVM_STATUS_SPI_FSM_STATE_SPI_WDATA_2_BUFFER0 (30L<<0)
197 #define MCPF_NVM_STATUS_SPI_FSM_STATE_SPI_WDATA_2_BUFFER1 (31L<<0)
198
199 u32_t mcpf_nvm_write;
200 #define MCPF_NVM_WRITE_NVM_WRITE_VALUE (0xffffffffL<<0)
201 #define MCPF_NVM_WRITE_NVM_WRITE_VALUE_BIT_BANG (0L<<0)
202 #define MCPF_NVM_WRITE_NVM_WRITE_VALUE_SI (1L<<0)
203 #define MCPF_NVM_WRITE_NVM_WRITE_VALUE_SO (2L<<0)
204 #define MCPF_NVM_WRITE_NVM_WRITE_VALUE_CS_B (4L<<0)
205 #define MCPF_NVM_WRITE_NVM_WRITE_VALUE_SCLK (8L<<0)
206
207 u32_t mcpf_nvm_addr;
208 #define MCPF_NVM_ADDR_NVM_ADDR_VALUE (0xffffffL<<0)
209 #define MCPF_NVM_ADDR_NVM_ADDR_VALUE_BIT_BANG (0L<<0)
210 #define MCPF_NVM_ADDR_NVM_ADDR_VALUE_SI (1L<<0)
211 #define MCPF_NVM_ADDR_NVM_ADDR_VALUE_SO (2L<<0)
212 #define MCPF_NVM_ADDR_NVM_ADDR_VALUE_CS_B (4L<<0)
213 #define MCPF_NVM_ADDR_NVM_ADDR_VALUE_SCLK (8L<<0)
214
215 u32_t mcpf_nvm_read;
216 #define MCPF_NVM_READ_NVM_READ_VALUE (0xffffffffL<<0)
217 #define MCPF_NVM_READ_NVM_READ_VALUE_BIT_BANG (0L<<0)
218 #define MCPF_NVM_READ_NVM_READ_VALUE_SI (1L<<0)
219 #define MCPF_NVM_READ_NVM_READ_VALUE_SO (2L<<0)
220 #define MCPF_NVM_READ_NVM_READ_VALUE_CS_B (4L<<0)
221 #define MCPF_NVM_READ_NVM_READ_VALUE_SCLK (8L<<0)
222
223 u32_t mcpf_nvm_cfg1;
224 #define MCPF_NVM_CFG1_FLASH_MODE (1L<<0)
225 #define MCPF_NVM_CFG1_BUFFER_MODE (1L<<1)
226 #define MCPF_NVM_CFG1_PASS_MODE (1L<<2)
227 #define MCPF_NVM_CFG1_BITBANG_MODE (1L<<3)
228 #define MCPF_NVM_CFG1_STATUS_BIT (0x7L<<4)
229 #define MCPF_NVM_CFG1_SPI_CLK_DIV (0xfL<<7)
230 #define MCPF_NVM_CFG1_SEE_CLK_DIV (0x7ffL<<11)
231 #define MCPF_NVM_CFG1_STRAP_CONTROL_0 (1L<<23)
232 #define MCPF_NVM_CFG1_PROTECT_MODE (1L<<24)
233 #define MCPF_NVM_CFG1_FLASH_SIZE (1L<<25)
234 #define MCPF_NVM_CFG1_FW_USTRAP_1 (1L<<26)
235 #define MCPF_NVM_CFG1_FW_USTRAP_0 (1L<<27)
236 #define MCPF_NVM_CFG1_FW_USTRAP_2 (1L<<28)
237 #define MCPF_NVM_CFG1_FW_USTRAP_3 (1L<<29)
238 #define MCPF_NVM_CFG1_FW_FLASH_TYPE_EN (1L<<30)
239 #define MCPF_NVM_CFG1_COMPAT_BYPASSS (1L<<31)
240
241 u32_t mcpf_nvm_cfg2;
242 #define MCPF_NVM_CFG2_ERASE_CMD (0xffL<<0)
243 #define MCPF_NVM_CFG2_CSB_W (0xffL<<8)
244 #define MCPF_NVM_CFG2_STATUS_CMD (0xffL<<16)
245 #define MCPF_NVM_CFG2_READ_ID_CMD (0xffL<<24)
246
247 u32_t mcpf_nvm_cfg3;
248 #define MCPF_NVM_CFG3_BUFFER_RD_CMD (0xffL<<0)
249 #define MCPF_NVM_CFG3_WRITE_CMD (0xffL<<8)
250 #define MCPF_NVM_CFG3_FAST_READ_CMD (0xffL<<16)
251 #define MCPF_NVM_CFG3_READ_CMD (0xffL<<24)
252
253 u32_t mcpf_nvm_sw_arb;
254 #define MCPF_NVM_SW_ARB_ARB_REQ_SET0 (1L<<0)
255 #define MCPF_NVM_SW_ARB_ARB_REQ_SET1 (1L<<1)
256 #define MCPF_NVM_SW_ARB_ARB_REQ_SET2 (1L<<2)
257 #define MCPF_NVM_SW_ARB_ARB_REQ_SET3 (1L<<3)
258 #define MCPF_NVM_SW_ARB_ARB_REQ_CLR0 (1L<<4)
259 #define MCPF_NVM_SW_ARB_ARB_REQ_CLR1 (1L<<5)
260 #define MCPF_NVM_SW_ARB_ARB_REQ_CLR2 (1L<<6)
261 #define MCPF_NVM_SW_ARB_ARB_REQ_CLR3 (1L<<7)
262 #define MCPF_NVM_SW_ARB_ARB_ARB0 (1L<<8)
263 #define MCPF_NVM_SW_ARB_ARB_ARB1 (1L<<9)
264 #define MCPF_NVM_SW_ARB_ARB_ARB2 (1L<<10)
265 #define MCPF_NVM_SW_ARB_ARB_ARB3 (1L<<11)
266 #define MCPF_NVM_SW_ARB_REQ0 (1L<<12)
267 #define MCPF_NVM_SW_ARB_REQ1 (1L<<13)
268 #define MCPF_NVM_SW_ARB_REQ2 (1L<<14)
269 #define MCPF_NVM_SW_ARB_REQ3 (1L<<15)
270
271 u32_t mcpf_nvm_jedec_id;
272 #define MCPF_NVM_JEDEC_ID_EXTENDED_DEVICE_INFO_LENGTH (0xffL<<0)
273 #define MCPF_NVM_JEDEC_ID_DEVICE_ID (0xffffL<<8)
274 #define MCPF_NVM_JEDEC_ID_MANUFACTURE_ID (0xffL<<24)
275
276 u32_t mcpf_nvm_cfg5;
277 #define MCPF_NVM_CFG5_WREN_CMD (0xffL<<0)
278 #define MCPF_NVM_CFG5_WRDI_CMD (0xffL<<8)
279 #define MCPF_NVM_CFG5_ERASE_ALL_CMD (0xffL<<16)
280 #define MCPF_NVM_CFG5_USE_BUFFER (1L<<30)
281 #define MCPF_NVM_CFG5_USE_LEGACY_SPI_FSM (1L<<31)
282
283 u32_t mcpf_nvm_cfg4;
284 #define MCPF_NVM_CFG4_FLASH_SIZE (0x7L<<0)
285 #define MCPF_NVM_CFG4_FLASH_SIZE_1MBIT (0L<<0)
286 #define MCPF_NVM_CFG4_FLASH_SIZE_2MBIT (1L<<0)
287 #define MCPF_NVM_CFG4_FLASH_SIZE_4MBIT (2L<<0)
288 #define MCPF_NVM_CFG4_FLASH_SIZE_8MBIT (3L<<0)
289 #define MCPF_NVM_CFG4_FLASH_SIZE_16MBIT (4L<<0)
290 #define MCPF_NVM_CFG4_FLASH_SIZE_32MBIT (5L<<0)
291 #define MCPF_NVM_CFG4_FLASH_SIZE_64MBIT (6L<<0)
292 #define MCPF_NVM_CFG4_FLASH_SIZE_128MBIT (7L<<0)
293 #define MCPF_NVM_CFG4_FLASH_VENDOR (1L<<3)
294 #define MCPF_NVM_CFG4_FLASH_VENDOR_ST (0L<<3)
295 #define MCPF_NVM_CFG4_FLASH_VENDOR_ATMEL (1L<<3)
296 #define MCPF_NVM_CFG4_MODE_256_EMPTY_BIT_LOC (0x3L<<4)
297 #define MCPF_NVM_CFG4_MODE_256_EMPTY_BIT_LOC_BIT8 (0L<<4)
298 #define MCPF_NVM_CFG4_MODE_256_EMPTY_BIT_LOC_BIT9 (1L<<4)
299 #define MCPF_NVM_CFG4_MODE_256_EMPTY_BIT_LOC_BIT10 (2L<<4)
300 #define MCPF_NVM_CFG4_MODE_256_EMPTY_BIT_LOC_BIT11 (3L<<4)
301 #define MCPF_NVM_CFG4_STATUS_BIT_POLARITY (1L<<6)
302 #define MCPF_NVM_CFG4_FAST (1L<<7)
303 #define MCPF_NVM_CFG4_SI_INPUT_RELAXED_TIMING (1L<<8)
304 #define MCPF_NVM_CFG4_PASS_MODE_RELAXED_TIMING (1L<<9)
305 #define MCPF_NVM_CFG4_SR_TURNAROUND (1L<<10)
306 #define MCPF_NVM_CFG4_READ_DUMMY_CYCLES (0xfL<<11)
307 #define MCPF_NVM_CFG4_FAST_READ_DUMMY_CYCLES (0xfL<<15)
308 #define MCPF_NVM_CFG4_SPI_SLOW_CLK_DIV (0xfL<<19)
309 #define MCPF_NVM_CFG4_SLOW_CLK_4_BUFFER_RD (1L<<23)
310 #define MCPF_NVM_CFG4_SLOW_CLK_4_ERASE (1L<<24)
311 #define MCPF_NVM_CFG4_SLOW_CLK_4_FAST_READ (1L<<25)
312 #define MCPF_NVM_CFG4_SLOW_CLK_4_READ (1L<<26)
313 #define MCPF_NVM_CFG4_SLOW_CLK_4_READ_ID (1L<<27)
314 #define MCPF_NVM_CFG4_SLOW_CLK_4_STATUS (1L<<28)
315 #define MCPF_NVM_CFG4_SLOW_CLK_4_WRDI (1L<<29)
316 #define MCPF_NVM_CFG4_SLOW_CLK_4_WREN (1L<<30)
317 #define MCPF_NVM_CFG4_SLOW_CLK_4_WRITE (1L<<31)
318
319 u32_t mcpf_nvm_reconfig;
320 #define MCPF_NVM_RECONFIG_ORIG_STRAP_VALUE (0xfL<<0)
321 #define MCPF_NVM_RECONFIG_ORIG_STRAP_VALUE_ST (0L<<0)
322 #define MCPF_NVM_RECONFIG_ORIG_STRAP_VALUE_ATMEL (1L<<0)
323 #define MCPF_NVM_RECONFIG_RECONFIG_STRAP_VALUE (0xfL<<4)
324 #define MCPF_NVM_RECONFIG_RESERVED (0x7fffffL<<8)
325 #define MCPF_NVM_RECONFIG_RECONFIG_DONE (1L<<31)
326
327 u32_t mcpf_nvm_nvm_unused[242];
328 u32_t mcpf_nvm_nvm_reg_end;
329 u32_t mcpf_unused_g[1536];
330 u32_t mcpf_smbus_config;
331 #define MCPF_SMBUS_CONFIG_HW_ARP_ASSIGN_ADDR (1L<<7)
332 #define MCPF_SMBUS_CONFIG_ARP_EN0 (1L<<8)
333 #define MCPF_SMBUS_CONFIG_ARP_EN1 (1L<<9)
334 #define MCPF_SMBUS_CONFIG_MASTER_RTRY_CNT (0xfL<<16)
335 #define MCPF_SMBUS_CONFIG_TIMESTAMP_CNT_EN (1L<<26)
336 #define MCPF_SMBUS_CONFIG_PROMISCOUS_MODE (1L<<27)
337 #define MCPF_SMBUS_CONFIG_EN_NIC_SMB_ADDR_0 (1L<<28)
338 #define MCPF_SMBUS_CONFIG_BIT_BANG_EN (1L<<29)
339 #define MCPF_SMBUS_CONFIG_SMB_EN (1L<<30)
340 #define MCPF_SMBUS_CONFIG_RESET (1L<<31)
341
342 u32_t mcpf_smbus_timing_config;
343 #define MCPF_SMBUS_TIMING_CONFIG_SMBUS_IDLE_TIME (0xffL<<8)
344 #define MCPF_SMBUS_TIMING_CONFIG_PERIODIC_SLAVE_STRETCH (0xffL<<16)
345 #define MCPF_SMBUS_TIMING_CONFIG_RANDOM_SLAVE_STRETCH (0x7fL<<24)
346 #define MCPF_SMBUS_TIMING_CONFIG_MODE_400 (1L<<31)
347
348 u32_t mcpf_smbus_address;
349 #define MCPF_SMBUS_ADDRESS_NIC_SMB_ADDR0 (0x7fL<<0)
350 #define MCPF_SMBUS_ADDRESS_EN_NIC_SMB_ADDR0 (1L<<7)
351 #define MCPF_SMBUS_ADDRESS_NIC_SMB_ADDR1 (0x7fL<<8)
352 #define MCPF_SMBUS_ADDRESS_EN_NIC_SMB_ADDR1 (1L<<15)
353 #define MCPF_SMBUS_ADDRESS_NIC_SMB_ADDR2 (0x7fL<<16)
354 #define MCPF_SMBUS_ADDRESS_EN_NIC_SMB_ADDR2 (1L<<23)
355 #define MCPF_SMBUS_ADDRESS_NIC_SMB_ADDR3 (0x7fL<<24)
356 #define MCPF_SMBUS_ADDRESS_EN_NIC_SMB_ADDR3 (1L<<31)
357
358 u32_t mcpf_smbus_master_fifo_control;
359 #define MCPF_SMBUS_MASTER_FIFO_CONTROL_MASTER_RX_FIFO_THRESHOLD (0x7fL<<8)
360 #define MCPF_SMBUS_MASTER_FIFO_CONTROL_MASTER_RX_PKT_COUNT (0x7fL<<16)
361 #define MCPF_SMBUS_MASTER_FIFO_CONTROL_MASTER_TX_FIFO_FLUSH (1L<<30)
362 #define MCPF_SMBUS_MASTER_FIFO_CONTROL_MASTER_RX_FIFO_FLUSH (1L<<31)
363
364 u32_t mcpf_smbus_slave_fifo_control;
365 #define MCPF_SMBUS_SLAVE_FIFO_CONTROL_SLAVE_RX_FIFO_THRESHOLD (0x7fL<<8)
366 #define MCPF_SMBUS_SLAVE_FIFO_CONTROL_SLAVE_RX_PKT_COUNT (0x7fL<<16)
367 #define MCPF_SMBUS_SLAVE_FIFO_CONTROL_SLAVE_TX_FIFO_FLUSH (1L<<30)
368 #define MCPF_SMBUS_SLAVE_FIFO_CONTROL_SLAVE_RX_FIFO_FLUSH (1L<<31)
369
370 u32_t mcpf_smbus_bit_bang_control;
371 #define MCPF_SMBUS_BIT_BANG_CONTROL_SMBDAT_OUT_EN (1L<<28)
372 #define MCPF_SMBUS_BIT_BANG_CONTROL_SMBDAT_IN (1L<<29)
373 #define MCPF_SMBUS_BIT_BANG_CONTROL_SMBCLK_OUT_EN (1L<<30)
374 #define MCPF_SMBUS_BIT_BANG_CONTROL_SMBCLK_IN (1L<<31)
375
376 u32_t mcpf_smbus_watchdog;
377 #define MCPF_SMBUS_WATCHDOG_WATCHDOG (0xffffL<<0)
378
379 u32_t mcpf_smbus_heartbeat;
380 #define MCPF_SMBUS_HEARTBEAT_HEARTBEAT (0xffffL<<0)
381
382 u32_t mcpf_smbus_poll_asf;
383 #define MCPF_SMBUS_POLL_ASF_POLL_ASF (0xffffL<<0)
384
385 u32_t mcpf_smbus_poll_legacy;
386 #define MCPF_SMBUS_POLL_LEGACY_POLL_LEGACY (0xffffL<<0)
387
388 u32_t mcpf_smbus_retran;
389 #define MCPF_SMBUS_RETRAN_RETRAN (0xffL<<0)
390
391 u32_t mcpf_smbus_timestamp;
392 #define MCPF_SMBUS_TIMESTAMP_TIMESTAMP (0xffffffffL<<0)
393
394 u32_t mcpf_smbus_master_command;
395 #define MCPF_SMBUS_MASTER_COMMAND_RD_BYTE_COUNT (0xffL<<0)
396 #define MCPF_SMBUS_MASTER_COMMAND_PEC (1L<<8)
397 #define MCPF_SMBUS_MASTER_COMMAND_SMBUS_PROTOCOL (0xfL<<9)
398 #define MCPF_SMBUS_MASTER_COMMAND_SMBUS_PROTOCOL_0000 (0L<<9)
399 #define MCPF_SMBUS_MASTER_COMMAND_SMBUS_PROTOCOL_0001 (1L<<9)
400 #define MCPF_SMBUS_MASTER_COMMAND_SMBUS_PROTOCOL_0010 (2L<<9)
401 #define MCPF_SMBUS_MASTER_COMMAND_SMBUS_PROTOCOL_0011 (3L<<9)
402 #define MCPF_SMBUS_MASTER_COMMAND_SMBUS_PROTOCOL_0100 (4L<<9)
403 #define MCPF_SMBUS_MASTER_COMMAND_SMBUS_PROTOCOL_0101 (5L<<9)
404 #define MCPF_SMBUS_MASTER_COMMAND_SMBUS_PROTOCOL_0110 (6L<<9)
405 #define MCPF_SMBUS_MASTER_COMMAND_SMBUS_PROTOCOL_0111 (7L<<9)
406 #define MCPF_SMBUS_MASTER_COMMAND_SMBUS_PROTOCOL_1000 (8L<<9)
407 #define MCPF_SMBUS_MASTER_COMMAND_SMBUS_PROTOCOL_1001 (9L<<9)
408 #define MCPF_SMBUS_MASTER_COMMAND_SMBUS_PROTOCOL_1010 (10L<<9)
409 #define MCPF_SMBUS_MASTER_COMMAND_SMBUS_PROTOCOL_1011 (11L<<9)
410 #define MCPF_SMBUS_MASTER_COMMAND_STATUS (0x7L<<25)
411 #define MCPF_SMBUS_MASTER_COMMAND_STATUS_000 (0L<<25)
412 #define MCPF_SMBUS_MASTER_COMMAND_STATUS_001 (1L<<25)
413 #define MCPF_SMBUS_MASTER_COMMAND_STATUS_010 (2L<<25)
414 #define MCPF_SMBUS_MASTER_COMMAND_STATUS_011 (3L<<25)
415 #define MCPF_SMBUS_MASTER_COMMAND_STATUS_100 (4L<<25)
416 #define MCPF_SMBUS_MASTER_COMMAND_STATUS_101 (5L<<25)
417 #define MCPF_SMBUS_MASTER_COMMAND_STATUS_110 (6L<<25)
418 #define MCPF_SMBUS_MASTER_COMMAND_STATUS_111 (7L<<25)
419 #define MCPF_SMBUS_MASTER_COMMAND_ABORT (1L<<30)
420 #define MCPF_SMBUS_MASTER_COMMAND_START_BUSY (1L<<31)
421
422 u32_t mcpf_smbus_slave_command;
423 #define MCPF_SMBUS_SLAVE_COMMAND_PEC (1L<<8)
424 #define MCPF_SMBUS_SLAVE_COMMAND_STATUS (0x7L<<23)
425 #define MCPF_SMBUS_SLAVE_COMMAND_STATUS_000 (0L<<23)
426 #define MCPF_SMBUS_SLAVE_COMMAND_STATUS_101 (5L<<23)
427 #define MCPF_SMBUS_SLAVE_COMMAND_STATUS_111 (7L<<23)
428 #define MCPF_SMBUS_SLAVE_COMMAND_ABORT (1L<<30)
429 #define MCPF_SMBUS_SLAVE_COMMAND_START (1L<<31)
430
431 u32_t mcpf_smbus_event_enable;
432 #define MCPF_SMBUS_EVENT_ENABLE_WATCHDOG_TO_EN (1L<<0)
433 #define MCPF_SMBUS_EVENT_ENABLE_HEARTBEAT_TO_EN (1L<<1)
434 #define MCPF_SMBUS_EVENT_ENABLE_POLL_ASF_TO_EN (1L<<2)
435 #define MCPF_SMBUS_EVENT_ENABLE_POLL_LEGACY_TO_EN (1L<<3)
436 #define MCPF_SMBUS_EVENT_ENABLE_RETRANSMIT_TO_EN (1L<<4)
437 #define MCPF_SMBUS_EVENT_ENABLE_SLAVE_ARP_EVENT_EN (1L<<20)
438 #define MCPF_SMBUS_EVENT_ENABLE_SLAVE_RD_EVENT_EN (1L<<21)
439 #define MCPF_SMBUS_EVENT_ENABLE_SLAVE_TX_UNDERRUN_EN (1L<<22)
440 #define MCPF_SMBUS_EVENT_ENABLE_SLAVE_START_BUSY_EN (1L<<23)
441 #define MCPF_SMBUS_EVENT_ENABLE_SLAVE_RX_EVENT_EN (1L<<24)
442 #define MCPF_SMBUS_EVENT_ENABLE_SLAVE_RX_THRESHOLD_HIT_EN (1L<<25)
443 #define MCPF_SMBUS_EVENT_ENABLE_SLAVE_RX_FIFO_FULL_EN (1L<<26)
444 #define MCPF_SMBUS_EVENT_ENABLE_MASTER_TX_UNDERRUN_EN (1L<<27)
445 #define MCPF_SMBUS_EVENT_ENABLE_MASTER_START_BUSY_EN (1L<<28)
446 #define MCPF_SMBUS_EVENT_ENABLE_MASTER_RX_EVENT_EN (1L<<29)
447 #define MCPF_SMBUS_EVENT_ENABLE_MASTER_RX_THRESHOLD_HIT_EN (1L<<30)
448 #define MCPF_SMBUS_EVENT_ENABLE_MASTER_RX_FIFO_FULL_EN (1L<<31)
449
450 u32_t mcpf_smbus_event_status;
451 #define MCPF_SMBUS_EVENT_STATUS_WATCHDOG_TO (1L<<0)
452 #define MCPF_SMBUS_EVENT_STATUS_HEARTBEAT_TO (1L<<1)
453 #define MCPF_SMBUS_EVENT_STATUS_POLL_ASF_TO (1L<<2)
454 #define MCPF_SMBUS_EVENT_STATUS_POLL_LEGACY_TO (1L<<3)
455 #define MCPF_SMBUS_EVENT_STATUS_RETRANSMIT_TO (1L<<4)
456 #define MCPF_SMBUS_EVENT_STATUS_SLAVE_ARP_EVENT (1L<<20)
457 #define MCPF_SMBUS_EVENT_STATUS_SLAVE_RD_EVENT (1L<<21)
458 #define MCPF_SMBUS_EVENT_STATUS_SLAVE_TX_UNDERRUN (1L<<22)
459 #define MCPF_SMBUS_EVENT_STATUS_SLAVE_START_BUSY (1L<<23)
460 #define MCPF_SMBUS_EVENT_STATUS_SLAVE_RX_EVENT (1L<<24)
461 #define MCPF_SMBUS_EVENT_STATUS_SLAVE_RX_THRESHOLD_HIT (1L<<25)
462 #define MCPF_SMBUS_EVENT_STATUS_SLAVE_RX_FIFO_FULL (1L<<26)
463 #define MCPF_SMBUS_EVENT_STATUS_MASTER_TX_UNDERRUN (1L<<27)
464 #define MCPF_SMBUS_EVENT_STATUS_MASTER_START_BUSY (1L<<28)
465 #define MCPF_SMBUS_EVENT_STATUS_MASTER_RX_EVENT (1L<<29)
466 #define MCPF_SMBUS_EVENT_STATUS_MASTER_RX_THRESHOLD_HIT (1L<<30)
467 #define MCPF_SMBUS_EVENT_STATUS_MASTER_RX_FIFO_FULL (1L<<31)
468
469 u32_t mcpf_smbus_master_data_write;
470 #define MCPF_SMBUS_MASTER_DATA_WRITE_MASTER_SMBUS_WR_DATA (0xffL<<0)
471 #define MCPF_SMBUS_MASTER_DATA_WRITE_WR_STATUS (1L<<31)
472
473 u32_t mcpf_smbus_master_data_read;
474 #define MCPF_SMBUS_MASTER_DATA_READ_MASTER_SMBUS_RD_DATA (0xffL<<0)
475 #define MCPF_SMBUS_MASTER_DATA_READ_PEC_ERR (1L<<29)
476 #define MCPF_SMBUS_MASTER_DATA_READ_RD_STATUS (0x3L<<30)
477 #define MCPF_SMBUS_MASTER_DATA_READ_RD_STATUS_00 (0L<<30)
478 #define MCPF_SMBUS_MASTER_DATA_READ_RD_STATUS_01 (1L<<30)
479 #define MCPF_SMBUS_MASTER_DATA_READ_RD_STATUS_10 (2L<<30)
480 #define MCPF_SMBUS_MASTER_DATA_READ_RD_STATUS_11 (3L<<30)
481
482 u32_t mcpf_smbus_slave_data_write;
483 #define MCPF_SMBUS_SLAVE_DATA_WRITE_SLAVE_SMBUS_WR_DATA (0xffL<<0)
484 #define MCPF_SMBUS_SLAVE_DATA_WRITE_WR_STATUS (1L<<31)
485 #define MCPF_SMBUS_SLAVE_DATA_WRITE_WR_STATUS_0 (0L<<31)
486 #define MCPF_SMBUS_SLAVE_DATA_WRITE_WR_STATUS_1 (1L<<31)
487
488 u32_t mcpf_smbus_slave_data_read;
489 #define MCPF_SMBUS_SLAVE_DATA_READ_SLAVE_SMBUS_RD_DATA (0xffL<<0)
490 #define MCPF_SMBUS_SLAVE_DATA_READ_ERR_STATUS (0x3L<<28)
491 #define MCPF_SMBUS_SLAVE_DATA_READ_ERR_STATUS_00 (0L<<28)
492 #define MCPF_SMBUS_SLAVE_DATA_READ_ERR_STATUS_01 (1L<<28)
493 #define MCPF_SMBUS_SLAVE_DATA_READ_ERR_STATUS_10 (2L<<28)
494 #define MCPF_SMBUS_SLAVE_DATA_READ_ERR_STATUS_11 (3L<<28)
495 #define MCPF_SMBUS_SLAVE_DATA_READ_RD_STATUS (0x3L<<30)
496 #define MCPF_SMBUS_SLAVE_DATA_READ_RD_STATUS_00 (0L<<30)
497 #define MCPF_SMBUS_SLAVE_DATA_READ_RD_STATUS_01 (1L<<30)
498 #define MCPF_SMBUS_SLAVE_DATA_READ_RD_STATUS_10 (2L<<30)
499 #define MCPF_SMBUS_SLAVE_DATA_READ_RD_STATUS_11 (3L<<30)
500
501 u32_t mcpf_smbus_smb_unused_1[12];
502 u32_t mcpf_smbus_arp_state;
503 #define MCPF_SMBUS_ARP_STATE_AV_FLAG0 (1L<<0)
504 #define MCPF_SMBUS_ARP_STATE_AR_FLAG0 (1L<<1)
505 #define MCPF_SMBUS_ARP_STATE_AV_FLAG1 (1L<<4)
506 #define MCPF_SMBUS_ARP_STATE_AR_FLAG1 (1L<<5)
507
508 u32_t mcpf_smbus_smb_unused_2[3];
509 u32_t mcpf_smbus_udid0_3;
510 #define MCPF_SMBUS_UDID0_3_BYTE_12 (0xffL<<0)
511 #define MCPF_SMBUS_UDID0_3_BYTE_13 (0xffL<<8)
512 #define MCPF_SMBUS_UDID0_3_BYTE_14 (0xffL<<16)
513 #define MCPF_SMBUS_UDID0_3_BYTE_15 (0xffL<<24)
514
515 u32_t mcpf_smbus_udid0_2;
516 #define MCPF_SMBUS_UDID0_2_BYTE_8 (0xffL<<0)
517 #define MCPF_SMBUS_UDID0_2_BYTE_9 (0xffL<<8)
518 #define MCPF_SMBUS_UDID0_2_BYTE_10 (0xffL<<16)
519 #define MCPF_SMBUS_UDID0_2_BYTE_11 (0xffL<<24)
520
521 u32_t mcpf_smbus_udid0_1;
522 #define MCPF_SMBUS_UDID0_1_BYTE_4 (0xffL<<0)
523 #define MCPF_SMBUS_UDID0_1_BYTE_5 (0xffL<<8)
524 #define MCPF_SMBUS_UDID0_1_BYTE_6 (0xffL<<16)
525 #define MCPF_SMBUS_UDID0_1_BYTE_7 (0xffL<<24)
526
527 u32_t mcpf_smbus_udid0_0;
528 #define MCPF_SMBUS_UDID0_0_BYTE_0 (0xffL<<0)
529 #define MCPF_SMBUS_UDID0_0_BYTE_1 (0xffL<<8)
530 #define MCPF_SMBUS_UDID0_0_BYTE_2 (0xffL<<16)
531 #define MCPF_SMBUS_UDID0_0_BYTE_3 (0xffL<<24)
532
533 u32_t mcpf_smbus_udid1_3;
534 #define MCPF_SMBUS_UDID1_3_BYTE_12 (0xffL<<0)
535 #define MCPF_SMBUS_UDID1_3_BYTE_13 (0xffL<<8)
536 #define MCPF_SMBUS_UDID1_3_BYTE_14 (0xffL<<16)
537 #define MCPF_SMBUS_UDID1_3_BYTE_15 (0xffL<<24)
538
539 u32_t mcpf_smbus_udid1_2;
540 #define MCPF_SMBUS_UDID1_2_BYTE_8 (0xffL<<0)
541 #define MCPF_SMBUS_UDID1_2_BYTE_9 (0xffL<<8)
542 #define MCPF_SMBUS_UDID1_2_BYTE_10 (0xffL<<16)
543 #define MCPF_SMBUS_UDID1_2_BYTE_11 (0xffL<<24)
544
545 u32_t mcpf_smbus_udid1_1;
546 #define MCPF_SMBUS_UDID1_1_BYTE_4 (0xffL<<0)
547 #define MCPF_SMBUS_UDID1_1_BYTE_5 (0xffL<<8)
548 #define MCPF_SMBUS_UDID1_1_BYTE_6 (0xffL<<16)
549 #define MCPF_SMBUS_UDID1_1_BYTE_7 (0xffL<<24)
550
551 u32_t mcpf_smbus_udid1_0;
552 #define MCPF_SMBUS_UDID1_0_BYTE_0 (0xffL<<0)
553 #define MCPF_SMBUS_UDID1_0_BYTE_1 (0xffL<<8)
554 #define MCPF_SMBUS_UDID1_0_BYTE_2 (0xffL<<16)
555 #define MCPF_SMBUS_UDID1_0_BYTE_3 (0xffL<<24)
556
557 u32_t mcpf_smbus_smb_unused_3[211];
558 u32_t mcpf_smbus_smb_reg_end;
559 u32_t mcpf_unused_h[512];
560 u32_t mcpf_m2p_status;
561 #define MCPF_M2P_STATUS_M2P_BUSY (1L<<0)
562 #define MCPF_M2P_STATUS_M2P_PKT_INUSE_ERROR (1L<<1)
563 #define MCPF_M2P_STATUS_M2P_PKT_OVERFLOW_ERROR (1L<<2)
564 #define MCPF_M2P_STATUS_M2P_PKT_UNDERFLOW_ERROR (1L<<3)
565 #define MCPF_M2P_STATUS_M2P_ZERO_LENGTH_ERROR (1L<<4)
566 #define MCPF_M2P_STATUS_M2P_DATA_SM (0x3L<<8)
567 #define MCPF_M2P_STATUS_M2P_PKT_FIFO_STATUS (0x3fL<<16)
568
569 u32_t mcpf_m2p_command;
570 #define MCPF_M2P_COMMAND_SEND_PKT_TO_PXP (1L<<0)
571
572 u32_t mcpf_m2p_vdm_length;
573 #define MCPF_M2P_VDM_LENGTH_VDM_LENGTH (0x7fL<<0)
574
575 u32_t mcpf_m2p_pci_id;
576 #define MCPF_M2P_PCI_ID_PCI_ID (0xffffL<<0)
577
578 u32_t mcpf_m2p_vendor_id;
579 #define MCPF_M2P_VENDOR_ID_VENDOR_ID (0xffffL<<0)
580
581 u32_t mcpf_m2p_vq_id;
582 #define MCPF_M2P_VQ_ID_VQR_ID (0x1fL<<0)
583
584 u32_t mcpf_m2p_src_fid;
585 #define MCPF_M2P_SRC_FID_SRC_FID (0xffffL<<0)
586
587 u32_t mcpf_m2p_route_type;
588 #define MCPF_M2P_ROUTE_TYPE_ROUTE_TYPE (0x7L<<0)
589
590 u32_t mcpf_m2p_tag;
591 #define MCPF_M2P_TAG_TAG (0xffL<<0)
592
593 u32_t mcpf_m2p_vendor_dword;
594 #define MCPF_M2P_VENDOR_DWORD_VENDOR_DWORD (0xffffffffL<<0)
595
596 u32_t mcpf_m2p_path_id;
597 #define MCPF_M2P_PATH_ID_PATH_ID (1L<<0)
598
599 u32_t mcpf_m2p_tx_data_fifo;
600 #define MCPF_M2P_TX_DATA_FIFO_FIFO_DATA (0xffffffffL<<0)
601
602 u32_t mcpf_m2p_unused[51];
603 u32_t mcpf_m2p_reg_end;
604 u32_t mcpf_p2m_status;
605 #define MCPF_P2M_STATUS_PKT_HDR_CNT (0x7fL<<0)
606 #define MCPF_P2M_STATUS_RESERVED1 (0x1ffL<<7)
607 #define MCPF_P2M_STATUS_PKT_DATA_CNT (0x1ffL<<16)
608 #define MCPF_P2M_STATUS_RESERVED2 (0x3fL<<25)
609 #define MCPF_P2M_STATUS_P2M_ATTN_BIT (1L<<31)
610
611 u32_t mcpf_p2m_config;
612 #define MCPF_P2M_CONFIG_BACKPRESSURE_MODE (1L<<0)
613 #define MCPF_P2M_CONFIG_DRAIN_MODE (1L<<1)
614 #define MCPF_P2M_CONFIG_VID_FILTER_DISCARD (1L<<2)
615 #define MCPF_P2M_CONFIG_RESERVED (0x1fffffffL<<3)
616
617 u32_t mcpf_p2m_vid_filt_config_0;
618 #define MCPF_P2M_VID_FILT_CONFIG_0_VID_FILT_VENDORID (0xffffL<<0)
619 #define MCPF_P2M_VID_FILT_CONFIG_0_VID_FILT_DISCARD (1L<<16)
620 #define MCPF_P2M_VID_FILT_CONFIG_0_VID_FILT_ENABLE (1L<<17)
621
622 u32_t mcpf_p2m_vid_filt_config_1;
623 #define MCPF_P2M_VID_FILT_CONFIG_1_VID_FILT_VENDORID (0xffffL<<0)
624 #define MCPF_P2M_VID_FILT_CONFIG_1_VID_FILT_DISCARD (1L<<16)
625 #define MCPF_P2M_VID_FILT_CONFIG_1_VID_FILT_ENABLE (1L<<17)
626
627 u32_t mcpf_p2m_tag_filt_config;
628 #define MCPF_P2M_TAG_FILT_CONFIG_TAG_FILT_VALUE (0xffL<<0)
629 #define MCPF_P2M_TAG_FILT_CONFIG_TAG_FILT_MASK (0xffL<<8)
630 #define MCPF_P2M_TAG_FILT_CONFIG_TAG_FILT_DISCARD (1L<<16)
631
632 u32_t mcpf_p2m_length_filt_config;
633 #define MCPF_P2M_LENGTH_FILT_CONFIG_LENGTH_MIN_VALUE (0x7fL<<0)
634 #define MCPF_P2M_LENGTH_FILT_CONFIG_TAG_FILT_MASK (0x7fL<<8)
635
636 u32_t mcpf_p2m_discard_stat_vendorid;
637 #define MCPF_P2M_DISCARD_STAT_VENDORID_DISCARD_STAT_VENDORID (0xffffffffL<<0)
638
639 u32_t mcpf_p2m_discard_stat_tag;
640 #define MCPF_P2M_DISCARD_STAT_TAG_DISCARD_STAT_TAG (0xffffffffL<<0)
641
642 u32_t mcpf_p2m_discard_stat_length;
643 #define MCPF_P2M_DISCARD_STAT_LENGTH_DISCARD_STAT_LENGTH (0xffffffffL<<0)
644
645 u32_t mcpf_p2m_drop_stat;
646 #define MCPF_P2M_DROP_STAT_DROP_STAT (0xffffffffL<<0)
647
648 u32_t mcpf_p2m_rcvd_stat;
649 #define MCPF_P2M_RCVD_STAT_RCVD_STAT (0xffffffffL<<0)
650
651 u32_t mcpf_p2m_hdr_single_reg;
652 #define MCPF_P2M_HDR_SINGLE_REG_HEADER_SINGLE_REG_MODE (0xffffffffL<<0)
653
654 u32_t mcpf_p2m_hdr_fifo_0;
655 #define MCPF_P2M_HDR_FIFO_0_HEADER_0 (0xffffffffL<<0)
656
657 u32_t mcpf_p2m_hdr_fifo_1;
658 #define MCPF_P2M_HDR_FIFO_1_HEADER_1 (0xffffffffL<<0)
659
660 u32_t mcpf_p2m_hdr_fifo_2;
661 #define MCPF_P2M_HDR_FIFO_2_HEADER_2 (0xffffffffL<<0)
662
663 u32_t mcpf_p2m_hdr_fifo_3;
664 #define MCPF_P2M_HDR_FIFO_3_HEADER_3 (0x7L<<0)
665 #define MCPF_P2M_HDR_FIFO_3_RESERVED (0x1fffffffL<<3)
666
667 u32_t mcpf_p2m_data_fifo;
668 #define MCPF_P2M_DATA_FIFO_DATA (0xffffffffL<<0)
669
670 u32_t mcpf_p2m_vdm_length;
671 #define MCPF_P2M_VDM_LENGTH_VDM_LENGTH (0x7fL<<0)
672
673 u32_t mcpf_p2m_pci_req_id;
674 #define MCPF_P2M_PCI_REQ_ID_PCI_REQ_ID (0xffffL<<0)
675
676 u32_t mcpf_p2m_vendor_id;
677 #define MCPF_P2M_VENDOR_ID_VENDOR_ID (0xffffL<<0)
678
679 u32_t mcpf_p2m_fid;
680 #define MCPF_P2M_FID_FID (0xffffL<<0)
681
682 u32_t mcpf_p2m_vendor_dword;
683 #define MCPF_P2M_VENDOR_DWORD_VENDOR_DWORD (0xffffffffL<<0)
684
685 u32_t mcpf_p2m_other_hdr_fields;
686 #define MCPF_P2M_OTHER_HDR_FIELDS_PATH_ID (1L<<0)
687 #define MCPF_P2M_OTHER_HDR_FIELDS_ROUTING_FIELD (0x7L<<4)
688 #define MCPF_P2M_OTHER_HDR_FIELDS_TAG (0xffL<<16)
689
690 u32_t mcpf_p2m_unused[40];
691 u32_t mcpf_p2m_reg_end;
692 u32_t mcpf_cache_pim_nvram_base;
693 u32_t mcpf_cache_paging_enable;
694 #define MCPF_CACHE_PAGING_ENABLE_ENABLE (1L<<0)
695
696 u32_t mcpf_cache_fetch_completion;
697 u32_t mcpf_cache_cache_ctrl_status_0;
698 #define MCPF_CACHE_CACHE_CTRL_STATUS_0_LOCK (1L<<0)
699 #define MCPF_CACHE_CACHE_CTRL_STATUS_0_ACTIVE (1L<<1)
700 #define MCPF_CACHE_CACHE_CTRL_STATUS_0_VALID (1L<<2)
701 #define MCPF_CACHE_CACHE_CTRL_STATUS_0_NVRAM_PAGE_OFFSET (0x1ffL<<3)
702
703 u32_t mcpf_cache_cache_ctrl_status_1;
704 #define MCPF_CACHE_CACHE_CTRL_STATUS_1_LOCK (1L<<0)
705 #define MCPF_CACHE_CACHE_CTRL_STATUS_1_ACTIVE (1L<<1)
706 #define MCPF_CACHE_CACHE_CTRL_STATUS_1_VALID (1L<<2)
707 #define MCPF_CACHE_CACHE_CTRL_STATUS_1_NVRAM_PAGE_OFFSET (0x1ffL<<3)
708
709 u32_t mcpf_cache_cache_ctrl_status_2;
710 #define MCPF_CACHE_CACHE_CTRL_STATUS_2_LOCK (1L<<0)
711 #define MCPF_CACHE_CACHE_CTRL_STATUS_2_ACTIVE (1L<<1)
712 #define MCPF_CACHE_CACHE_CTRL_STATUS_2_VALID (1L<<2)
713 #define MCPF_CACHE_CACHE_CTRL_STATUS_2_NVRAM_PAGE_OFFSET (0x1ffL<<3)
714
715 u32_t mcpf_cache_cache_ctrl_status_3;
716 #define MCPF_CACHE_CACHE_CTRL_STATUS_3_LOCK (1L<<0)
717 #define MCPF_CACHE_CACHE_CTRL_STATUS_3_ACTIVE (1L<<1)
718 #define MCPF_CACHE_CACHE_CTRL_STATUS_3_VALID (1L<<2)
719 #define MCPF_CACHE_CACHE_CTRL_STATUS_3_NVRAM_PAGE_OFFSET (0x1ffL<<3)
720
721 u32_t mcpf_cache_cache_ctrl_status_4;
722 #define MCPF_CACHE_CACHE_CTRL_STATUS_4_LOCK (1L<<0)
723 #define MCPF_CACHE_CACHE_CTRL_STATUS_4_ACTIVE (1L<<1)
724 #define MCPF_CACHE_CACHE_CTRL_STATUS_4_VALID (1L<<2)
725 #define MCPF_CACHE_CACHE_CTRL_STATUS_4_NVRAM_PAGE_OFFSET (0x1ffL<<3)
726
727 u32_t mcpf_cache_cache_ctrl_status_5;
728 #define MCPF_CACHE_CACHE_CTRL_STATUS_5_LOCK (1L<<0)
729 #define MCPF_CACHE_CACHE_CTRL_STATUS_5_ACTIVE (1L<<1)
730 #define MCPF_CACHE_CACHE_CTRL_STATUS_5_VALID (1L<<2)
731 #define MCPF_CACHE_CACHE_CTRL_STATUS_5_NVRAM_PAGE_OFFSET (0x1ffL<<3)
732
733 u32_t mcpf_cache_cache_ctrl_status_6;
734 #define MCPF_CACHE_CACHE_CTRL_STATUS_6_LOCK (1L<<0)
735 #define MCPF_CACHE_CACHE_CTRL_STATUS_6_ACTIVE (1L<<1)
736 #define MCPF_CACHE_CACHE_CTRL_STATUS_6_VALID (1L<<2)
737 #define MCPF_CACHE_CACHE_CTRL_STATUS_6_NVRAM_PAGE_OFFSET (0x1ffL<<3)
738
739 u32_t mcpf_cache_cache_ctrl_status_7;
740 #define MCPF_CACHE_CACHE_CTRL_STATUS_7_LOCK (1L<<0)
741 #define MCPF_CACHE_CACHE_CTRL_STATUS_7_ACTIVE (1L<<1)
742 #define MCPF_CACHE_CACHE_CTRL_STATUS_7_VALID (1L<<2)
743 #define MCPF_CACHE_CACHE_CTRL_STATUS_7_NVRAM_PAGE_OFFSET (0x1ffL<<3)
744
745 u32_t mcpf_cache_cache_ctrl_status_8;
746 #define MCPF_CACHE_CACHE_CTRL_STATUS_8_LOCK (1L<<0)
747 #define MCPF_CACHE_CACHE_CTRL_STATUS_8_ACTIVE (1L<<1)
748 #define MCPF_CACHE_CACHE_CTRL_STATUS_8_VALID (1L<<2)
749 #define MCPF_CACHE_CACHE_CTRL_STATUS_8_NVRAM_PAGE_OFFSET (0x1ffL<<3)
750
751 u32_t mcpf_cache_cache_ctrl_status_9;
752 #define MCPF_CACHE_CACHE_CTRL_STATUS_9_LOCK (1L<<0)
753 #define MCPF_CACHE_CACHE_CTRL_STATUS_9_ACTIVE (1L<<1)
754 #define MCPF_CACHE_CACHE_CTRL_STATUS_9_VALID (1L<<2)
755 #define MCPF_CACHE_CACHE_CTRL_STATUS_9_NVRAM_PAGE_OFFSET (0x1ffL<<3)
756
757 u32_t mcpf_cache_cache_ctrl_status_10;
758 #define MCPF_CACHE_CACHE_CTRL_STATUS_10_LOCK (1L<<0)
759 #define MCPF_CACHE_CACHE_CTRL_STATUS_10_ACTIVE (1L<<1)
760 #define MCPF_CACHE_CACHE_CTRL_STATUS_10_VALID (1L<<2)
761 #define MCPF_CACHE_CACHE_CTRL_STATUS_10_NVRAM_PAGE_OFFSET (0x1ffL<<3)
762
763 u32_t mcpf_cache_cache_ctrl_status_11;
764 #define MCPF_CACHE_CACHE_CTRL_STATUS_11_LOCK (1L<<0)
765 #define MCPF_CACHE_CACHE_CTRL_STATUS_11_ACTIVE (1L<<1)
766 #define MCPF_CACHE_CACHE_CTRL_STATUS_11_VALID (1L<<2)
767 #define MCPF_CACHE_CACHE_CTRL_STATUS_11_NVRAM_PAGE_OFFSET (0x1ffL<<3)
768
769 u32_t mcpf_cache_cache_ctrl_status_12;
770 #define MCPF_CACHE_CACHE_CTRL_STATUS_12_LOCK (1L<<0)
771 #define MCPF_CACHE_CACHE_CTRL_STATUS_12_ACTIVE (1L<<1)
772 #define MCPF_CACHE_CACHE_CTRL_STATUS_12_VALID (1L<<2)
773 #define MCPF_CACHE_CACHE_CTRL_STATUS_12_NVRAM_PAGE_OFFSET (0x1ffL<<3)
774
775 u32_t mcpf_cache_cache_ctrl_status_13;
776 #define MCPF_CACHE_CACHE_CTRL_STATUS_13_LOCK (1L<<0)
777 #define MCPF_CACHE_CACHE_CTRL_STATUS_13_ACTIVE (1L<<1)
778 #define MCPF_CACHE_CACHE_CTRL_STATUS_13_VALID (1L<<2)
779 #define MCPF_CACHE_CACHE_CTRL_STATUS_13_NVRAM_PAGE_OFFSET (0x1ffL<<3)
780
781 u32_t mcpf_cache_cache_ctrl_status_14;
782 #define MCPF_CACHE_CACHE_CTRL_STATUS_14_LOCK (1L<<0)
783 #define MCPF_CACHE_CACHE_CTRL_STATUS_14_ACTIVE (1L<<1)
784 #define MCPF_CACHE_CACHE_CTRL_STATUS_14_VALID (1L<<2)
785 #define MCPF_CACHE_CACHE_CTRL_STATUS_14_NVRAM_PAGE_OFFSET (0x1ffL<<3)
786
787 u32_t mcpf_cache_cache_ctrl_status_15;
788 #define MCPF_CACHE_CACHE_CTRL_STATUS_15_LOCK (1L<<0)
789 #define MCPF_CACHE_CACHE_CTRL_STATUS_15_ACTIVE (1L<<1)
790 #define MCPF_CACHE_CACHE_CTRL_STATUS_15_VALID (1L<<2)
791 #define MCPF_CACHE_CACHE_CTRL_STATUS_15_NVRAM_PAGE_OFFSET (0x1ffL<<3)
792
793 u32_t mcpf_cache_img_loader_baddr;
794 #define MCPF_CACHE_IMG_LOADER_BADDR_VALUE (0x7fffffL<<2)
795
796 u32_t mcpf_cache_img_loader_gaddr;
797 #define MCPF_CACHE_IMG_LOADER_GADDR_VALUE (0x7fffffL<<2)
798
799 u32_t mcpf_cache_img_loader_caddr;
800 #define MCPF_CACHE_IMG_LOADER_CADDR_VALUE (0x7fffffL<<2)
801
802 u32_t mcpf_cache_img_loader_cdata;
803 #define MCPF_CACHE_IMG_LOADER_CDATA_VALUE (0x7fffffL<<2)
804
805 u32_t mcpf_cache_img_loader_cfg;
806 #define MCPF_CACHE_IMG_LOADER_CFG_VALUE (0x7fffffL<<2)
807
808 u32_t mcpf_cache_stat_hit_counter;
809 u32_t mcpf_cache_stat_miss_counter;
810 u32_t mcpf_cache_last_page_0;
811 #define MCPF_CACHE_LAST_PAGE_0_VALID (1L<<0)
812 #define MCPF_CACHE_LAST_PAGE_0_IS_LAST (1L<<1)
813 #define MCPF_CACHE_LAST_PAGE_0_PAGE_INDEX (0xfL<<2)
814 #define MCPF_CACHE_LAST_PAGE_0_PAGE_OFFSET (0x1ffL<<6)
815
816 u32_t mcpf_cache_last_page_1;
817 #define MCPF_CACHE_LAST_PAGE_1_VALID (1L<<0)
818 #define MCPF_CACHE_LAST_PAGE_1_IS_LAST (1L<<1)
819 #define MCPF_CACHE_LAST_PAGE_1_PAGE_INDEX (0xfL<<2)
820 #define MCPF_CACHE_LAST_PAGE_1_PAGE_OFFSET (0x1ffL<<6)
821
822 u32_t mcpf_cache_page_fetch_state;
823 u32_t mcpf_cache_cache_error_status;
824 #define MCPF_CACHE_CACHE_ERROR_STATUS_OUT_OF_BOUNDS_READ (1L<<0)
825 #define MCPF_CACHE_CACHE_ERROR_STATUS_ILLEGAL_FETCH (1L<<1)
826
827 u32_t mcpf_cache_cache_unused[33];
828 u32_t mcpf_cache_reg_end;
829 u32_t mcpf_unused_i[1088];
830 u32_t mcpf_to_bmb_fifo_command;
831 #define MCPF_TO_BMB_FIFO_COMMAND_FLUSH (1L<<0)
832 #define MCPF_TO_BMB_FIFO_COMMAND_ERROR (1L<<1)
833 #define MCPF_TO_BMB_FIFO_COMMAND_PKT_TC (0xfL<<4)
834 #define MCPF_TO_BMB_FIFO_COMMAND_PKT_LEN (0xffffL<<16)
835
836 u32_t mcpf_to_bmb_fifo_status;
837 #define MCPF_TO_BMB_FIFO_STATUS_WRITE_DONE (1L<<0)
838
839 u32_t mcpf_to_bmb_fifo_wr_data;
840 u32_t mcpf_bmb_unused_1;
841 u32_t mcpf_to_bmb_fifo_sop_dscr0;
842 u32_t mcpf_to_bmb_fifo_sop_dscr1;
843 u32_t mcpf_to_bmb_fifo_sop_dscr2;
844 u32_t mcpf_to_bmb_fifo_sop_dscr3;
845 u32_t mcpf_frm_bmb_fifo_command;
846 #define MCPF_FRM_BMB_FIFO_COMMAND_READ_DONE (1L<<0)
847 #define MCPF_FRM_BMB_FIFO_COMMAND_FLUSH (1L<<4)
848 #define MCPF_FRM_BMB_FIFO_COMMAND_CLR_PKT_COUNTERS (1L<<5)
849
850 u32_t mcpf_frm_bmb_fifo_status;
851 #define MCPF_FRM_BMB_FIFO_STATUS_BUSY (1L<<0)
852 #define MCPF_FRM_BMB_FIFO_STATUS_PKT_TC0 (0x3L<<2)
853 #define MCPF_FRM_BMB_FIFO_STATUS_DATA_VALID (1L<<4)
854 #define MCPF_FRM_BMB_FIFO_STATUS_SOP (1L<<5)
855 #define MCPF_FRM_BMB_FIFO_STATUS_EOP (1L<<6)
856 #define MCPF_FRM_BMB_FIFO_STATUS_ERR (1L<<7)
857 #define MCPF_FRM_BMB_FIFO_STATUS_BYTE_VALID (0x3L<<8)
858 #define MCPF_FRM_BMB_FIFO_STATUS_BYTE_VALID_0 (0L<<8)
859 #define MCPF_FRM_BMB_FIFO_STATUS_BYTE_VALID_1 (1L<<8)
860 #define MCPF_FRM_BMB_FIFO_STATUS_BYTE_VALID_2 (2L<<8)
861 #define MCPF_FRM_BMB_FIFO_STATUS_BYTE_VALID_3 (3L<<8)
862 #define MCPF_FRM_BMB_FIFO_STATUS_PKT_TC1 (0x3L<<10)
863 #define MCPF_FRM_BMB_FIFO_STATUS_PKT_PORT (0xfL<<12)
864 #define MCPF_FRM_BMB_FIFO_STATUS_PKT_LEN (0xffffL<<16)
865
866 u32_t mcpf_bmb_unused_2;
867 u32_t mcpf_frm_bmb_fifo_rd_data;
868 u32_t mcpf_frm_bmb_fifo_sop_dscr0;
869 u32_t mcpf_frm_bmb_fifo_sop_dscr1;
870 u32_t mcpf_frm_bmb_fifo_sop_dscr2;
871 u32_t mcpf_frm_bmb_fifo_sop_dscr3;
872 u32_t mcpf_bmb_unused_3[239];
873 u32_t mcpf_bmb_reg_end;
874 u32_t mcpf_unused_j[87808];
875 } mcp_fio_t;
876
877 #endif /* MCP_FIO_H */