1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License, v.1, (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://opensource.org/licenses/CDDL-1.0.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright 2014-2017 Cavium, Inc.
24 * The contents of this file are subject to the terms of the Common Development
25 * and Distribution License, v.1, (the "License").
26
27 * You may not use this file except in compliance with the License.
28
29 * You can obtain a copy of the License at available
30 * at http://opensource.org/licenses/CDDL-1.0
31
32 * See the License for the specific language governing permissions and
33 * limitations under the License.
34 */
35
36
37 #ifndef MISC_BITS_H
38 #define MISC_BITS_H
39
40 /*reset_config*/
41 #define MISCS_REGISTERS_RESET_CONFIG_NCSI (0x1<<0)
42 #define MISCS_REGISTERS_RESET_CONFIG_UMAC (0x1<<1)
43 #define MISCS_REGISTERS_RESET_CONFIG_MSTAT (0x1<<2)
44 #define MISCS_REGISTERS_RESET_CONFIG_CPMU (0x1<<3)
45 #define MISCS_REGISTERS_RESET_CONFIG_PXPV_AUTO_MODE (0x1<<4)
46 #define MISCS_REGISTERS_RESET_CONFIG_NWM_MAC_CORE (0x1<<5)
47 #define MISCS_REGISTERS_RESET_CONFIG_RSRV6 (0x1<<6)
48 #define MISCS_REGISTERS_RESET_CONFIG_RST_MCP_N_RESET_REG_HARD_CORE_AUTO_MODE (0x1<<7)
49 #define MISCS_REGISTERS_RESET_CONFIG_RST_MCP_N_HARD_CORE_RST_B_AUTO_MODE (0x1<<8)
50 #define MISCS_REGISTERS_RESET_CONFIG_RST_MCP_N_RESET_CMN_CPU_AUTO_MODE (0x1<<9)
51 #define MISCS_REGISTERS_RESET_CONFIG_RST_MCP_N_RESET_CMN_CORE_AUTO_MODE (0x1<<10)
52 #define MISCS_REGISTERS_RESET_CONFIG_RSRV11 (0x1<<11)
53 #define MISCS_REGISTERS_RESET_CONFIG_RSRV12 (0x1<<12)
54 #define MISCS_REGISTERS_RESET_CONFIG_RSRV13 (0x1<<13)
55 #define MISCS_REGISTERS_RESET_CONFIG_RST_MISC_CORE_AUTO_MODE (0x1<<14)
56 #define MISCS_REGISTERS_RESET_CONFIG_RST_DBUE_AUTO_MODE (0x1<<15)
57 #define MISCS_REGISTERS_RESET_CONFIG_GRC_RESET_ASSERT_ON_CORE_RST (0x1<<16)
58 #define MISCS_REGISTERS_RESET_CONFIG_RST_MCP_N_RESET_CMN_CPU_ASSERT_ON_CORE_RST (0x1<<17)
59 #define MISCS_REGISTERS_RESET_CONFIG_RST_MCP_N_RESET_CMN_CORE_ASSERT_ON_CORE_RST (0x1<<18)
60 #define MISCS_REGISTERS_RESET_CONFIG_RST_RBCN_ASSERT_ON_CORE_RST (0x1<<19)
61 #define MISCS_REGISTERS_RESET_CONFIG_NWM_CORE (0x1<<20)
62 #define MISCS_REGISTERS_RESET_CONFIG_RST_MISC_CORE_ASSERT_ON_CORE_RST (0x1<<21)
63 #define MISCS_REGISTERS_RESET_CONFIG_RST_DBUE_ASSERT_ON_CORE_RST (0x1<<22)
64 #define MISCS_REGISTERS_RESET_CONFIG_WRAPPERS_IDDQ_AND_RST_SIGNALS_ASSERT_ON_CORE_RST (0x1<<23)
65 #define MISCS_REGISTERS_RESET_CONFIG_RBCW (0x1<<24)
66 #define MISCS_REGISTERS_RESET_CONFIG_RST_PGLC_AUTO_MODE (0x1<<25)
67 #define MISCS_REGISTERS_RESET_CONFIG_RST_BMB_ON_CORE_RST (0x1<<26)
68 #define MISCS_REGISTERS_RESET_CONFIG_RST_OPTE_ON_CORE_RST (0x1<<27)
69 #define MISCS_REGISTERS_RESET_CONFIG_OPCS (0x1<<28)
70 #define MISCS_REGISTERS_RESET_CONFIG_NWS (0x1<<29)
71 #define MISCS_REGISTERS_RESET_CONFIG_MS (0x1<<30)
72 #define MISCS_REGISTERS_RESET_CONFIG_LED (0x1<<31)
73
74 /* MISCS_REG_RESET_PL_UA */
75 #define MISCS_REG_RESET_PL_UA_SET (MISCS_REG_RESET_PL_UA + 4)
76 #define MISCS_REG_RESET_PL_UA_CLEAR (MISCS_REG_RESET_PL_UA + 8)
77 #define MISCS_REG_RESET_PL_UA_RST_GRC (0x1<<0)
78 #define MISCS_REG_RESET_PL_UA_RST_MCP_N_RESET_REG_HARD_CORE (0x1<<1)
79 #define MISCS_REG_RESET_PL_UA_RST_MCP_N_HARD_CORE_RST_B (0x1<<2)
80 #define MISCS_REG_RESET_PL_UA_RST_MCP_N_RESET_CMN_CPU (0x1<<3)
81 #define MISCS_REG_RESET_PL_UA_RST_MCP_N_RESET_CMN_CORE (0x1<<4)
82 #define MISCS_REG_RESET_PL_UA_RST_MISC_CORE (0x1<<5)
83 #define MISCS_REG_RESET_PL_UA_RST_DBUE_UART (0x1<<6)
84 #define MISCS_REG_RESET_PL_UA_RST_BMB (0x1<<7)
85 #define MISCS_REG_RESET_PL_UA_RST_IPC (0x1<<8)
86 #define MISCS_REG_RESET_PL_UA_RST_CRBCN (0x1<<9)
87
88 #define MISCS_REG_RESET_PL_UA_PROCESS_KILL (0x0)
89
90 #define MISCS_REG_RESET_PL_HV_SET (MISCS_REG_RESET_PL_HV + 4)
91 #define MISCS_REG_RESET_PL_HV_CLEAR (MISCS_REG_RESET_PL_HV + 8)
92 #define MISCS_REG_RESET_PL_HV_RST_CNIG (0x1<<0)
93 #define MISCS_REG_RESET_PL_HV_RST_PGLC (0x1<<1)
94 #define MISCS_REG_RESET_PL_HV_RST_PXPV (0x1<<2)
95 #define MISCS_REG_RESET_PL_HV_RST_CRBCH (0x1<<3)
96 #define MISCS_REG_RESET_PL_HV_RST_OPTE (0x1<<4)
97 #define MISCS_REG_RESET_PL_HV_RST_NCSI (0x1<<5)
98 #define MISCS_REG_RESET_PL_HV_RST_UMAC (0x1<<6)
99 #define MISCS_REG_RESET_PL_HV_RST_MSTAT (0x1<<7)
100 #define MISCS_REG_RESET_PL_HV_RST_CPMU (0x1<<8)
101 #define MISCS_REG_RESET_PL_HV_RST_RSRV (0x1<<9)
102 #define MISCS_REG_RESET_PL_HV_RST_RBCW (0x1<<10)
103 #define MISCS_REG_RESET_PL_HV_RST_OPCS (0x1<<11)
104 #define MISCS_REG_RESET_PL_HV_RST_NWS (0x1<<12)
105 #define MISCS_REG_RESET_PL_HV_RST_MS (0x1<<13)
106 #define MISCS_REG_RESET_PL_HV_RST_LED (0x1<<14)
107
108
109
110 #define MISCS_REG_RESET_PL_HV_PROCESS_KILL (0x0)
111
112 /* MISC_REG_RESET_PL_UA */
113 #define MISC_REG_RESET_PL_UA_SET (MISC_REG_RESET_PL_UA + 4)
114 #define MISC_REG_RESET_PL_UA_CLEAR (MISC_REG_RESET_PL_UA + 8)
115 #define MISC_REG_RESET_PL_UA_RST_MISC_CORE (0x1<<0)
116 #define MISC_REG_RESET_PL_UA_RST_GRC (0x1<<1)
117 #define MISC_REG_RESET_PL_UA_RST_RBCN (0x1<<2)
118 #define MISC_REG_RESET_PL_UA_RST_RBCZ (0x1<<3)
119
120 #define MISC_REG_RESET_PL_UA_PROCESS_KILL (0x0)
121
122 /* MISC_REG_RESET_PL_HV */
123 #define MISC_REG_RESET_PL_HV_SET (MISC_REG_RESET_PL_HV + 4)
124 #define MISC_REG_RESET_PL_HV_CLEAR (MISC_REG_RESET_PL_HV + 8)
125 #define MISC_REG_RESET_PL_HV_RST_PSWHST (0x1<<0)
126 #define MISC_REG_RESET_PL_HV_RST_PSWRQ (0x1<<1)
127 #define MISC_REG_RESET_PL_HV_RST_PSWRD (0x1<<2)
128 #define MISC_REG_RESET_PL_HV_RST_PSWWR (0x1<<3)
129 #define MISC_REG_RESET_PL_HV_RST_ATC (0x1<<4)
130
131 #define MISC_REG_RESET_PL_HV_PROCESS_KILL \
132 (MISC_REG_RESET_PL_HV_RST_PSWRQ | \
133 MISC_REG_RESET_PL_HV_RST_PSWRD | \
134 MISC_REG_RESET_PL_HV_RST_PSWWR | \
135 MISC_REG_RESET_PL_HV_RST_ATC)
136
137 /* PL_HV_2 - for K2 only */
138 #define MISCS_REG_RESET_PL_HV_2_SET (MISCS_REG_RESET_PL_HV_2 + 4)
139 #define MISCS_REG_RESET_PL_HV_2_CLEAR (MISCS_REG_RESET_PL_HV_2 + 8)
140 #define MISCS_REG_RESET_PL_HV_2_RST_NWM (1<<0)
141 #define MISCS_REG_RESET_PL_HV_2_RST_NWM_MAC0 (1<<1)
142 #define MISCS_REG_RESET_PL_HV_2_RST_NWM_MAC1 (1<<2)
143 #define MISCS_REG_RESET_PL_HV_2_RST_NWM_MAC2 (1<<3)
144 #define MISCS_REG_RESET_PL_HV_2_RST_NWM_MAC3 (1<<4)
145 #define MISCS_REG_RESET_PL_HV_2_RST_NWM_GPCS0 (1<<5)
146 #define MISCS_REG_RESET_PL_HV_2_RST_NWM_GPCS1 (1<<6)
147 #define MISCS_REG_RESET_PL_HV_2_RST_NWM_GPCS2 (1<<7)
148 #define MISCS_REG_RESET_PL_HV_2_RST_NWM_GPCS3 (1<<8)
149 #define MISCS_REG_RESET_PL_HV_2_RST_NWM_XPCS0 (1<<9)
150 #define MISCS_REG_RESET_PL_HV_2_RST_NWM_XPCS1 (1<<10)
151 #define MISCS_REG_RESET_PL_HV_2_RST_NWM_XPCS2 (1<<11)
152 #define MISCS_REG_RESET_PL_HV_2_RST_NWM_XPCS3 (1<<12)
153 #define MISCS_REG_RESET_PL_HV_2_RST_NWM_XPCS4 (1<<13)
154 #define MISCS_REG_RESET_PL_HV_2_RST_NWM_XPCS5 (1<<14)
155 #define MISCS_REG_RESET_PL_HV_2_RST_NWM_XPCS6 (1<<15)
156 #define MISCS_REG_RESET_PL_HV_2_RST_NWM_XPCS7 (1<<16)
157 #define MISCS_REG_RESET_PL_HV_2_RST_NWM_TX_LANE0 (1<<17)
158 #define MISCS_REG_RESET_PL_HV_2_RST_NWM_TX_LANE1 (1<<18)
159 #define MISCS_REG_RESET_PL_HV_2_RST_NWM_TX_LANE2 (1<<19)
160 #define MISCS_REG_RESET_PL_HV_2_RST_NWM_TX_LANE3 (1<<20)
161 #define MISCS_REG_RESET_PL_HV_2_RST_NWM_RX_LANE0 (1<<21)
162 #define MISCS_REG_RESET_PL_HV_2_RST_NWM_RX_LANE1 (1<<22)
163 #define MISCS_REG_RESET_PL_HV_2_RST_NWM_RX_LANE2 (1<<23)
164 #define MISCS_REG_RESET_PL_HV_2_RST_NWM_RX_LANE3 (1<<24)
165 #define MISCS_REG_RESET_PL_HV_2_RST_NWM_SDGB (1<<25)
166
167
168 /* MISC_REG_RESET_PL_PDA_VMAIN_1 */
169 #define MISC_REG_RESET_PL_PDA_VMAIN_1_SET (MISC_REG_RESET_PL_PDA_VMAIN_1 + 4)
170 #define MISC_REG_RESET_PL_PDA_VMAIN_1_CLEAR (MISC_REG_RESET_PL_PDA_VMAIN_1 + 8)
171 #define MISC_REG_RESET_PL_PDA_VMAIN_1_RST_BRB (0x1<<0)
172 #define MISC_REG_RESET_PL_PDA_VMAIN_1_RST_PRS (0x1<<1)
173 #define MISC_REG_RESET_PL_PDA_VMAIN_1_RST_SRC (0x1<<2)
174 #define MISC_REG_RESET_PL_PDA_VMAIN_1_RST_TSDM (0x1<<3)
175 #define MISC_REG_RESET_PL_PDA_VMAIN_1_RST_TSEM (0x1<<4)
176 #define MISC_REG_RESET_PL_PDA_VMAIN_1_RST_TCM (0x1<<5)
177 #define MISC_REG_RESET_PL_PDA_VMAIN_1_RST_RBCR (0x1<<6)
178 #define MISC_REG_RESET_PL_PDA_VMAIN_1_RST_USDM (0x1<<7)
179 #define MISC_REG_RESET_PL_PDA_VMAIN_1_RST_UCM (0x1<<8)
180 #define MISC_REG_RESET_PL_PDA_VMAIN_1_RST_USEM (0x1<<9)
181 #define MISC_REG_RESET_PL_PDA_VMAIN_1_RST_BTB (0x1<<10)
182 #define MISC_REG_RESET_PL_PDA_VMAIN_1_RST_PBF_PB1 (0x1<<11)
183 #define MISC_REG_RESET_PL_PDA_VMAIN_1_RST_PBF_PB2 (0x1<<12)
184 #define MISC_REG_RESET_PL_PDA_VMAIN_1_RST_RPB (0x1<<13)
185 #define MISC_REG_RESET_PL_PDA_VMAIN_1_RST_RBCU (0x1<<14)
186 #define MISC_REG_RESET_PL_PDA_VMAIN_1_RST_PBF (0x1<<15)
187 #define MISC_REG_RESET_PL_PDA_VMAIN_1_RST_QM (0x1<<16)
188 #define MISC_REG_RESET_PL_PDA_VMAIN_1_RST_TM (0x1<<17)
189 #define MISC_REG_RESET_PL_PDA_VMAIN_1_RST_DORQ (0x1<<18)
190 #define MISC_REG_RESET_PL_PDA_VMAIN_1_RST_XCM (0x1<<19)
191 #define MISC_REG_RESET_PL_PDA_VMAIN_1_RST_XSDM (0x1<<20)
192 #define MISC_REG_RESET_PL_PDA_VMAIN_1_RST_XSEM (0x1<<21)
193 #define MISC_REG_RESET_PL_PDA_VMAIN_1_RST_RBCT (0x1<<22)
194 #define MISC_REG_RESET_PL_PDA_VMAIN_1_RST_CDU (0x1<<23)
195 #define MISC_REG_RESET_PL_PDA_VMAIN_1_RST_CCFC (0x1<<24)
196 #define MISC_REG_RESET_PL_PDA_VMAIN_1_RST_TCFC (0x1<<25)
197 #define MISC_REG_RESET_PL_PDA_VMAIN_1_RST_RBCP (0x1<<26)
198 #define MISC_REG_RESET_PL_PDA_VMAIN_1_RST_IGU (0x1<<27)
199 #define MISC_REG_RESET_PL_PDA_VMAIN_1_RST_DMAE (0x1<<28)
200 #define MISC_REG_RESET_PL_PDA_VMAIN_1_RST_SEMI_RTC (0x1<<29)
201
202 #define MISC_REG_RESET_PL_PDA_VMAIN_1_PROCESS_KILL (~MISC_REG_RESET_PL_PDA_VMAIN_1_RST_IGU)
203
204 /* MISC_REG_RESET_PL_PDA_VMAIN_2 */
205 #define MISC_REG_RESET_PL_PDA_VMAIN_2_SET (MISC_REG_RESET_PL_PDA_VMAIN_2 + 4)
206 #define MISC_REG_RESET_PL_PDA_VMAIN_2_CLEAR (MISC_REG_RESET_PL_PDA_VMAIN_2 + 8)
207 #define MISC_REG_RESET_PL_PDA_VMAIN_2_RST_RBCF (0x1<<0)
208 #define MISC_REG_RESET_PL_PDA_VMAIN_2_RST_RBCX (0x1<<1)
209 #define MISC_REG_RESET_PL_PDA_VMAIN_2_RST_RBCS (0x1<<2)
210 #define MISC_REG_RESET_PL_PDA_VMAIN_2_RST_MCM (0x1<<3)
211 #define MISC_REG_RESET_PL_PDA_VMAIN_2_RST_PCM (0x1<<4)
212 #define MISC_REG_RESET_PL_PDA_VMAIN_2_RST_YCM (0x1<<5)
213 #define MISC_REG_RESET_PL_PDA_VMAIN_2_RST_MSDM (0x1<<6)
214 #define MISC_REG_RESET_PL_PDA_VMAIN_2_RST_YSDM (0x1<<7)
215 #define MISC_REG_RESET_PL_PDA_VMAIN_2_RST_PSDM (0x1<<8)
216 #define MISC_REG_RESET_PL_PDA_VMAIN_2_RST_MSEM (0x1<<9)
217 #define MISC_REG_RESET_PL_PDA_VMAIN_2_RST_YSEM (0x1<<10)
218 #define MISC_REG_RESET_PL_PDA_VMAIN_2_RST_PSEM (0x1<<11)
219 #define MISC_REG_RESET_PL_PDA_VMAIN_2_RST_XYLD (0x1<<12)
220 #define MISC_REG_RESET_PL_PDA_VMAIN_2_RST_TMLD (0x1<<13)
221 #define MISC_REG_RESET_PL_PDA_VMAIN_2_RST_MULD (0x1<<14)
222 #define MISC_REG_RESET_PL_PDA_VMAIN_2_RST_YULD (0x1<<15)
223 #define MISC_REG_RESET_PL_PDA_VMAIN_2_RST_RDIF (0x1<<16)
224 #define MISC_REG_RESET_PL_PDA_VMAIN_2_RST_TDIF (0x1<<17)
225 #define MISC_REG_RESET_PL_PDA_VMAIN_2_RST_RSS (0x1<<18)
226 #define MISC_REG_RESET_PL_PDA_VMAIN_2_RST_CAU (0x1<<19)
227 #define MISC_REG_RESET_PL_PDA_VMAIN_2_RST_PTU (0x1<<20)
228 #define MISC_REG_RESET_PL_PDA_VMAIN_2_RST_PRM (0x1<<21)
229 #define MISC_REG_RESET_PL_PDA_VMAIN_2_RST_RBCY (0x1<<22)
230 #define MISC_REG_RESET_PL_PDA_VMAIN_2_RST_RBCQ (0x1<<23)
231 #define MISC_REG_RESET_PL_PDA_VMAIN_2_RST_RBCM (0x1<<24)
232 #define MISC_REG_RESET_PL_PDA_VMAIN_2_RST_RBCB (0x1<<25)
233 #define MISC_REG_RESET_PL_PDA_VMAIN_2_RST_RBCV (0x1<<26)
234
235 #define MISC_REG_RESET_PL_PDA_VMAIN_2_PROCESS_KILL (0x3FFFFF)
236
237 /* MISC_REG_RESET_PL_PDA_VAUX */
238 #define MISC_REG_RESET_PL_PDA_VAUX_SET (MISC_REG_RESET_PL_PDA_VAUX + 4)
239 #define MISC_REG_RESET_PL_PDA_VAUX_CLEAR (MISC_REG_RESET_PL_PDA_VAUX + 8)
240 #define MISC_REG_RESET_PL_PDA_VAUX_RST_NIG (0x1<<0)
241 #define MISC_REG_RESET_PL_PDA_VAUX_RST_RBCH (0x1<<1)
242 #define MISC_REG_RESET_PL_PDA_VAUX_RST_NIG_HARD (0x1<<2)
243 #define MISC_REG_RESET_PL_PDA_VAUX_RST_DBG (0x1<<3)
244 #define MISC_REG_RESET_PL_PDA_VAUX_RST_XMAC (0x1<<4)
245 #define MISC_REG_RESET_PL_PDA_VAUX_RST_XMAC_SOFT (0x1<<5)
246 #define MISC_REG_RESET_PL_PDA_VAUX_RST_MSTAT_NW (0x1<<6)
247 #define MISC_REG_RESET_PL_PDA_VAUX_RST_WOL (0x1<<7)
248 #define MISC_REG_RESET_PL_PDA_VAUX_RST_WOL_HARD (0x1<<8)
249
250 #define MISC_REG_RESET_PL_PDA_VAUX_PROCESS_KILL \
251 (MISC_REG_RESET_PL_PDA_VAUX_RST_NIG | \
252 MISC_REG_RESET_PL_PDA_VAUX_RST_NIG_HARD )
253
254 #define MISC_REG_RESET_BLOCKS(path, _reg_, _bits_) \
255 do { \
256 REG_WRITE(path, _reg_ ## _CLEAR, _bits_); \
257 REG_WRITE(path, _reg_ ## _SET, _bits_); \
258 } while (0)
259 /* MISCS_REG_VAUX_EN_DIS */
260 #define MISCS_VAUX_VALUE (0x3L<<0)
261 #define MISCS_VAUX_VALUE_POS 0
262 #define MISCS_VAUX_SET (0x3L<<2)
263 #define MISCS_VAUX_SET_POS 2
264 #define MISCS_VAUX_CLR (0x3L<<4)
265 #define MISCS_VAUX_CLR_POS 4
266 #define MISCS_VAUX_FLOAT (0x3L<<6)
267 #define MISCS_VAUX_FLOAT_POS 6
268
269 /* VAUX_EN_DIS pin assignment */
270 #define MISCS_VAUX_EN_L 0x1 /* Bit 0 */
271 #define MISCS_VAUX_DIS_L 0x2 /* Bit 1 */
272
273 #define MISCS_MAIN_SEQ_BYP_SEL_VAUX_B (1<<4)
274 /////////////////////////
275 // HW Lock Definitions //
276 /////////////////////////
277
278 // Masters
279 #define HW_LOCK_MASTER_FUNC_0 0
280 #define HW_LOCK_MASTER_FUNC_1 1
281 #define HW_LOCK_MASTER_FUNC_2 2
282 #define HW_LOCK_MASTER_FUNC_3 3
283 #define HW_LOCK_MASTER_FUNC_4 4
284 #define HW_LOCK_MASTER_FUNC_5 5
285 #define HW_LOCK_MASTER_FUNC_6 6
286 #define HW_LOCK_MASTER_FUNC_7 7
287 #define HW_LOCK_MASTER_RESERVED_8 8
288 #define HW_LOCK_MASTER_RESERVED_9 9
289 #define HW_LOCK_MASTER_RESERVED_10 10
290 #define HW_LOCK_MASTER_RESERVED_11 11
291 #define HW_LOCK_MASTER_RESERVED_12 12
292 #define HW_LOCK_MASTER_HOST_SCRIPTS 13
293 #define HW_LOCK_MASTER_MCP_RESET 14
294 #define HW_LOCK_MASTER_MCP 15
295
296 // Resources
297 #define HW_LOCK_RESOURCE_RESERVED_0 (1 << 0)
298 #define HW_LOCK_RESOURCE_RESERVED_1 (1 << 1)
299 #define HW_LOCK_RESOURCE_RESERVED_2 (1 << 2)
300 #define HW_LOCK_RESOURCE_RESERVED_3 (1 << 3)
301 #define HW_LOCK_RESOURCE_RESERVED_4 (1 << 4)
302 #define HW_LOCK_RESOURCE_RESERVED_5 (1 << 5)
303 #define HW_LOCK_RESOURCE_RESERVED_6 (1 << 6)
304 #define HW_LOCK_RESOURCE_RESERVED_7 (1 << 7)
305 #define HW_LOCK_RESOURCE_RESERVED_8 (1 << 8)
306 #define HW_LOCK_RESOURCE_RESERVED_9 (1 << 9)
307 #define HW_LOCK_RESOURCE_RESERVED_10 (1 << 10)
308 #define HW_LOCK_RESOURCE_RESERVED_11 (1 << 11)
309 #define HW_LOCK_RESOURCE_RESERVED_12 (1 << 12)
310 #define HW_LOCK_RESOURCE_RESERVED_13 (1 << 13)
311 #define HW_LOCK_RESOURCE_RESERVED_14 (1 << 14)
312 #define HW_LOCK_RESOURCE_RESERVED_15 (1 << 15)
313 #define HW_LOCK_RESOURCE_RESERVED_16 (1 << 16)
314 #define HW_LOCK_RESOURCE_RESERVED_17 (1 << 17)
315 #define HW_LOCK_RESOURCE_RESERVED_18 (1 << 18)
316 #define HW_LOCK_RESOURCE_RESERVED_19 (1 << 19)
317 #define HW_LOCK_RESOURCE_RESERVED_20 (1 << 20)
318 #define HW_LOCK_RESOURCE_RESERVED_21 (1 << 21)
319 #define HW_LOCK_RESOURCE_RESERVED_22 (1 << 22)
320 #define HW_LOCK_RESOURCE_RESERVED_23 (1 << 23)
321 #define HW_LOCK_RESOURCE_RESERVED_24 (1 << 24)
322 #define HW_LOCK_RESOURCE_RESERVED_25 (1 << 25)
323 #define HW_LOCK_RESOURCE_RESERVED_26 (1 << 26)
324 #define HW_LOCK_RESOURCE_OEM_0 (1 << 27)
325 #define HW_LOCK_RESOURCE_OEM_1 (1 << 28)
326 #define HW_LOCK_RESOURCE_OEM_2 (1 << 29)
327 #define HW_LOCK_RESOURCE_OEM_3 (1 << 30)
328 #define HW_LOCK_RESOURCE_OEM_4 (1 << 31)
329 #define HW_LOCK_MAX_RESOURCE_VALUE (31)
330
331
332 /////////////////////////
333 // CHIP DEF Definitions //
334 /////////////////////////
335 #define MISCS_REG_CHIP_NUM_K2_DRVSIM 0x1628
336 #define MISCS_REG_CHIP_NUM_BB_DRVSIM 0x1629
337
338 #define MISCS_REG_CHIP_NUM_K2 0x1630
339 #define MISCS_REG_CHIP_NUM_BB 0x1634
340 #define MISCS_REG_CHIP_NUM_BB_T 0x1635
341
342
343 #define CHIP_IS_BB(chip_num) ((chip_num == MISCS_REG_CHIP_NUM_BB_DRVSIM) || (chip_num == MISCS_REG_CHIP_NUM_BB) || (chip_num == MISCS_REG_CHIP_NUM_BB_T))
344 #define CHIP_IS_K2(chip_num) ((chip_num == MISCS_REG_CHIP_NUM_K2_DRVSIM) || (chip_num == MISCS_REG_CHIP_NUM_K2))
345
346 #define MISCS_REG_AVS_PVTMON_DACCODE_VMAIN_DAC_CODE_MASK 0x000003ff
347 #define MISCS_REG_AVS_PVTMON_DACCODE_VMAIN_DAC_CODE_SHIFT 0
348 #define MISCS_REG_AVS_PVTMON_DACCODE_VMAIN_DAC_OVERRIDE_MASK 0x00000400
349 #define MISCS_REG_AVS_PVTMON_DACCODE_VMAIN_DAC_OVERRIDE_SHIFT 10
350 #define MISCS_REG_AVS_PVTMON_DACCODE_VMGMT_DAC_CODE_MASK 0x001ff800
351 #define MISCS_REG_AVS_PVTMON_DACCODE_VMGMT_DAC_CODE_SHIFT 11
352 #define MISCS_REG_AVS_PVTMON_DACCODE_VMGMT_DAC_OVERRIDE_MASK 0x00200000
353 #define MISCS_REG_AVS_PVTMON_DACCODE_VMGMT_DAC_OVERRIDE_SHIFT 21
354 /*
355 * Secured Mode Definitions
356 */
357 enum secure_modes {
358 SECURITY_MODE_NON_SECURED_MODE = 0,
359 SECURITY_MODE_SECURED_MODE = 1,
360 SECURITY_MODE_FULLY_SECURED_MODE = 2
361 };
362
363 #define MISCS_REG_MFW_SECURITY_MODE_SOURCE_MASK (0x1)
364 #define MISCS_REG_MFW_SECURITY_MODE_SOURCE_SHIFT (0)
365 #define MISCS_REG_MFW_SECURITY_MODE_SOURCE_EXT_PIN (0)
366 #define MISCS_REG_MFW_SECURITY_MODE_SOURCE_OVERRIDE (1)
367
368 #define MISCS_REG_MFW_SECURITY_MODE_OVERRIDE_VAL_MASK (0x6)
369 #define MISCS_REG_MFW_SECURITY_MODE_OVERRIDE_VAL_SHIFT (0x1)
370 /* Values are SECURITY_MODE_XXX */
371
372 /* MISCS_REG_GENERIC_POR_0 definition */
373 #define MISCS_POR_RESET_VAL_SHIFT 0
374 #define MISCS_POR_RESET_VAL_MASK 0x00000001
375
376 #define MISCS_POR_CNT_SHIFT 1
377 #define MISCS_POR_CNT_MASK 0x00000002
378
379 #define MISCS_CORE_CNT_SHIFT 2
380 #define MISCS_CORE_CNT_MASK 0x000ffffc
381
382 #define MISCS_MCP_RESET_CNT_SHIFT 20
383 #define MISCS_MCP_RESET_CNT_MASK 0xfff00000
384
385
386 #define MISC_REG_BLOCK_256B_EN_K2_BRB (1<<0)
387 #define MISC_REG_BLOCK_256B_EN_K2_BTB (1<<1)
388 #endif // MISC_BITS_H