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MFV: illumos-gate@48d370f1e98a10b1bdf160dd83a49e0f49f6c1b7
9809 nvme driver should attach to all NVMe 1.x devices
9810 Update parts of NVMe headers for newer specs
9811 nvmeadm(1M) should have ctf
Reviewed by: Hans Rosenfeld <hans.rosenfeld@joyent.com>
Reviewed by: Jerry Jelinek <jerry.jelinek@joyent.com>
Reviewed by: Yuri Pankov <yuripv@yuripv.net>
Reviewed by: Richard Lowe <richlowe@richlowe.net>
Reviewed by: Andy Fiddaman <omnios@citrus-it.co.uk>
Approved by: Dan McDonald <danmcd@joyent.com>
Author: Robert Mustacchi <rm@joyent.com>
NEX-7237 nvme CSTS register definition is wrong
Reviewed by: Yuri Pankov <yuri.pankov@nexenta.com>
Reviewed by: Dan Fields <dan.fields@nexenta.com>
Reviewed by: Dan McDonald <danmcd@omniti.com>
Reviewed by: Igor Kozhukhov <ikozhukhov@gmail.com>
NEX-4431 want NVMe management utility
Reviewed by: Josef 'Jeff' Sipek <josef.sipek@nexenta.com>
Reviewed by: Sanjay Nadkarni <sanjay.nadkarni@nexenta.com>
NEX-2182 need driver for Intel NVM Express (nvme) (preview)
Reviewed by: Dan Fields <dan.fields@nexenta.com>
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--- old/usr/src/uts/common/io/nvme/nvme_reg.h
+++ new/usr/src/uts/common/io/nvme/nvme_reg.h
1 1 /*
2 2 * This file and its contents are supplied under the terms of the
3 3 * Common Development and Distribution License ("CDDL"), version 1.0.
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4 4 * You may only use this file in accordance with the terms of version
5 5 * 1.0 of the CDDL.
6 6 *
7 7 * A full copy of the text of the CDDL should have accompanied this
8 8 * source. A copy of the CDDL is also available via the Internet at
9 9 * http://www.illumos.org/license/CDDL.
10 10 */
11 11
12 12 /*
13 13 * Copyright 2016 Nexenta Systems, Inc. All rights reserved.
14 + * Copyright (c) 2018, Joyent, Inc.
14 15 */
15 16
16 17 /*
17 18 * NVMe hardware interface
18 19 */
19 20
20 21 #ifndef _NVME_REG_H
21 22 #define _NVME_REG_H
22 23
23 24 #include <sys/nvme.h>
24 25
25 26 #pragma pack(1)
26 27
27 28 #ifdef __cplusplus
28 29 extern "C" {
29 30 #endif
30 31
31 32
32 33 /*
33 34 * NVMe constants
34 35 */
35 36 #define NVME_MAX_ADMIN_QUEUE_LEN 4096
36 37
37 38 /*
38 39 * NVMe registers and register fields
39 40 */
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40 41 #define NVME_REG_CAP 0x0 /* Controller Capabilities */
41 42 #define NVME_REG_VS 0x8 /* Version */
42 43 #define NVME_REG_INTMS 0xc /* Interrupt Mask Set */
43 44 #define NVME_REG_INTMC 0x10 /* Interrupt Mask Clear */
44 45 #define NVME_REG_CC 0x14 /* Controller Configuration */
45 46 #define NVME_REG_CSTS 0x1c /* Controller Status */
46 47 #define NVME_REG_NSSR 0x20 /* NVM Subsystem Reset */
47 48 #define NVME_REG_AQA 0x24 /* Admin Queue Attributes */
48 49 #define NVME_REG_ASQ 0x28 /* Admin Submission Queue */
49 50 #define NVME_REG_ACQ 0x30 /* Admin Completion Qeueu */
51 +#define NVME_REG_CMBLOC 0x38 /* Controller Memory Buffer Location */
52 +#define NVME_REG_CMBSZ 0x3C /* Controller Memory Buffer Size */
53 +#define NVME_REG_BPINFO 0x40 /* Boot Partition Information */
54 +#define NVME_REG_BPRSEL 0x44 /* Boot Partition Read Select */
55 +#define NVME_REG_BPMBL 0x48 /* Boot Partition Memory Buffer Loc */
50 56 #define NVME_REG_SQTDBL(nvme, n) \
51 57 (0x1000 + ((2 * (n)) * nvme->n_doorbell_stride))
52 58 #define NVME_REG_CQHDBL(nvme, n) \
53 59 (0x1000 + ((2 * (n) + 1) * nvme->n_doorbell_stride))
54 60
55 61 #define NVME_CAP_CSS_NVM 1 /* NVM Command Set */
56 62 #define NVME_CAP_AMS_WRR 1 /* Weighted Round-Robin */
57 63
58 64 /* CAP -- Controller Capabilities */
59 65 typedef union {
60 66 struct {
61 67 uint16_t cap_mqes; /* Maximum Queue Entries Supported */
62 68 uint8_t cap_cqr:1; /* Contiguous Queues Required */
63 69 uint8_t cap_ams:2; /* Arbitration Mechanisms Supported */
64 70 uint8_t cap_rsvd1:5;
65 71 uint8_t cap_to; /* Timeout */
66 72 uint16_t cap_dstrd:4; /* Doorbell Stride */
67 73 uint16_t cap_nssrs:1; /* NVM Subsystem Reset Supported */
68 74 uint16_t cap_css:8; /* Command Sets Supported */
69 - uint16_t cap_rsvd2:3;
75 + uint16_t cap_rsvd2:2;
76 + uint8_t cap_bps:1; /* Boot Partition Support */
70 77 uint8_t cap_mpsmin:4; /* Memory Page Size Minimum */
71 78 uint8_t cap_mpsmax:4; /* Memory Page Size Maximum */
72 79 uint8_t cap_rsvd3;
73 80 } b;
74 81 uint64_t r;
75 82 } nvme_reg_cap_t;
76 83
77 84 /* VS -- Version */
78 85 typedef union {
79 86 struct {
80 87 uint8_t vs_rsvd;
81 88 uint8_t vs_mnr; /* Minor Version Number */
82 89 uint16_t vs_mjr; /* Major Version Number */
83 90 } b;
84 91 uint32_t r;
85 92 } nvme_reg_vs_t;
86 93
87 94 /* CC -- Controller Configuration */
88 95 #define NVME_CC_SHN_NORMAL 1 /* Normal Shutdown Notification */
89 96 #define NVME_CC_SHN_ABRUPT 2 /* Abrupt Shutdown Notification */
90 97
91 98 typedef union {
92 99 struct {
93 100 uint16_t cc_en:1; /* Enable */
94 101 uint16_t cc_rsvd1:3;
95 102 uint16_t cc_css:3; /* I/O Command Set Selected */
96 103 uint16_t cc_mps:4; /* Memory Page Size */
97 104 uint16_t cc_ams:3; /* Arbitration Mechanism Selected */
98 105 uint16_t cc_shn:2; /* Shutdown Notification */
99 106 uint8_t cc_iosqes:4; /* I/O Submission Queue Entry Size */
100 107 uint8_t cc_iocqes:4; /* I/O Completion Queue Entry Size */
101 108 uint8_t cc_rsvd2;
102 109 } b;
103 110 uint32_t r;
104 111 } nvme_reg_cc_t;
105 112
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106 113 /* CSTS -- Controller Status */
107 114 #define NVME_CSTS_SHN_OCCURING 1 /* Shutdown Processing Occuring */
108 115 #define NVME_CSTS_SHN_COMPLETE 2 /* Shutdown Processing Complete */
109 116
110 117 typedef union {
111 118 struct {
112 119 uint32_t csts_rdy:1; /* Ready */
113 120 uint32_t csts_cfs:1; /* Controller Fatal Status */
114 121 uint32_t csts_shst:2; /* Shutdown Status */
115 122 uint32_t csts_nssro:1; /* NVM Subsystem Reset Occured */
116 - uint32_t csts_rsvd:27;
123 + uint32_t csts_pp:1; /* Processing Paused */
124 + uint32_t csts_rsvd:26;
117 125 } b;
118 126 uint32_t r;
119 127 } nvme_reg_csts_t;
120 128
121 129 /* NSSR -- NVM Subsystem Reset */
122 130 #define NVME_NSSR_NSSRC 0x4e564d65 /* NSSR magic value */
123 131 typedef uint32_t nvme_reg_nssr_t;
124 132
125 133 /* AQA -- Admin Queue Attributes */
126 134 typedef union {
127 135 struct {
128 136 uint16_t aqa_asqs:12; /* Admin Submission Queue Size */
129 137 uint16_t aqa_rsvd1:4;
130 138 uint16_t aqa_acqs:12; /* Admin Completion Queue Size */
131 139 uint16_t aqa_rsvd2:4;
132 140 } b;
133 141 uint32_t r;
134 142 } nvme_reg_aqa_t;
135 143
136 144 /*
137 145 * The spec specifies the lower 12 bits of ASQ and ACQ as reserved, which is
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138 146 * probably a specification bug. The full 64bit regs are used as base address,
139 147 * and the lower bits must be zero to ensure alignment on the page size
140 148 * specified in CC.MPS.
141 149 */
142 150 /* ASQ -- Admin Submission Queue Base Address */
143 151 typedef uint64_t nvme_reg_asq_t; /* Admin Submission Queue Base */
144 152
145 153 /* ACQ -- Admin Completion Queue Base Address */
146 154 typedef uint64_t nvme_reg_acq_t; /* Admin Completion Queue Base */
147 155
156 +/* CMBLOC - Controller Memory Buffer Location */
157 +typedef union {
158 + struct {
159 + uint32_t cmbloc_bir:3; /* Base Indicator Register */
160 + uint32_t cmbloc_rsvd:9;
161 + uint32_t cmbloc_ofst:20; /* Offset */
162 + } b;
163 + uint32_t r;
164 +} nvme_reg_cmbloc_t;
165 +
166 +/* CMBSZ - Controller Memory Buffer Size */
167 +typedef union {
168 + struct {
169 + uint32_t cmbsz_sqs:1; /* Submission Queue Support */
170 + uint32_t cmbsz_cqs:1; /* Completion Queue Support */
171 + uint32_t cmbsz_lists:1; /* PRP SGL List Support */
172 + uint32_t cmbsz_rds:1; /* Read Data Support */
173 + uint32_t cmbsz_wds:1; /* Write Data Support */
174 + uint32_t cmbsz_rsvd:3;
175 + uint32_t cmbsz_szu:4; /* Size Units */
176 + uint32_t cmbsz_sz:20; /* Size */
177 + } b;
178 + uint32_t r;
179 +} nvme_reg_cmbsz_t;
180 +
181 +/* BPINFO - Boot Partition Information */
182 +typedef union {
183 + struct {
184 + uint32_t bpinfo_bpsz:15; /* Boot Partition Size */
185 + uint32_t bpinfo_rsvd:9;
186 + uint32_t bpinfo_brs:2; /* Boot Read Status */
187 + uint32_t bpinfo_rsvd2:5;
188 + uint32_t bpinfo_abpid:1; /* Active Boot Partition ID */
189 + } b;
190 + uint32_t r;
191 +} nvme_reg_bpinfo_t;
192 +
193 +/* BPRSEL - Boot Partition Read Select */
194 +typedef union {
195 + struct {
196 + uint32_t bprsel_bprsz:10; /* Boot Partition Read Size */
197 + uint32_t bprsel_bprof:20; /* Boot Partition Read Offset */
198 + uint32_t bprsel_rsvd:1;
199 + uint32_t bprsel_bpid:1; /* Boot Partition Identifier */
200 + } b;
201 + uint32_t r;
202 +} nvme_reg_bprsel_t;
203 +
204 +/* BPMBL - Boot Partition Memory Location Buffer Location */
205 +typedef uint64_t nvme_reg_bpbml_t; /* Memory Buffer Base Address */
206 +
148 207 /* SQyTDBL -- Submission Queue y Tail Doorbell */
149 208 typedef union {
150 209 struct {
151 210 uint16_t sqtdbl_sqt; /* Submission Queue Tail */
152 211 uint16_t sqtdbl_rsvd;
153 212 } b;
154 213 uint32_t r;
155 214 } nvme_reg_sqtdbl_t;
156 215
157 216 /* CQyHDBL -- Completion Queue y Head Doorbell */
158 217 typedef union {
159 218 struct {
160 219 uint16_t cqhdbl_cqh; /* Completion Queue Head */
161 220 uint16_t cqhdbl_rsvd;
162 221 } b;
163 222 uint32_t r;
164 223 } nvme_reg_cqhdbl_t;
165 224
166 225 /*
167 226 * NVMe submission queue entries
168 227 */
169 228
170 229 /* NVMe scatter/gather list descriptor */
171 230 typedef struct {
172 231 uint64_t sgl_addr; /* Address */
173 232 uint32_t sgl_len; /* Length */
174 233 uint8_t sgl_rsvd[3];
175 234 uint8_t sgl_zero:4;
176 235 uint8_t sgl_type:4; /* SGL descriptor type */
177 236 } nvme_sgl_t;
178 237
179 238 /* NVMe SGL descriptor type */
180 239 #define NVME_SGL_DATA_BLOCK 0
181 240 #define NVME_SGL_BIT_BUCKET 1
182 241 #define NVME_SGL_SEGMENT 2
183 242 #define NVME_SGL_LAST_SEGMENT 3
184 243 #define NVME_SGL_VENDOR 0xf
185 244
186 245 /* NVMe submission queue entry */
187 246 typedef struct {
188 247 uint8_t sqe_opc; /* Opcode */
189 248 uint8_t sqe_fuse:2; /* Fused Operation */
190 249 uint8_t sqe_rsvd:5;
191 250 uint8_t sqe_psdt:1; /* PRP or SGL for Data Transfer */
192 251 uint16_t sqe_cid; /* Command Identifier */
193 252 uint32_t sqe_nsid; /* Namespace Identifier */
194 253 uint64_t sqe_rsvd1;
195 254 union {
196 255 uint64_t m_ptr; /* Metadata Pointer */
197 256 uint64_t m_sglp; /* Metadata SGL Segment Pointer */
198 257 } sqe_m;
199 258 union {
200 259 uint64_t d_prp[2]; /* Physical Page Region Entries 1 & 2 */
201 260 nvme_sgl_t d_sgl; /* SGL Entry 1 */
202 261 } sqe_dptr; /* Data Pointer */
203 262 uint32_t sqe_cdw10; /* Number of Dwords in Data Transfer */
204 263 uint32_t sqe_cdw11; /* Number of Dwords in Metadata Xfer */
205 264 uint32_t sqe_cdw12;
206 265 uint32_t sqe_cdw13;
207 266 uint32_t sqe_cdw14;
208 267 uint32_t sqe_cdw15;
209 268 } nvme_sqe_t;
210 269
211 270 /* NVMe admin command opcodes */
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212 271 #define NVME_OPC_DELETE_SQUEUE 0x0
213 272 #define NVME_OPC_CREATE_SQUEUE 0x1
214 273 #define NVME_OPC_GET_LOG_PAGE 0x2
215 274 #define NVME_OPC_DELETE_CQUEUE 0x4
216 275 #define NVME_OPC_CREATE_CQUEUE 0x5
217 276 #define NVME_OPC_IDENTIFY 0x6
218 277 #define NVME_OPC_ABORT 0x8
219 278 #define NVME_OPC_SET_FEATURES 0x9
220 279 #define NVME_OPC_GET_FEATURES 0xa
221 280 #define NVME_OPC_ASYNC_EVENT 0xc
281 +#define NVME_OPC_NS_MGMT 0xd /* 1.2 */
222 282 #define NVME_OPC_FW_ACTIVATE 0x10
223 283 #define NVME_OPC_FW_IMAGE_LOAD 0x11
284 +#define NVME_OPC_SELF_TEST 0x14 /* 1.3 */
285 +#define NVME_OPC_NS_ATTACH 0x15 /* 1.2 */
286 +#define NVME_OPC_KEEP_ALIVE 0x18 /* 1.3 */
287 +#define NVME_OPC_DIRECTIVE_SEND 0x19 /* 1.3 */
288 +#define NVME_OPC_DIRECTIVE_RECV 0x1A /* 1.3 */
289 +#define NVME_OPC_VIRT_MGMT 0x1C /* 1.3 */
290 +#define NVME_OPC_NVMEMI_SEND 0x1D /* 1.3 */
291 +#define NVME_OPC_NVMEMI_RECV 0x1E /* 1.3 */
292 +#define NVME_OPC_DB_CONFIG 0x7C /* 1.3 */
224 293
225 294 /* NVMe NVM command set specific admin command opcodes */
226 295 #define NVME_OPC_NVM_FORMAT 0x80
227 296 #define NVME_OPC_NVM_SEC_SEND 0x81
228 297 #define NVME_OPC_NVM_SEC_RECV 0x82
229 298
230 299 /* NVMe NVM command opcodes */
231 300 #define NVME_OPC_NVM_FLUSH 0x0
232 301 #define NVME_OPC_NVM_WRITE 0x1
233 302 #define NVME_OPC_NVM_READ 0x2
234 303 #define NVME_OPC_NVM_WRITE_UNC 0x4
235 304 #define NVME_OPC_NVM_COMPARE 0x5
236 305 #define NVME_OPC_NVM_WRITE_ZERO 0x8
237 306 #define NVME_OPC_NVM_DSET_MGMT 0x9
238 307 #define NVME_OPC_NVM_RESV_REG 0xd
239 308 #define NVME_OPC_NVM_RESV_REPRT 0xe
240 309 #define NVME_OPC_NVM_RESV_ACQ 0x11
241 310 #define NVME_OPC_NVM_RESV_REL 0x12
242 311
243 312 /*
244 313 * NVMe completion queue entry
245 314 */
246 315 typedef struct {
247 316 uint32_t cqe_dw0; /* Command Specific */
248 317 uint32_t cqe_rsvd1;
249 318 uint16_t cqe_sqhd; /* SQ Head Pointer */
250 319 uint16_t cqe_sqid; /* SQ Identifier */
251 320 uint16_t cqe_cid; /* Command Identifier */
252 321 nvme_cqe_sf_t cqe_sf; /* Status Field */
253 322 } nvme_cqe_t;
254 323
255 324 /* NVMe completion status code type */
256 325 #define NVME_CQE_SCT_GENERIC 0 /* Generic Command Status */
257 326 #define NVME_CQE_SCT_SPECIFIC 1 /* Command Specific Status */
258 327 #define NVME_CQE_SCT_INTEGRITY 2 /* Media and Data Integrity Errors */
259 328 #define NVME_CQE_SCT_VENDOR 7 /* Vendor Specific */
260 329
261 330 /* NVMe completion status code (generic) */
262 331 #define NVME_CQE_SC_GEN_SUCCESS 0x0 /* Successful Completion */
263 332 #define NVME_CQE_SC_GEN_INV_OPC 0x1 /* Invalid Command Opcode */
264 333 #define NVME_CQE_SC_GEN_INV_FLD 0x2 /* Invalid Field in Command */
265 334 #define NVME_CQE_SC_GEN_ID_CNFL 0x3 /* Command ID Conflict */
266 335 #define NVME_CQE_SC_GEN_DATA_XFR_ERR 0x4 /* Data Transfer Error */
267 336 #define NVME_CQE_SC_GEN_ABORT_PWRLOSS 0x5 /* Cmds Aborted / Pwr Loss */
268 337 #define NVME_CQE_SC_GEN_INTERNAL_ERR 0x6 /* Internal Error */
269 338 #define NVME_CQE_SC_GEN_ABORT_REQUEST 0x7 /* Command Abort Requested */
270 339 #define NVME_CQE_SC_GEN_ABORT_SQ_DEL 0x8 /* Cmd Aborted / SQ deletion */
271 340 #define NVME_CQE_SC_GEN_ABORT_FUSE_FAIL 0x9 /* Cmd Aborted / Failed Fused */
272 341 #define NVME_CQE_SC_GEN_ABORT_FUSE_MISS 0xa /* Cmd Aborted / Missing Fusd */
273 342 #define NVME_CQE_SC_GEN_INV_NS 0xb /* Inval Namespace or Format */
274 343 #define NVME_CQE_SC_GEN_CMD_SEQ_ERR 0xc /* Command Sequence Error */
275 344 #define NVME_CQE_SC_GEN_INV_SGL_LAST 0xd /* Inval SGL Last Seg Desc */
276 345 #define NVME_CQE_SC_GEN_INV_SGL_NUM 0xe /* Inval Number of SGL Desc */
277 346 #define NVME_CQE_SC_GEN_INV_DSGL_LEN 0xf /* Data SGL Length Invalid */
278 347 #define NVME_CQE_SC_GEN_INV_MSGL_LEN 0x10 /* Metadata SGL Length Inval */
279 348 #define NVME_CQE_SC_GEN_INV_SGL_DESC 0x11 /* SGL Descriptor Type Inval */
280 349
281 350 /* NVMe completion status code (generic NVM commands) */
282 351 #define NVME_CQE_SC_GEN_NVM_LBA_RANGE 0x80 /* LBA Out Of Range */
283 352 #define NVME_CQE_SC_GEN_NVM_CAP_EXC 0x81 /* Capacity Exceeded */
284 353 #define NVME_CQE_SC_GEN_NVM_NS_NOTRDY 0x82 /* Namespace Not Ready */
285 354 #define NVME_CQE_SC_GEN_NVM_RSV_CNFLCT 0x83 /* Reservation Conflict */
286 355
287 356 /* NVMe completion status code (command specific) */
288 357 #define NVME_CQE_SC_SPC_INV_CQ 0x0 /* Completion Queue Invalid */
289 358 #define NVME_CQE_SC_SPC_INV_QID 0x1 /* Invalid Queue Identifier */
290 359 #define NVME_CQE_SC_SPC_MAX_QSZ_EXC 0x2 /* Max Queue Size Exceeded */
291 360 #define NVME_CQE_SC_SPC_ABRT_CMD_EXC 0x3 /* Abort Cmd Limit Exceeded */
292 361 #define NVME_CQE_SC_SPC_ASYNC_EVREQ_EXC 0x5 /* Async Event Request Limit */
293 362 #define NVME_CQE_SC_SPC_INV_FW_SLOT 0x6 /* Invalid Firmware Slot */
294 363 #define NVME_CQE_SC_SPC_INV_FW_IMG 0x7 /* Invalid Firmware Image */
295 364 #define NVME_CQE_SC_SPC_INV_INT_VECT 0x8 /* Invalid Interrupt Vector */
296 365 #define NVME_CQE_SC_SPC_INV_LOG_PAGE 0x9 /* Invalid Log Page */
297 366 #define NVME_CQE_SC_SPC_INV_FORMAT 0xa /* Invalid Format */
298 367 #define NVME_CQE_SC_SPC_FW_RESET 0xb /* FW Application Reset Reqd */
299 368 #define NVME_CQE_SC_SPC_INV_Q_DEL 0xc /* Invalid Queue Deletion */
300 369 #define NVME_CQE_SC_SPC_FEAT_SAVE 0xd /* Feature Id Not Saveable */
301 370 #define NVME_CQE_SC_SPC_FEAT_CHG 0xe /* Feature Not Changeable */
302 371 #define NVME_CQE_SC_SPC_FEAT_NS_SPEC 0xf /* Feature Not Namespace Spec */
303 372 #define NVME_CQE_SC_SPC_FW_NSSR 0x10 /* FW Application NSSR Reqd */
304 373
305 374 /* NVMe completion status code (NVM command specific */
306 375 #define NVME_CQE_SC_SPC_NVM_CNFL_ATTR 0x80 /* Conflicting Attributes */
307 376 #define NVME_CQE_SC_SPC_NVM_INV_PROT 0x81 /* Invalid Protection */
308 377 #define NVME_CQE_SC_SPC_NVM_READONLY 0x82 /* Write to Read Only Range */
309 378
310 379 /* NVMe completion status code (data / metadata integrity) */
311 380 #define NVME_CQE_SC_INT_NVM_WRITE 0x80 /* Write Fault */
312 381 #define NVME_CQE_SC_INT_NVM_READ 0x81 /* Unrecovered Read Error */
313 382 #define NVME_CQE_SC_INT_NVM_GUARD 0x82 /* Guard Check Error */
314 383 #define NVME_CQE_SC_INT_NVM_APPL_TAG 0x83 /* Application Tag Check Err */
315 384 #define NVME_CQE_SC_INT_NVM_REF_TAG 0x84 /* Reference Tag Check Err */
316 385 #define NVME_CQE_SC_INT_NVM_COMPARE 0x85 /* Compare Failure */
317 386 #define NVME_CQE_SC_INT_NVM_ACCESS 0x86 /* Access Denied */
318 387
319 388 /*
320 389 * NVMe Asynchronous Event Request
321 390 */
322 391 #define NVME_ASYNC_TYPE_ERROR 0x0 /* Error Status */
323 392 #define NVME_ASYNC_TYPE_HEALTH 0x1 /* SMART/Health Status */
324 393 #define NVME_ASYNC_TYPE_VENDOR 0x7 /* vendor specific */
325 394
326 395 #define NVME_ASYNC_ERROR_INV_SQ 0x0 /* Invalid Submission Queue */
327 396 #define NVME_ASYNC_ERROR_INV_DBL 0x1 /* Invalid Doorbell Write */
328 397 #define NVME_ASYNC_ERROR_DIAGFAIL 0x2 /* Diagnostic Failure */
329 398 #define NVME_ASYNC_ERROR_PERSISTENT 0x3 /* Persistent Internal Error */
330 399 #define NVME_ASYNC_ERROR_TRANSIENT 0x4 /* Transient Internal Error */
331 400 #define NVME_ASYNC_ERROR_FW_LOAD 0x5 /* Firmware Image Load Error */
332 401
333 402 #define NVME_ASYNC_HEALTH_RELIABILITY 0x0 /* Device Reliability */
334 403 #define NVME_ASYNC_HEALTH_TEMPERATURE 0x1 /* Temp. Above Threshold */
335 404 #define NVME_ASYNC_HEALTH_SPARE 0x2 /* Spare Below Threshold */
336 405
337 406 typedef union {
338 407 struct {
339 408 uint8_t ae_type:3; /* Asynchronous Event Type */
340 409 uint8_t ae_rsvd1:5;
341 410 uint8_t ae_info; /* Asynchronous Event Info */
342 411 uint8_t ae_logpage; /* Associated Log Page */
343 412 uint8_t ae_rsvd2;
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344 413 } b;
345 414 uint32_t r;
346 415 } nvme_async_event_t;
347 416
348 417 /*
349 418 * NVMe Create Completion/Submission Queue
350 419 */
351 420 typedef union {
352 421 struct {
353 422 uint16_t q_qid; /* Queue Identifier */
354 - uint16_t q_qsize; /* Queue Size */
423 + uint16_t q_qsize; /* Queue Size */
355 424 } b;
356 425 uint32_t r;
357 426 } nvme_create_queue_dw10_t;
358 427
359 428 typedef union {
360 429 struct {
361 430 uint16_t cq_pc:1; /* Physically Contiguous */
362 431 uint16_t cq_ien:1; /* Interrupts Enabled */
363 432 uint16_t cq_rsvd:14;
364 433 uint16_t cq_iv; /* Interrupt Vector */
365 434 } b;
366 435 uint32_t r;
367 436 } nvme_create_cq_dw11_t;
368 437
369 438 typedef union {
370 439 struct {
371 440 uint16_t sq_pc:1; /* Physically Contiguous */
372 441 uint16_t sq_qprio:2; /* Queue Priority */
373 442 uint16_t sq_rsvd:13;
374 443 uint16_t sq_cqid; /* Completion Queue ID */
375 444 } b;
376 445 uint32_t r;
377 446 } nvme_create_sq_dw11_t;
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378 447
379 448 /*
380 449 * NVMe Identify
381 450 */
382 451
383 452 /* NVMe Identify parameters (cdw10) */
384 453 #define NVME_IDENTIFY_NSID 0x0 /* Identify Namespace */
385 454 #define NVME_IDENTIFY_CTRL 0x1 /* Identify Controller */
386 455 #define NVME_IDENTIFY_LIST 0x2 /* Identify List Namespaces */
387 456
457 +#define NVME_IDENTIFY_NSID_ALLOC_LIST 0x10 /* List Allocated NSID */
458 +#define NVME_IDENTIFY_NSID_ALLOC 0x11 /* Identify Allocated NSID */
459 +#define NVME_IDENTIFY_NSID_CTRL_LIST 0x12 /* List Controllers on NSID */
460 +#define NVME_IDENTIFY_CTRL_LIST 0x13 /* Controller List */
461 +#define NVME_IDENTIFY_PRIMARY_CAPS 0x14 /* Primary Controller Caps */
388 462
389 463 /*
390 464 * NVMe Abort Command
391 465 */
392 466 typedef union {
393 467 struct {
394 468 uint16_t ac_sqid; /* Submission Queue ID */
395 469 uint16_t ac_cid; /* Command ID */
396 470 } b;
397 471 uint32_t r;
398 472 } nvme_abort_cmd_t;
399 473
400 474
401 475 /*
402 476 * NVMe Get Log Page
403 477 */
404 478 typedef union {
405 479 struct {
406 480 uint8_t lp_lid; /* Log Page Identifier */
407 481 uint8_t lp_rsvd1;
408 482 uint16_t lp_numd:12; /* Number of Dwords */
409 483 uint16_t lp_rsvd2:4;
410 484 } b;
411 485 uint32_t r;
412 486 } nvme_getlogpage_t;
413 487
414 488
415 489 #ifdef __cplusplus
416 490 }
417 491 #endif
418 492
419 493 #pragma pack() /* pack(1) */
420 494
421 495 #endif /* _NVME_REG_H */
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