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MFV: illumos-gate@48d370f1e98a10b1bdf160dd83a49e0f49f6c1b7
9809 nvme driver should attach to all NVMe 1.x devices
9810 Update parts of NVMe headers for newer specs
9811 nvmeadm(1M) should have ctf
Reviewed by: Hans Rosenfeld <hans.rosenfeld@joyent.com>
Reviewed by: Jerry Jelinek <jerry.jelinek@joyent.com>
Reviewed by: Yuri Pankov <yuripv@yuripv.net>
Reviewed by: Richard Lowe <richlowe@richlowe.net>
Reviewed by: Andy Fiddaman <omnios@citrus-it.co.uk>
Approved by: Dan McDonald <danmcd@joyent.com>
Author: Robert Mustacchi <rm@joyent.com>
NEX-18067 Catch up with illumos 8806 8805
8806 xattr_dir_inactive() releases used vnode with kernel panic
Reviewed by: Marcel Telka <marcel@telka.sk>
Reviewed by: Gordon Ross <gordon.w.ross@gmail.com>
Approved by: Dan McDonald <danmcd@joyent.com>
8805 xattr_dir_lookup() can leak a vnode hold
Reviewed by: Marcel Telka <marcel@telka.sk>
Reviewed by: Gordon Ross <gordon.w.ross@gmail.com>
Approved by: Dan McDonald <danmcd@joyent.com>
NEX-17991 emulated NVMe controller on ESXi 6.7 fails to attach
Reviewed by: Dan Fields <dan.fields@nexenta.com>
Reviewed by: Rick McNeal <rick.mcneal@nexenta.com>
NEX-16749 some NVMe controllers get upset about NS ID of 0 when checking "Error Recovery" feature
Reviewed by: Cynthia Eastham <cynthia.eastham@nexenta.com>
Reviewed by: Roman Strashkin <roman.strashkin@nexenta.com>
Reviewed by: Rick McNeal <rick.mcneal@nexenta.com>
NEX-16880 update NVME code
8804 nvme: add alias for pciclass,010802
Reviewed by: Peter Tribble <peter.tribble@gmail.com>
Reviewed by: Michal Nowak <mnowak@startmail.com>
Approved by: Richard Lowe <richlowe@richlowe.net>
8979 nvmeadm(1m): ctl/[ns] -> ctl[/ns]
Reviewed by: Yuri Pankov <yuripv@gmx.com>
Reviewed by: Rich Lowe <richlowe@richlowe.net>
Reviewed by: Rob Johnston <rob.johnston@joyent.com>
Reviewed by: Toomas Soome <tsoome@me.com>
Approved by: Dan McDonald <danmcd@joyent.com>
8945 nvme panics when async events are not supported
Reviewed by: Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org>
Reviewed by: Yuri Pankov <yuripv@yuripv.net>
Reviewed by: Michal Nowak <mnowak@startmail.com>
Approved by: Richard Lowe <richlowe@richlowe.net>
NEX-16549 nvme: "programming error: invalid NS/format" doing 'nvmeadm list' on a controller without namespaces
Reviewed by: Roman Strashkin <roman.strashkin@nexenta.com>
Reviewed by: Dan Fields <dan.fields@nexenta.com>
NEX-15208 nvme: Software Progress Marker feature is optional
Reviewed by: Dan Fields <dan.fields@nexenta.com>
Reviewed by: Cynthia Eastham <cynthia.eastham@nexenta.com>
NEX-8020 illumos nvme changes
Reviewed by: Dan Fields <dan.fields@nexenta.com>
Reviewed by: Gordon Ross <gordon.ross@nexenta.com>
NEX-7539 nvme fails to get error log page from Samsung PM1725
Reviewed by: Dan Fields <dan.fields@nexenta.com>
Reviewed by: Rick McNeal <rick.mcneal@nexenta.com>
Reviewed by: Gordon Ross <gordon.ross@nexenta.com>
NEX-7538 nvme shouldn't ignore namespaces that support extended data LBAs
Reviewed by: Dan Fields <dan.fields@nexenta.com>
Reviewed by: Rick McNeal <rick.mcneal@nexenta.com>
NEX-7373 nvme queue DMA attribute count_max is 0-based
Reviewed by: Gordon Ross <gordon.ross@nexenta.com
Reviewed by: Dan Fields <dan.fields@nexenta.com>
NEX-7369 bump nvme admin command timeout to 1s
Reviewed by: Yuri Pankov <yuri.pankov@nexenta.com>
Reviewed by: Rick McNeal <rick.mcneal@nexenta.com>
NEX-6740 nvme checksum errors with blocksize < 4096
Reviewed by: Hans Rosenfeld <hans.rosenfeld@nexenta.com>
Reviewed by: Yuri Pankov <yuri.pankov@nexenta.com>
Reviewed by: Rick McNeal <rick.mcneal@nexenta.com>
NEX-7349 nvme ignores interrupt enabling failure
Reviewed by: Yuri Pankov <yuri.pankov@nexenta.com>
Reviewed by: Rick McNeal <rick.mcneal@nexenta.com>
NEX-7336 nvme initial interrupt issues
Reviewed by: Robert Mustacchi <rm@joyent.com>
Reviewed by: Gordon Ross <gordon.ross@nexenta.com>
Reviewed by: Evan Layton <evan.layton@nexenta.com>
NEX-7322 nvme fix from Tegile needs a fix
Reviewed by: Evan Layton <evan.layton@nexenta.com>
Reviewed by: Bayard Bell <bayard.bell@nexenta.com>
Reviewed by: Dan Fields <dan.fields@nexenta.com>
NEX-7321 nvme version number check is broken again
Reviewed by: Steve Peng <steve.peng@nexenta.com>
Reviewed by: Rob Gittins <rob.gittins@nexenta.com>
NEX-7291 several small nvme fixes from Tegile
Reviewed by: Dan Fields <dan.fields@nexenta.com>
Reviewed by: Yuri Pankov <yuri.pankov@nexenta.com>
NEX-7290 nvme: id_nlbaf field is 0-based
Reviewed by: Dan Fields <dan.fields@nexenta.com>
Reviewed by: Yuri Pankov <yuri.pankov@nexenta.com>
NEX-7236 nvme shouldn't use ddi_intr_enable/disable to block interrupts
Reviewed by: Yuri Pankov <yuri.pankov@nexenta.com>
Reviewed by: Dan Fields <dan.fields@nexenta.com>
Reviewed by: Dan McDonald <danmcd@omniti.com>
Reviewed by: Igor Kozhukhov <ikozhukhov@gmail.com>
NEX-5192 Samsung SSD SM951-NVMe shows checksum errors
Reviewed by: Yuri Pankov <yuri.pankov@nexenta.com>
Reviewed by: Josef 'Jeff' Sipek <josef.sipek@nexenta.com>
NEX-5792 support NVMe namespace EUI64
Reviewed by: Josef 'Jeff' Sipek <josef.sipek@nexenta.com>
Reviewed by: Rick McNeal <rick.mcneal@nexenta.com>
NEX-6132 nvmeadm(1M) get-feature command could use some cleanup
Reviewed by: Josef 'Jeff' Sipek <josef.sipek@nexenta.com>
Reviewed by: Rick McNeal <rick.mcneal@nexenta.com>
NEX-6130 basic NVMe 1.1 support
Reviewed by: Josef 'Jeff' Sipek <josef.sipek@nexenta.com>
Reviewed by: Rick McNeal <rick.mcneal@nexenta.com>
NEX-5791 support NVMe volatile write cache
Reviewed by: Yuri Pankov <yuri.pankov@nexenta.com>
Reviewed by: Josef 'Jeff' Sipek <josef.sipek@nexenta.com>
NEX-4431 want NVMe management utility
Reviewed by: Josef 'Jeff' Sipek <josef.sipek@nexenta.com>
Reviewed by: Sanjay Nadkarni <sanjay.nadkarni@nexenta.com>
NEX-4849 nvme version number check is broken
Reviewed by: Dan McDonald <danmcd@omniti.com>
Reviewed by: Toomas Soome <tsoome@me.com>
Reviewed by: Garrett D'Amore <garrett@damore.org>
Approved by: Robert Mustacchi <rm@joyent.com>
NEX-4850 off-by-one in nvme_get_logpage()
Reviewed by: Dan McDonald <danmcd@omniti.com>
Reviewed by: Toomas Soome <tsoome@me.com>
Reviewed by: Garrett D'Amore <garrett@damore.org>
Approved by: Robert Mustacchi <rm@joyent.com>
NEX-4427 blkdev should provide the device_error kstat for iostat -E
Reviewed by: Richard Elling <Richard.Elling@RichardElling.com>
Reviewed by: Garrett D'Amore <garrett@damore.org>
NEX-4424 kstat module needs cleanup
Reviewed by: Richard Elling <Richard.Elling@RichardElling.com>
Reviewed by: Garrett D'Amore <garrett@damore.org>
NEX-4420 format(1M) should be able to use device inquiry properties
Reviewed by: Dan McDonald <danmcd@omniti.com>
NEX-4419 blkdev and blkdev drivers should provide inquiry properties
Reviewed by: Garrett D'Amore <garrett@damore.org>
Reviewed by: Josef 'Jeff' Sipek <josef.sipek@nexenta.com>
NEX-2182 need driver for Intel NVM Express (nvme)
Reviewed by: Dan Fields <dan.fields@nexenta.com>
Reviewed by: Josef 'Jeff' Sipek <josef.sipek@nexenta.com>
Reviewed by: Robert Mustacchi <rm@joyent.com>
NEX-2182 need driver for Intel NVM Express (nvme) (preview)
Reviewed by: Dan Fields <dan.fields@nexenta.com>
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--- old/usr/src/uts/common/io/nvme/nvme.c
+++ new/usr/src/uts/common/io/nvme/nvme.c
1 1 /*
2 2 * This file and its contents are supplied under the terms of the
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3 3 * Common Development and Distribution License ("CDDL"), version 1.0.
4 4 * You may only use this file in accordance with the terms of version
5 5 * 1.0 of the CDDL.
6 6 *
7 7 * A full copy of the text of the CDDL should have accompanied this
8 8 * source. A copy of the CDDL is also available via the Internet at
9 9 * http://www.illumos.org/license/CDDL.
10 10 */
11 11
12 12 /*
13 - * Copyright 2016 Nexenta Systems, Inc. All rights reserved.
13 + * Copyright 2018 Nexenta Systems, Inc.
14 14 * Copyright 2016 Tegile Systems, Inc. All rights reserved.
15 15 * Copyright (c) 2016 The MathWorks, Inc. All rights reserved.
16 - * Copyright 2017 Joyent, Inc.
16 + * Copyright 2018 Joyent, Inc.
17 17 */
18 18
19 19 /*
20 20 * blkdev driver for NVMe compliant storage devices
21 21 *
22 22 * This driver was written to conform to version 1.2.1 of the NVMe
23 23 * specification. It may work with newer versions, but that is completely
24 24 * untested and disabled by default.
25 25 *
26 26 * The driver has only been tested on x86 systems and will not work on big-
27 27 * endian systems without changes to the code accessing registers and data
28 28 * structures used by the hardware.
29 29 *
30 30 *
31 31 * Interrupt Usage:
32 32 *
33 33 * The driver will use a single interrupt while configuring the device as the
34 34 * specification requires, but contrary to the specification it will try to use
35 35 * a single-message MSI(-X) or FIXED interrupt. Later in the attach process it
36 36 * will switch to multiple-message MSI(-X) if supported. The driver wants to
37 37 * have one interrupt vector per CPU, but it will work correctly if less are
38 38 * available. Interrupts can be shared by queues, the interrupt handler will
39 39 * iterate through the I/O queue array by steps of n_intr_cnt. Usually only
40 40 * the admin queue will share an interrupt with one I/O queue. The interrupt
41 41 * handler will retrieve completed commands from all queues sharing an interrupt
42 42 * vector and will post them to a taskq for completion processing.
43 43 *
44 44 *
45 45 * Command Processing:
46 46 *
47 47 * NVMe devices can have up to 65535 I/O queue pairs, with each queue holding up
48 48 * to 65536 I/O commands. The driver will configure one I/O queue pair per
49 49 * available interrupt vector, with the queue length usually much smaller than
50 50 * the maximum of 65536. If the hardware doesn't provide enough queues, fewer
51 51 * interrupt vectors will be used.
52 52 *
53 53 * Additionally the hardware provides a single special admin queue pair that can
54 54 * hold up to 4096 admin commands.
55 55 *
56 56 * From the hardware perspective both queues of a queue pair are independent,
57 57 * but they share some driver state: the command array (holding pointers to
58 58 * commands currently being processed by the hardware) and the active command
59 59 * counter. Access to a queue pair and the shared state is protected by
60 60 * nq_mutex.
61 61 *
62 62 * When a command is submitted to a queue pair the active command counter is
63 63 * incremented and a pointer to the command is stored in the command array. The
64 64 * array index is used as command identifier (CID) in the submission queue
65 65 * entry. Some commands may take a very long time to complete, and if the queue
66 66 * wraps around in that time a submission may find the next array slot to still
67 67 * be used by a long-running command. In this case the array is sequentially
68 68 * searched for the next free slot. The length of the command array is the same
69 69 * as the configured queue length. Queue overrun is prevented by the semaphore,
70 70 * so a command submission may block if the queue is full.
71 71 *
72 72 *
73 73 * Polled I/O Support:
74 74 *
75 75 * For kernel core dump support the driver can do polled I/O. As interrupts are
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76 76 * turned off while dumping the driver will just submit a command in the regular
77 77 * way, and then repeatedly attempt a command retrieval until it gets the
78 78 * command back.
79 79 *
80 80 *
81 81 * Namespace Support:
82 82 *
83 83 * NVMe devices can have multiple namespaces, each being a independent data
84 84 * store. The driver supports multiple namespaces and creates a blkdev interface
85 85 * for each namespace found. Namespaces can have various attributes to support
86 - * thin provisioning and protection information. This driver does not support
87 - * any of this and ignores namespaces that have these attributes.
86 + * protection information. This driver does not support any of this and ignores
87 + * namespaces that have these attributes.
88 88 *
89 89 * As of NVMe 1.1 namespaces can have an 64bit Extended Unique Identifier
90 90 * (EUI64). This driver uses the EUI64 if present to generate the devid and
91 91 * passes it to blkdev to use it in the device node names. As this is currently
92 92 * untested namespaces with EUI64 are ignored by default.
93 93 *
94 94 * We currently support only (2 << NVME_MINOR_INST_SHIFT) - 2 namespaces in a
95 95 * single controller. This is an artificial limit imposed by the driver to be
96 96 * able to address a reasonable number of controllers and namespaces using a
97 97 * 32bit minor node number.
98 98 *
99 99 *
100 100 * Minor nodes:
101 101 *
102 102 * For each NVMe device the driver exposes one minor node for the controller and
103 103 * one minor node for each namespace. The only operations supported by those
104 104 * minor nodes are open(9E), close(9E), and ioctl(9E). This serves as the
105 105 * interface for the nvmeadm(1M) utility.
106 106 *
107 107 *
108 108 * Blkdev Interface:
109 109 *
110 110 * This driver uses blkdev to do all the heavy lifting involved with presenting
111 111 * a disk device to the system. As a result, the processing of I/O requests is
112 112 * relatively simple as blkdev takes care of partitioning, boundary checks, DMA
113 113 * setup, and splitting of transfers into manageable chunks.
114 114 *
115 115 * I/O requests coming in from blkdev are turned into NVM commands and posted to
116 116 * an I/O queue. The queue is selected by taking the CPU id modulo the number of
117 117 * queues. There is currently no timeout handling of I/O commands.
118 118 *
119 119 * Blkdev also supports querying device/media information and generating a
120 120 * devid. The driver reports the best block size as determined by the namespace
121 121 * format back to blkdev as physical block size to support partition and block
122 122 * alignment. The devid is either based on the namespace EUI64, if present, or
123 123 * composed using the device vendor ID, model number, serial number, and the
124 124 * namespace ID.
125 125 *
126 126 *
127 127 * Error Handling:
128 128 *
129 129 * Error handling is currently limited to detecting fatal hardware errors,
130 130 * either by asynchronous events, or synchronously through command status or
131 131 * admin command timeouts. In case of severe errors the device is fenced off,
132 132 * all further requests will return EIO. FMA is then called to fault the device.
133 133 *
134 134 * The hardware has a limit for outstanding asynchronous event requests. Before
135 135 * this limit is known the driver assumes it is at least 1 and posts a single
136 136 * asynchronous request. Later when the limit is known more asynchronous event
137 137 * requests are posted to allow quicker reception of error information. When an
138 138 * asynchronous event is posted by the hardware the driver will parse the error
139 139 * status fields and log information or fault the device, depending on the
140 140 * severity of the asynchronous event. The asynchronous event request is then
141 141 * reused and posted to the admin queue again.
142 142 *
143 143 * On command completion the command status is checked for errors. In case of
144 144 * errors indicating a driver bug the driver panics. Almost all other error
145 145 * status values just cause EIO to be returned.
146 146 *
147 147 * Command timeouts are currently detected for all admin commands except
148 148 * asynchronous event requests. If a command times out and the hardware appears
149 149 * to be healthy the driver attempts to abort the command. The original command
150 150 * timeout is also applied to the abort command. If the abort times out too the
151 151 * driver assumes the device to be dead, fences it off, and calls FMA to retire
152 152 * it. In all other cases the aborted command should return immediately with a
153 153 * status indicating it was aborted, and the driver will wait indefinitely for
154 154 * that to happen. No timeout handling of normal I/O commands is presently done.
155 155 *
156 156 * Any command that times out due to the controller dropping dead will be put on
157 157 * nvme_lost_cmds list if it references DMA memory. This will prevent the DMA
158 158 * memory being reused by the system and later be written to by a "dead" NVMe
159 159 * controller.
160 160 *
161 161 *
162 162 * Locking:
163 163 *
164 164 * Each queue pair has its own nq_mutex, which must be held when accessing the
165 165 * associated queue registers or the shared state of the queue pair. Callers of
166 166 * nvme_unqueue_cmd() must make sure that nq_mutex is held, while
167 167 * nvme_submit_{admin,io}_cmd() and nvme_retrieve_cmd() take care of this
168 168 * themselves.
169 169 *
170 170 * Each command also has its own nc_mutex, which is associated with the
171 171 * condition variable nc_cv. It is only used on admin commands which are run
172 172 * synchronously. In that case it must be held across calls to
173 173 * nvme_submit_{admin,io}_cmd() and nvme_wait_cmd(), which is taken care of by
174 174 * nvme_admin_cmd(). It must also be held whenever the completion state of the
175 175 * command is changed or while a admin command timeout is handled.
176 176 *
177 177 * If both nc_mutex and nq_mutex must be held, nc_mutex must be acquired first.
178 178 * More than one nc_mutex may only be held when aborting commands. In this case,
179 179 * the nc_mutex of the command to be aborted must be held across the call to
180 180 * nvme_abort_cmd() to prevent the command from completing while the abort is in
181 181 * progress.
182 182 *
183 183 * Each minor node has its own nm_mutex, which protects the open count nm_ocnt
184 184 * and exclusive-open flag nm_oexcl.
185 185 *
186 186 *
187 187 * Quiesce / Fast Reboot:
188 188 *
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189 189 * The driver currently does not support fast reboot. A quiesce(9E) entry point
190 190 * is still provided which is used to send a shutdown notification to the
191 191 * device.
192 192 *
193 193 *
194 194 * Driver Configuration:
195 195 *
196 196 * The following driver properties can be changed to control some aspects of the
197 197 * drivers operation:
198 198 * - strict-version: can be set to 0 to allow devices conforming to newer
199 - * versions or namespaces with EUI64 to be used
199 + * major versions to be used
200 200 * - ignore-unknown-vendor-status: can be set to 1 to not handle any vendor
201 201 * specific command status as a fatal error leading device faulting
202 202 * - admin-queue-len: the maximum length of the admin queue (16-4096)
203 203 * - io-queue-len: the maximum length of the I/O queues (16-65536)
204 204 * - async-event-limit: the maximum number of asynchronous event requests to be
205 205 * posted by the driver
206 206 * - volatile-write-cache-enable: can be set to 0 to disable the volatile write
207 207 * cache
208 208 * - min-phys-block-size: the minimum physical block size to report to blkdev,
209 209 * which is among other things the basis for ZFS vdev ashift
210 210 *
211 211 *
212 212 * TODO:
213 213 * - figure out sane default for I/O queue depth reported to blkdev
214 214 * - FMA handling of media errors
215 215 * - support for devices supporting very large I/O requests using chained PRPs
216 216 * - support for configuring hardware parameters like interrupt coalescing
217 217 * - support for media formatting and hard partitioning into namespaces
218 218 * - support for big-endian systems
219 219 * - support for fast reboot
220 220 * - support for firmware updates
221 221 * - support for NVMe Subsystem Reset (1.1)
222 222 * - support for Scatter/Gather lists (1.1)
223 223 * - support for Reservations (1.1)
224 224 * - support for power management
225 225 */
226 226
227 227 #include <sys/byteorder.h>
228 228 #ifdef _BIG_ENDIAN
229 229 #error nvme driver needs porting for big-endian platforms
230 230 #endif
231 231
232 232 #include <sys/modctl.h>
233 233 #include <sys/conf.h>
234 234 #include <sys/devops.h>
235 235 #include <sys/ddi.h>
236 236 #include <sys/sunddi.h>
237 237 #include <sys/sunndi.h>
238 238 #include <sys/bitmap.h>
239 239 #include <sys/sysmacros.h>
240 240 #include <sys/param.h>
241 241 #include <sys/varargs.h>
242 242 #include <sys/cpuvar.h>
243 243 #include <sys/disp.h>
244 244 #include <sys/blkdev.h>
245 245 #include <sys/atomic.h>
246 246 #include <sys/archsystm.h>
247 247 #include <sys/sata/sata_hba.h>
248 248 #include <sys/stat.h>
249 249 #include <sys/policy.h>
250 250 #include <sys/list.h>
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251 251
252 252 #include <sys/nvme.h>
253 253
254 254 #ifdef __x86
255 255 #include <sys/x86_archext.h>
256 256 #endif
257 257
258 258 #include "nvme_reg.h"
259 259 #include "nvme_var.h"
260 260
261 +/*
262 + * Assertions to make sure that we've properly captured various aspects of the
263 + * packed structures and haven't broken them during updates.
264 + */
265 +CTASSERT(sizeof (nvme_identify_ctrl_t) == 0x1000);
266 +CTASSERT(offsetof(nvme_identify_ctrl_t, id_oacs) == 256);
267 +CTASSERT(offsetof(nvme_identify_ctrl_t, id_sqes) == 512);
268 +CTASSERT(offsetof(nvme_identify_ctrl_t, id_subnqn) == 768);
269 +CTASSERT(offsetof(nvme_identify_ctrl_t, id_nvmof) == 1792);
270 +CTASSERT(offsetof(nvme_identify_ctrl_t, id_psd) == 2048);
271 +CTASSERT(offsetof(nvme_identify_ctrl_t, id_vs) == 3072);
261 272
273 +CTASSERT(sizeof (nvme_identify_nsid_t) == 0x1000);
274 +CTASSERT(offsetof(nvme_identify_nsid_t, id_fpi) == 32);
275 +CTASSERT(offsetof(nvme_identify_nsid_t, id_nguid) == 104);
276 +CTASSERT(offsetof(nvme_identify_nsid_t, id_lbaf) == 128);
277 +CTASSERT(offsetof(nvme_identify_nsid_t, id_vs) == 384);
278 +
279 +CTASSERT(sizeof (nvme_identify_primary_caps_t) == 0x1000);
280 +CTASSERT(offsetof(nvme_identify_primary_caps_t, nipc_vqfrt) == 32);
281 +CTASSERT(offsetof(nvme_identify_primary_caps_t, nipc_vifrt) == 64);
282 +
283 +
262 284 /* NVMe spec version supported */
263 285 static const int nvme_version_major = 1;
264 -static const int nvme_version_minor = 2;
265 286
266 287 /* tunable for admin command timeout in seconds, default is 1s */
267 288 int nvme_admin_cmd_timeout = 1;
268 289
269 290 /* tunable for FORMAT NVM command timeout in seconds, default is 600s */
270 291 int nvme_format_cmd_timeout = 600;
271 292
272 293 static int nvme_attach(dev_info_t *, ddi_attach_cmd_t);
273 294 static int nvme_detach(dev_info_t *, ddi_detach_cmd_t);
274 295 static int nvme_quiesce(dev_info_t *);
275 296 static int nvme_fm_errcb(dev_info_t *, ddi_fm_error_t *, const void *);
276 297 static int nvme_setup_interrupts(nvme_t *, int, int);
277 298 static void nvme_release_interrupts(nvme_t *);
278 299 static uint_t nvme_intr(caddr_t, caddr_t);
279 300
280 301 static void nvme_shutdown(nvme_t *, int, boolean_t);
281 302 static boolean_t nvme_reset(nvme_t *, boolean_t);
282 303 static int nvme_init(nvme_t *);
283 304 static nvme_cmd_t *nvme_alloc_cmd(nvme_t *, int);
284 305 static void nvme_free_cmd(nvme_cmd_t *);
285 306 static nvme_cmd_t *nvme_create_nvm_cmd(nvme_namespace_t *, uint8_t,
286 307 bd_xfer_t *);
287 308 static void nvme_admin_cmd(nvme_cmd_t *, int);
288 309 static void nvme_submit_admin_cmd(nvme_qpair_t *, nvme_cmd_t *);
289 310 static int nvme_submit_io_cmd(nvme_qpair_t *, nvme_cmd_t *);
290 311 static void nvme_submit_cmd_common(nvme_qpair_t *, nvme_cmd_t *);
291 312 static nvme_cmd_t *nvme_unqueue_cmd(nvme_t *, nvme_qpair_t *, int);
292 313 static nvme_cmd_t *nvme_retrieve_cmd(nvme_t *, nvme_qpair_t *);
293 314 static void nvme_wait_cmd(nvme_cmd_t *, uint_t);
294 315 static void nvme_wakeup_cmd(void *);
295 316 static void nvme_async_event_task(void *);
296 317
297 318 static int nvme_check_unknown_cmd_status(nvme_cmd_t *);
298 319 static int nvme_check_vendor_cmd_status(nvme_cmd_t *);
299 320 static int nvme_check_integrity_cmd_status(nvme_cmd_t *);
300 321 static int nvme_check_specific_cmd_status(nvme_cmd_t *);
301 322 static int nvme_check_generic_cmd_status(nvme_cmd_t *);
302 323 static inline int nvme_check_cmd_status(nvme_cmd_t *);
303 324
304 325 static int nvme_abort_cmd(nvme_cmd_t *, uint_t);
305 326 static void nvme_async_event(nvme_t *);
306 327 static int nvme_format_nvm(nvme_t *, uint32_t, uint8_t, boolean_t, uint8_t,
307 328 boolean_t, uint8_t);
308 329 static int nvme_get_logpage(nvme_t *, void **, size_t *, uint8_t, ...);
309 330 static int nvme_identify(nvme_t *, uint32_t, void **);
310 331 static int nvme_set_features(nvme_t *, uint32_t, uint8_t, uint32_t,
311 332 uint32_t *);
312 333 static int nvme_get_features(nvme_t *, uint32_t, uint8_t, uint32_t *,
313 334 void **, size_t *);
314 335 static int nvme_write_cache_set(nvme_t *, boolean_t);
315 336 static int nvme_set_nqueues(nvme_t *, uint16_t *);
316 337
317 338 static void nvme_free_dma(nvme_dma_t *);
318 339 static int nvme_zalloc_dma(nvme_t *, size_t, uint_t, ddi_dma_attr_t *,
319 340 nvme_dma_t **);
320 341 static int nvme_zalloc_queue_dma(nvme_t *, uint32_t, uint16_t, uint_t,
321 342 nvme_dma_t **);
322 343 static void nvme_free_qpair(nvme_qpair_t *);
323 344 static int nvme_alloc_qpair(nvme_t *, uint32_t, nvme_qpair_t **, int);
324 345 static int nvme_create_io_qpair(nvme_t *, nvme_qpair_t *, uint16_t);
325 346
326 347 static inline void nvme_put64(nvme_t *, uintptr_t, uint64_t);
327 348 static inline void nvme_put32(nvme_t *, uintptr_t, uint32_t);
328 349 static inline uint64_t nvme_get64(nvme_t *, uintptr_t);
329 350 static inline uint32_t nvme_get32(nvme_t *, uintptr_t);
330 351
331 352 static boolean_t nvme_check_regs_hdl(nvme_t *);
332 353 static boolean_t nvme_check_dma_hdl(nvme_dma_t *);
333 354
334 355 static int nvme_fill_prp(nvme_cmd_t *, bd_xfer_t *);
335 356
336 357 static void nvme_bd_xfer_done(void *);
337 358 static void nvme_bd_driveinfo(void *, bd_drive_t *);
338 359 static int nvme_bd_mediainfo(void *, bd_media_t *);
339 360 static int nvme_bd_cmd(nvme_namespace_t *, bd_xfer_t *, uint8_t);
340 361 static int nvme_bd_read(void *, bd_xfer_t *);
341 362 static int nvme_bd_write(void *, bd_xfer_t *);
342 363 static int nvme_bd_sync(void *, bd_xfer_t *);
343 364 static int nvme_bd_devid(void *, dev_info_t *, ddi_devid_t *);
344 365
345 366 static int nvme_prp_dma_constructor(void *, void *, int);
346 367 static void nvme_prp_dma_destructor(void *, void *);
347 368
348 369 static void nvme_prepare_devid(nvme_t *, uint32_t);
349 370
350 371 static int nvme_open(dev_t *, int, int, cred_t *);
351 372 static int nvme_close(dev_t, int, int, cred_t *);
352 373 static int nvme_ioctl(dev_t, int, intptr_t, int, cred_t *, int *);
353 374
354 375 #define NVME_MINOR_INST_SHIFT 9
355 376 #define NVME_MINOR(inst, nsid) (((inst) << NVME_MINOR_INST_SHIFT) | (nsid))
356 377 #define NVME_MINOR_INST(minor) ((minor) >> NVME_MINOR_INST_SHIFT)
357 378 #define NVME_MINOR_NSID(minor) ((minor) & ((1 << NVME_MINOR_INST_SHIFT) - 1))
358 379 #define NVME_MINOR_MAX (NVME_MINOR(1, 0) - 2)
359 380
360 381 static void *nvme_state;
361 382 static kmem_cache_t *nvme_cmd_cache;
362 383
363 384 /*
364 385 * DMA attributes for queue DMA memory
365 386 *
366 387 * Queue DMA memory must be page aligned. The maximum length of a queue is
367 388 * 65536 entries, and an entry can be 64 bytes long.
368 389 */
369 390 static ddi_dma_attr_t nvme_queue_dma_attr = {
370 391 .dma_attr_version = DMA_ATTR_V0,
371 392 .dma_attr_addr_lo = 0,
372 393 .dma_attr_addr_hi = 0xffffffffffffffffULL,
373 394 .dma_attr_count_max = (UINT16_MAX + 1) * sizeof (nvme_sqe_t) - 1,
374 395 .dma_attr_align = 0x1000,
375 396 .dma_attr_burstsizes = 0x7ff,
376 397 .dma_attr_minxfer = 0x1000,
377 398 .dma_attr_maxxfer = (UINT16_MAX + 1) * sizeof (nvme_sqe_t),
378 399 .dma_attr_seg = 0xffffffffffffffffULL,
379 400 .dma_attr_sgllen = 1,
380 401 .dma_attr_granular = 1,
381 402 .dma_attr_flags = 0,
382 403 };
383 404
384 405 /*
385 406 * DMA attributes for transfers using Physical Region Page (PRP) entries
386 407 *
387 408 * A PRP entry describes one page of DMA memory using the page size specified
388 409 * in the controller configuration's memory page size register (CC.MPS). It uses
389 410 * a 64bit base address aligned to this page size. There is no limitation on
390 411 * chaining PRPs together for arbitrarily large DMA transfers.
391 412 */
392 413 static ddi_dma_attr_t nvme_prp_dma_attr = {
393 414 .dma_attr_version = DMA_ATTR_V0,
394 415 .dma_attr_addr_lo = 0,
395 416 .dma_attr_addr_hi = 0xffffffffffffffffULL,
396 417 .dma_attr_count_max = 0xfff,
397 418 .dma_attr_align = 0x1000,
398 419 .dma_attr_burstsizes = 0x7ff,
399 420 .dma_attr_minxfer = 0x1000,
400 421 .dma_attr_maxxfer = 0x1000,
401 422 .dma_attr_seg = 0xfff,
402 423 .dma_attr_sgllen = -1,
403 424 .dma_attr_granular = 1,
404 425 .dma_attr_flags = 0,
405 426 };
406 427
407 428 /*
408 429 * DMA attributes for transfers using scatter/gather lists
409 430 *
410 431 * A SGL entry describes a chunk of DMA memory using a 64bit base address and a
411 432 * 32bit length field. SGL Segment and SGL Last Segment entries require the
412 433 * length to be a multiple of 16 bytes.
413 434 */
414 435 static ddi_dma_attr_t nvme_sgl_dma_attr = {
415 436 .dma_attr_version = DMA_ATTR_V0,
416 437 .dma_attr_addr_lo = 0,
417 438 .dma_attr_addr_hi = 0xffffffffffffffffULL,
418 439 .dma_attr_count_max = 0xffffffffUL,
419 440 .dma_attr_align = 1,
420 441 .dma_attr_burstsizes = 0x7ff,
421 442 .dma_attr_minxfer = 0x10,
422 443 .dma_attr_maxxfer = 0xfffffffffULL,
423 444 .dma_attr_seg = 0xffffffffffffffffULL,
424 445 .dma_attr_sgllen = -1,
425 446 .dma_attr_granular = 0x10,
426 447 .dma_attr_flags = 0
427 448 };
428 449
429 450 static ddi_device_acc_attr_t nvme_reg_acc_attr = {
430 451 .devacc_attr_version = DDI_DEVICE_ATTR_V0,
431 452 .devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC,
432 453 .devacc_attr_dataorder = DDI_STRICTORDER_ACC
433 454 };
434 455
435 456 static struct cb_ops nvme_cb_ops = {
436 457 .cb_open = nvme_open,
437 458 .cb_close = nvme_close,
438 459 .cb_strategy = nodev,
439 460 .cb_print = nodev,
440 461 .cb_dump = nodev,
441 462 .cb_read = nodev,
442 463 .cb_write = nodev,
443 464 .cb_ioctl = nvme_ioctl,
444 465 .cb_devmap = nodev,
445 466 .cb_mmap = nodev,
446 467 .cb_segmap = nodev,
447 468 .cb_chpoll = nochpoll,
448 469 .cb_prop_op = ddi_prop_op,
449 470 .cb_str = 0,
450 471 .cb_flag = D_NEW | D_MP,
451 472 .cb_rev = CB_REV,
452 473 .cb_aread = nodev,
453 474 .cb_awrite = nodev
454 475 };
455 476
456 477 static struct dev_ops nvme_dev_ops = {
457 478 .devo_rev = DEVO_REV,
458 479 .devo_refcnt = 0,
459 480 .devo_getinfo = ddi_no_info,
460 481 .devo_identify = nulldev,
461 482 .devo_probe = nulldev,
462 483 .devo_attach = nvme_attach,
463 484 .devo_detach = nvme_detach,
464 485 .devo_reset = nodev,
465 486 .devo_cb_ops = &nvme_cb_ops,
466 487 .devo_bus_ops = NULL,
467 488 .devo_power = NULL,
468 489 .devo_quiesce = nvme_quiesce,
469 490 };
470 491
471 492 static struct modldrv nvme_modldrv = {
472 493 .drv_modops = &mod_driverops,
473 494 .drv_linkinfo = "NVMe v1.1b",
474 495 .drv_dev_ops = &nvme_dev_ops
475 496 };
476 497
477 498 static struct modlinkage nvme_modlinkage = {
478 499 .ml_rev = MODREV_1,
479 500 .ml_linkage = { &nvme_modldrv, NULL }
480 501 };
481 502
482 503 static bd_ops_t nvme_bd_ops = {
483 504 .o_version = BD_OPS_VERSION_0,
484 505 .o_drive_info = nvme_bd_driveinfo,
485 506 .o_media_info = nvme_bd_mediainfo,
486 507 .o_devid_init = nvme_bd_devid,
487 508 .o_sync_cache = nvme_bd_sync,
488 509 .o_read = nvme_bd_read,
489 510 .o_write = nvme_bd_write,
490 511 };
491 512
492 513 /*
493 514 * This list will hold commands that have timed out and couldn't be aborted.
494 515 * As we don't know what the hardware may still do with the DMA memory we can't
495 516 * free them, so we'll keep them forever on this list where we can easily look
496 517 * at them with mdb.
497 518 */
498 519 static struct list nvme_lost_cmds;
499 520 static kmutex_t nvme_lc_mutex;
500 521
501 522 int
502 523 _init(void)
503 524 {
504 525 int error;
505 526
506 527 error = ddi_soft_state_init(&nvme_state, sizeof (nvme_t), 1);
507 528 if (error != DDI_SUCCESS)
508 529 return (error);
509 530
510 531 nvme_cmd_cache = kmem_cache_create("nvme_cmd_cache",
511 532 sizeof (nvme_cmd_t), 64, NULL, NULL, NULL, NULL, NULL, 0);
512 533
513 534 mutex_init(&nvme_lc_mutex, NULL, MUTEX_DRIVER, NULL);
514 535 list_create(&nvme_lost_cmds, sizeof (nvme_cmd_t),
515 536 offsetof(nvme_cmd_t, nc_list));
516 537
517 538 bd_mod_init(&nvme_dev_ops);
518 539
519 540 error = mod_install(&nvme_modlinkage);
520 541 if (error != DDI_SUCCESS) {
521 542 ddi_soft_state_fini(&nvme_state);
522 543 mutex_destroy(&nvme_lc_mutex);
523 544 list_destroy(&nvme_lost_cmds);
524 545 bd_mod_fini(&nvme_dev_ops);
525 546 }
526 547
527 548 return (error);
528 549 }
529 550
530 551 int
531 552 _fini(void)
532 553 {
533 554 int error;
534 555
535 556 if (!list_is_empty(&nvme_lost_cmds))
536 557 return (DDI_FAILURE);
537 558
538 559 error = mod_remove(&nvme_modlinkage);
539 560 if (error == DDI_SUCCESS) {
540 561 ddi_soft_state_fini(&nvme_state);
541 562 kmem_cache_destroy(nvme_cmd_cache);
542 563 mutex_destroy(&nvme_lc_mutex);
543 564 list_destroy(&nvme_lost_cmds);
544 565 bd_mod_fini(&nvme_dev_ops);
545 566 }
546 567
547 568 return (error);
548 569 }
549 570
550 571 int
551 572 _info(struct modinfo *modinfop)
552 573 {
553 574 return (mod_info(&nvme_modlinkage, modinfop));
554 575 }
555 576
556 577 static inline void
557 578 nvme_put64(nvme_t *nvme, uintptr_t reg, uint64_t val)
558 579 {
559 580 ASSERT(((uintptr_t)(nvme->n_regs + reg) & 0x7) == 0);
560 581
561 582 /*LINTED: E_BAD_PTR_CAST_ALIGN*/
562 583 ddi_put64(nvme->n_regh, (uint64_t *)(nvme->n_regs + reg), val);
563 584 }
564 585
565 586 static inline void
566 587 nvme_put32(nvme_t *nvme, uintptr_t reg, uint32_t val)
567 588 {
568 589 ASSERT(((uintptr_t)(nvme->n_regs + reg) & 0x3) == 0);
569 590
570 591 /*LINTED: E_BAD_PTR_CAST_ALIGN*/
571 592 ddi_put32(nvme->n_regh, (uint32_t *)(nvme->n_regs + reg), val);
572 593 }
573 594
574 595 static inline uint64_t
575 596 nvme_get64(nvme_t *nvme, uintptr_t reg)
576 597 {
577 598 uint64_t val;
578 599
579 600 ASSERT(((uintptr_t)(nvme->n_regs + reg) & 0x7) == 0);
580 601
581 602 /*LINTED: E_BAD_PTR_CAST_ALIGN*/
582 603 val = ddi_get64(nvme->n_regh, (uint64_t *)(nvme->n_regs + reg));
583 604
584 605 return (val);
585 606 }
586 607
587 608 static inline uint32_t
588 609 nvme_get32(nvme_t *nvme, uintptr_t reg)
589 610 {
590 611 uint32_t val;
591 612
592 613 ASSERT(((uintptr_t)(nvme->n_regs + reg) & 0x3) == 0);
593 614
594 615 /*LINTED: E_BAD_PTR_CAST_ALIGN*/
595 616 val = ddi_get32(nvme->n_regh, (uint32_t *)(nvme->n_regs + reg));
596 617
597 618 return (val);
598 619 }
599 620
600 621 static boolean_t
601 622 nvme_check_regs_hdl(nvme_t *nvme)
602 623 {
603 624 ddi_fm_error_t error;
604 625
605 626 ddi_fm_acc_err_get(nvme->n_regh, &error, DDI_FME_VERSION);
606 627
607 628 if (error.fme_status != DDI_FM_OK)
608 629 return (B_TRUE);
609 630
610 631 return (B_FALSE);
611 632 }
612 633
613 634 static boolean_t
614 635 nvme_check_dma_hdl(nvme_dma_t *dma)
615 636 {
616 637 ddi_fm_error_t error;
617 638
618 639 if (dma == NULL)
619 640 return (B_FALSE);
620 641
621 642 ddi_fm_dma_err_get(dma->nd_dmah, &error, DDI_FME_VERSION);
622 643
623 644 if (error.fme_status != DDI_FM_OK)
624 645 return (B_TRUE);
625 646
626 647 return (B_FALSE);
627 648 }
628 649
629 650 static void
630 651 nvme_free_dma_common(nvme_dma_t *dma)
631 652 {
632 653 if (dma->nd_dmah != NULL)
633 654 (void) ddi_dma_unbind_handle(dma->nd_dmah);
634 655 if (dma->nd_acch != NULL)
635 656 ddi_dma_mem_free(&dma->nd_acch);
636 657 if (dma->nd_dmah != NULL)
637 658 ddi_dma_free_handle(&dma->nd_dmah);
638 659 }
639 660
640 661 static void
641 662 nvme_free_dma(nvme_dma_t *dma)
642 663 {
643 664 nvme_free_dma_common(dma);
644 665 kmem_free(dma, sizeof (*dma));
645 666 }
646 667
647 668 /* ARGSUSED */
648 669 static void
649 670 nvme_prp_dma_destructor(void *buf, void *private)
650 671 {
651 672 nvme_dma_t *dma = (nvme_dma_t *)buf;
652 673
653 674 nvme_free_dma_common(dma);
654 675 }
655 676
656 677 static int
657 678 nvme_alloc_dma_common(nvme_t *nvme, nvme_dma_t *dma,
658 679 size_t len, uint_t flags, ddi_dma_attr_t *dma_attr)
659 680 {
660 681 if (ddi_dma_alloc_handle(nvme->n_dip, dma_attr, DDI_DMA_SLEEP, NULL,
661 682 &dma->nd_dmah) != DDI_SUCCESS) {
662 683 /*
663 684 * Due to DDI_DMA_SLEEP this can't be DDI_DMA_NORESOURCES, and
664 685 * the only other possible error is DDI_DMA_BADATTR which
665 686 * indicates a driver bug which should cause a panic.
666 687 */
667 688 dev_err(nvme->n_dip, CE_PANIC,
668 689 "!failed to get DMA handle, check DMA attributes");
669 690 return (DDI_FAILURE);
670 691 }
671 692
672 693 /*
673 694 * ddi_dma_mem_alloc() can only fail when DDI_DMA_NOSLEEP is specified
674 695 * or the flags are conflicting, which isn't the case here.
675 696 */
676 697 (void) ddi_dma_mem_alloc(dma->nd_dmah, len, &nvme->n_reg_acc_attr,
677 698 DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, NULL, &dma->nd_memp,
678 699 &dma->nd_len, &dma->nd_acch);
679 700
680 701 if (ddi_dma_addr_bind_handle(dma->nd_dmah, NULL, dma->nd_memp,
681 702 dma->nd_len, flags | DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, NULL,
682 703 &dma->nd_cookie, &dma->nd_ncookie) != DDI_DMA_MAPPED) {
683 704 dev_err(nvme->n_dip, CE_WARN,
684 705 "!failed to bind DMA memory");
685 706 atomic_inc_32(&nvme->n_dma_bind_err);
686 707 nvme_free_dma_common(dma);
687 708 return (DDI_FAILURE);
688 709 }
689 710
690 711 return (DDI_SUCCESS);
691 712 }
692 713
693 714 static int
694 715 nvme_zalloc_dma(nvme_t *nvme, size_t len, uint_t flags,
695 716 ddi_dma_attr_t *dma_attr, nvme_dma_t **ret)
696 717 {
697 718 nvme_dma_t *dma = kmem_zalloc(sizeof (nvme_dma_t), KM_SLEEP);
698 719
699 720 if (nvme_alloc_dma_common(nvme, dma, len, flags, dma_attr) !=
700 721 DDI_SUCCESS) {
701 722 *ret = NULL;
702 723 kmem_free(dma, sizeof (nvme_dma_t));
703 724 return (DDI_FAILURE);
704 725 }
705 726
706 727 bzero(dma->nd_memp, dma->nd_len);
707 728
708 729 *ret = dma;
709 730 return (DDI_SUCCESS);
710 731 }
711 732
712 733 /* ARGSUSED */
713 734 static int
714 735 nvme_prp_dma_constructor(void *buf, void *private, int flags)
715 736 {
716 737 nvme_dma_t *dma = (nvme_dma_t *)buf;
717 738 nvme_t *nvme = (nvme_t *)private;
718 739
719 740 dma->nd_dmah = NULL;
720 741 dma->nd_acch = NULL;
721 742
722 743 if (nvme_alloc_dma_common(nvme, dma, nvme->n_pagesize,
723 744 DDI_DMA_READ, &nvme->n_prp_dma_attr) != DDI_SUCCESS) {
724 745 return (-1);
725 746 }
726 747
727 748 ASSERT(dma->nd_ncookie == 1);
728 749
729 750 dma->nd_cached = B_TRUE;
730 751
731 752 return (0);
732 753 }
733 754
734 755 static int
735 756 nvme_zalloc_queue_dma(nvme_t *nvme, uint32_t nentry, uint16_t qe_len,
736 757 uint_t flags, nvme_dma_t **dma)
737 758 {
738 759 uint32_t len = nentry * qe_len;
739 760 ddi_dma_attr_t q_dma_attr = nvme->n_queue_dma_attr;
740 761
741 762 len = roundup(len, nvme->n_pagesize);
742 763
743 764 q_dma_attr.dma_attr_minxfer = len;
744 765
745 766 if (nvme_zalloc_dma(nvme, len, flags, &q_dma_attr, dma)
746 767 != DDI_SUCCESS) {
747 768 dev_err(nvme->n_dip, CE_WARN,
748 769 "!failed to get DMA memory for queue");
749 770 goto fail;
750 771 }
751 772
752 773 if ((*dma)->nd_ncookie != 1) {
753 774 dev_err(nvme->n_dip, CE_WARN,
754 775 "!got too many cookies for queue DMA");
755 776 goto fail;
756 777 }
757 778
758 779 return (DDI_SUCCESS);
759 780
760 781 fail:
761 782 if (*dma) {
762 783 nvme_free_dma(*dma);
763 784 *dma = NULL;
764 785 }
765 786
766 787 return (DDI_FAILURE);
767 788 }
768 789
769 790 static void
770 791 nvme_free_qpair(nvme_qpair_t *qp)
771 792 {
772 793 int i;
773 794
774 795 mutex_destroy(&qp->nq_mutex);
775 796 sema_destroy(&qp->nq_sema);
776 797
777 798 if (qp->nq_sqdma != NULL)
778 799 nvme_free_dma(qp->nq_sqdma);
779 800 if (qp->nq_cqdma != NULL)
780 801 nvme_free_dma(qp->nq_cqdma);
781 802
782 803 if (qp->nq_active_cmds > 0)
783 804 for (i = 0; i != qp->nq_nentry; i++)
784 805 if (qp->nq_cmd[i] != NULL)
785 806 nvme_free_cmd(qp->nq_cmd[i]);
786 807
787 808 if (qp->nq_cmd != NULL)
788 809 kmem_free(qp->nq_cmd, sizeof (nvme_cmd_t *) * qp->nq_nentry);
789 810
790 811 kmem_free(qp, sizeof (nvme_qpair_t));
791 812 }
792 813
793 814 static int
794 815 nvme_alloc_qpair(nvme_t *nvme, uint32_t nentry, nvme_qpair_t **nqp,
795 816 int idx)
796 817 {
797 818 nvme_qpair_t *qp = kmem_zalloc(sizeof (*qp), KM_SLEEP);
798 819
799 820 mutex_init(&qp->nq_mutex, NULL, MUTEX_DRIVER,
800 821 DDI_INTR_PRI(nvme->n_intr_pri));
801 822 sema_init(&qp->nq_sema, nentry, NULL, SEMA_DRIVER, NULL);
802 823
803 824 if (nvme_zalloc_queue_dma(nvme, nentry, sizeof (nvme_sqe_t),
804 825 DDI_DMA_WRITE, &qp->nq_sqdma) != DDI_SUCCESS)
805 826 goto fail;
806 827
807 828 if (nvme_zalloc_queue_dma(nvme, nentry, sizeof (nvme_cqe_t),
808 829 DDI_DMA_READ, &qp->nq_cqdma) != DDI_SUCCESS)
809 830 goto fail;
810 831
811 832 qp->nq_sq = (nvme_sqe_t *)qp->nq_sqdma->nd_memp;
812 833 qp->nq_cq = (nvme_cqe_t *)qp->nq_cqdma->nd_memp;
813 834 qp->nq_nentry = nentry;
814 835
815 836 qp->nq_sqtdbl = NVME_REG_SQTDBL(nvme, idx);
816 837 qp->nq_cqhdbl = NVME_REG_CQHDBL(nvme, idx);
817 838
818 839 qp->nq_cmd = kmem_zalloc(sizeof (nvme_cmd_t *) * nentry, KM_SLEEP);
819 840 qp->nq_next_cmd = 0;
820 841
821 842 *nqp = qp;
822 843 return (DDI_SUCCESS);
823 844
824 845 fail:
825 846 nvme_free_qpair(qp);
826 847 *nqp = NULL;
827 848
828 849 return (DDI_FAILURE);
829 850 }
830 851
831 852 static nvme_cmd_t *
832 853 nvme_alloc_cmd(nvme_t *nvme, int kmflag)
833 854 {
834 855 nvme_cmd_t *cmd = kmem_cache_alloc(nvme_cmd_cache, kmflag);
835 856
836 857 if (cmd == NULL)
837 858 return (cmd);
838 859
839 860 bzero(cmd, sizeof (nvme_cmd_t));
840 861
841 862 cmd->nc_nvme = nvme;
842 863
843 864 mutex_init(&cmd->nc_mutex, NULL, MUTEX_DRIVER,
844 865 DDI_INTR_PRI(nvme->n_intr_pri));
845 866 cv_init(&cmd->nc_cv, NULL, CV_DRIVER, NULL);
846 867
847 868 return (cmd);
848 869 }
849 870
850 871 static void
851 872 nvme_free_cmd(nvme_cmd_t *cmd)
852 873 {
853 874 /* Don't free commands on the lost commands list. */
854 875 if (list_link_active(&cmd->nc_list))
855 876 return;
856 877
857 878 if (cmd->nc_dma) {
858 879 if (cmd->nc_dma->nd_cached)
859 880 kmem_cache_free(cmd->nc_nvme->n_prp_cache,
860 881 cmd->nc_dma);
861 882 else
862 883 nvme_free_dma(cmd->nc_dma);
863 884 cmd->nc_dma = NULL;
864 885 }
865 886
866 887 cv_destroy(&cmd->nc_cv);
867 888 mutex_destroy(&cmd->nc_mutex);
868 889
869 890 kmem_cache_free(nvme_cmd_cache, cmd);
870 891 }
871 892
872 893 static void
873 894 nvme_submit_admin_cmd(nvme_qpair_t *qp, nvme_cmd_t *cmd)
874 895 {
875 896 sema_p(&qp->nq_sema);
876 897 nvme_submit_cmd_common(qp, cmd);
877 898 }
878 899
879 900 static int
880 901 nvme_submit_io_cmd(nvme_qpair_t *qp, nvme_cmd_t *cmd)
881 902 {
882 903 if (sema_tryp(&qp->nq_sema) == 0)
883 904 return (EAGAIN);
884 905
885 906 nvme_submit_cmd_common(qp, cmd);
886 907 return (0);
887 908 }
888 909
889 910 static void
890 911 nvme_submit_cmd_common(nvme_qpair_t *qp, nvme_cmd_t *cmd)
891 912 {
892 913 nvme_reg_sqtdbl_t tail = { 0 };
893 914
894 915 mutex_enter(&qp->nq_mutex);
895 916 cmd->nc_completed = B_FALSE;
896 917
897 918 /*
898 919 * Try to insert the cmd into the active cmd array at the nq_next_cmd
899 920 * slot. If the slot is already occupied advance to the next slot and
900 921 * try again. This can happen for long running commands like async event
901 922 * requests.
902 923 */
903 924 while (qp->nq_cmd[qp->nq_next_cmd] != NULL)
904 925 qp->nq_next_cmd = (qp->nq_next_cmd + 1) % qp->nq_nentry;
905 926 qp->nq_cmd[qp->nq_next_cmd] = cmd;
906 927
907 928 qp->nq_active_cmds++;
908 929
909 930 cmd->nc_sqe.sqe_cid = qp->nq_next_cmd;
910 931 bcopy(&cmd->nc_sqe, &qp->nq_sq[qp->nq_sqtail], sizeof (nvme_sqe_t));
911 932 (void) ddi_dma_sync(qp->nq_sqdma->nd_dmah,
912 933 sizeof (nvme_sqe_t) * qp->nq_sqtail,
913 934 sizeof (nvme_sqe_t), DDI_DMA_SYNC_FORDEV);
914 935 qp->nq_next_cmd = (qp->nq_next_cmd + 1) % qp->nq_nentry;
915 936
916 937 tail.b.sqtdbl_sqt = qp->nq_sqtail = (qp->nq_sqtail + 1) % qp->nq_nentry;
917 938 nvme_put32(cmd->nc_nvme, qp->nq_sqtdbl, tail.r);
918 939
919 940 mutex_exit(&qp->nq_mutex);
920 941 }
921 942
922 943 static nvme_cmd_t *
923 944 nvme_unqueue_cmd(nvme_t *nvme, nvme_qpair_t *qp, int cid)
924 945 {
925 946 nvme_cmd_t *cmd;
926 947
927 948 ASSERT(mutex_owned(&qp->nq_mutex));
928 949 ASSERT3S(cid, <, qp->nq_nentry);
929 950
930 951 cmd = qp->nq_cmd[cid];
931 952 qp->nq_cmd[cid] = NULL;
932 953 ASSERT3U(qp->nq_active_cmds, >, 0);
933 954 qp->nq_active_cmds--;
934 955 sema_v(&qp->nq_sema);
935 956
936 957 ASSERT3P(cmd, !=, NULL);
937 958 ASSERT3P(cmd->nc_nvme, ==, nvme);
938 959 ASSERT3S(cmd->nc_sqe.sqe_cid, ==, cid);
939 960
940 961 return (cmd);
941 962 }
942 963
943 964 static nvme_cmd_t *
944 965 nvme_retrieve_cmd(nvme_t *nvme, nvme_qpair_t *qp)
945 966 {
946 967 nvme_reg_cqhdbl_t head = { 0 };
947 968
948 969 nvme_cqe_t *cqe;
949 970 nvme_cmd_t *cmd;
950 971
951 972 (void) ddi_dma_sync(qp->nq_cqdma->nd_dmah, 0,
952 973 sizeof (nvme_cqe_t) * qp->nq_nentry, DDI_DMA_SYNC_FORKERNEL);
953 974
954 975 mutex_enter(&qp->nq_mutex);
955 976 cqe = &qp->nq_cq[qp->nq_cqhead];
956 977
957 978 /* Check phase tag of CQE. Hardware inverts it for new entries. */
958 979 if (cqe->cqe_sf.sf_p == qp->nq_phase) {
959 980 mutex_exit(&qp->nq_mutex);
960 981 return (NULL);
961 982 }
962 983
963 984 ASSERT(nvme->n_ioq[cqe->cqe_sqid] == qp);
964 985
965 986 cmd = nvme_unqueue_cmd(nvme, qp, cqe->cqe_cid);
966 987
967 988 ASSERT(cmd->nc_sqid == cqe->cqe_sqid);
968 989 bcopy(cqe, &cmd->nc_cqe, sizeof (nvme_cqe_t));
969 990
970 991 qp->nq_sqhead = cqe->cqe_sqhd;
971 992
972 993 head.b.cqhdbl_cqh = qp->nq_cqhead = (qp->nq_cqhead + 1) % qp->nq_nentry;
973 994
974 995 /* Toggle phase on wrap-around. */
975 996 if (qp->nq_cqhead == 0)
976 997 qp->nq_phase = qp->nq_phase ? 0 : 1;
977 998
978 999 nvme_put32(cmd->nc_nvme, qp->nq_cqhdbl, head.r);
979 1000 mutex_exit(&qp->nq_mutex);
980 1001
981 1002 return (cmd);
982 1003 }
983 1004
984 1005 static int
985 1006 nvme_check_unknown_cmd_status(nvme_cmd_t *cmd)
986 1007 {
987 1008 nvme_cqe_t *cqe = &cmd->nc_cqe;
988 1009
989 1010 dev_err(cmd->nc_nvme->n_dip, CE_WARN,
990 1011 "!unknown command status received: opc = %x, sqid = %d, cid = %d, "
991 1012 "sc = %x, sct = %x, dnr = %d, m = %d", cmd->nc_sqe.sqe_opc,
992 1013 cqe->cqe_sqid, cqe->cqe_cid, cqe->cqe_sf.sf_sc, cqe->cqe_sf.sf_sct,
993 1014 cqe->cqe_sf.sf_dnr, cqe->cqe_sf.sf_m);
994 1015
995 1016 if (cmd->nc_xfer != NULL)
996 1017 bd_error(cmd->nc_xfer, BD_ERR_ILLRQ);
997 1018
998 1019 if (cmd->nc_nvme->n_strict_version) {
999 1020 cmd->nc_nvme->n_dead = B_TRUE;
1000 1021 ddi_fm_service_impact(cmd->nc_nvme->n_dip, DDI_SERVICE_LOST);
1001 1022 }
1002 1023
1003 1024 return (EIO);
1004 1025 }
1005 1026
1006 1027 static int
1007 1028 nvme_check_vendor_cmd_status(nvme_cmd_t *cmd)
1008 1029 {
1009 1030 nvme_cqe_t *cqe = &cmd->nc_cqe;
1010 1031
1011 1032 dev_err(cmd->nc_nvme->n_dip, CE_WARN,
1012 1033 "!unknown command status received: opc = %x, sqid = %d, cid = %d, "
1013 1034 "sc = %x, sct = %x, dnr = %d, m = %d", cmd->nc_sqe.sqe_opc,
1014 1035 cqe->cqe_sqid, cqe->cqe_cid, cqe->cqe_sf.sf_sc, cqe->cqe_sf.sf_sct,
1015 1036 cqe->cqe_sf.sf_dnr, cqe->cqe_sf.sf_m);
1016 1037 if (!cmd->nc_nvme->n_ignore_unknown_vendor_status) {
1017 1038 cmd->nc_nvme->n_dead = B_TRUE;
1018 1039 ddi_fm_service_impact(cmd->nc_nvme->n_dip, DDI_SERVICE_LOST);
1019 1040 }
1020 1041
1021 1042 return (EIO);
1022 1043 }
1023 1044
1024 1045 static int
1025 1046 nvme_check_integrity_cmd_status(nvme_cmd_t *cmd)
1026 1047 {
1027 1048 nvme_cqe_t *cqe = &cmd->nc_cqe;
1028 1049
1029 1050 switch (cqe->cqe_sf.sf_sc) {
1030 1051 case NVME_CQE_SC_INT_NVM_WRITE:
1031 1052 /* write fail */
1032 1053 /* TODO: post ereport */
1033 1054 if (cmd->nc_xfer != NULL)
1034 1055 bd_error(cmd->nc_xfer, BD_ERR_MEDIA);
1035 1056 return (EIO);
1036 1057
1037 1058 case NVME_CQE_SC_INT_NVM_READ:
1038 1059 /* read fail */
1039 1060 /* TODO: post ereport */
1040 1061 if (cmd->nc_xfer != NULL)
1041 1062 bd_error(cmd->nc_xfer, BD_ERR_MEDIA);
1042 1063 return (EIO);
1043 1064
1044 1065 default:
1045 1066 return (nvme_check_unknown_cmd_status(cmd));
1046 1067 }
1047 1068 }
1048 1069
1049 1070 static int
1050 1071 nvme_check_generic_cmd_status(nvme_cmd_t *cmd)
1051 1072 {
1052 1073 nvme_cqe_t *cqe = &cmd->nc_cqe;
1053 1074
1054 1075 switch (cqe->cqe_sf.sf_sc) {
1055 1076 case NVME_CQE_SC_GEN_SUCCESS:
1056 1077 return (0);
1057 1078
1058 1079 /*
1059 1080 * Errors indicating a bug in the driver should cause a panic.
1060 1081 */
1061 1082 case NVME_CQE_SC_GEN_INV_OPC:
1062 1083 /* Invalid Command Opcode */
1063 1084 if (!cmd->nc_dontpanic)
1064 1085 dev_err(cmd->nc_nvme->n_dip, CE_PANIC,
1065 1086 "programming error: invalid opcode in cmd %p",
1066 1087 (void *)cmd);
1067 1088 return (EINVAL);
1068 1089
1069 1090 case NVME_CQE_SC_GEN_INV_FLD:
1070 1091 /* Invalid Field in Command */
1071 1092 if (!cmd->nc_dontpanic)
1072 1093 dev_err(cmd->nc_nvme->n_dip, CE_PANIC,
1073 1094 "programming error: invalid field in cmd %p",
1074 1095 (void *)cmd);
1075 1096 return (EIO);
1076 1097
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1077 1098 case NVME_CQE_SC_GEN_ID_CNFL:
1078 1099 /* Command ID Conflict */
1079 1100 dev_err(cmd->nc_nvme->n_dip, CE_PANIC, "programming error: "
1080 1101 "cmd ID conflict in cmd %p", (void *)cmd);
1081 1102 return (0);
1082 1103
1083 1104 case NVME_CQE_SC_GEN_INV_NS:
1084 1105 /* Invalid Namespace or Format */
1085 1106 if (!cmd->nc_dontpanic)
1086 1107 dev_err(cmd->nc_nvme->n_dip, CE_PANIC,
1087 - "programming error: " "invalid NS/format in cmd %p",
1108 + "programming error: invalid NS/format in cmd %p",
1088 1109 (void *)cmd);
1089 1110 return (EINVAL);
1090 1111
1091 1112 case NVME_CQE_SC_GEN_NVM_LBA_RANGE:
1092 1113 /* LBA Out Of Range */
1093 1114 dev_err(cmd->nc_nvme->n_dip, CE_PANIC, "programming error: "
1094 1115 "LBA out of range in cmd %p", (void *)cmd);
1095 1116 return (0);
1096 1117
1097 1118 /*
1098 1119 * Non-fatal errors, handle gracefully.
1099 1120 */
1100 1121 case NVME_CQE_SC_GEN_DATA_XFR_ERR:
1101 1122 /* Data Transfer Error (DMA) */
1102 1123 /* TODO: post ereport */
1103 1124 atomic_inc_32(&cmd->nc_nvme->n_data_xfr_err);
1104 1125 if (cmd->nc_xfer != NULL)
1105 1126 bd_error(cmd->nc_xfer, BD_ERR_NTRDY);
1106 1127 return (EIO);
1107 1128
1108 1129 case NVME_CQE_SC_GEN_INTERNAL_ERR:
1109 1130 /*
1110 1131 * Internal Error. The spec (v1.0, section 4.5.1.2) says
1111 1132 * detailed error information is returned as async event,
1112 1133 * so we pretty much ignore the error here and handle it
1113 1134 * in the async event handler.
1114 1135 */
1115 1136 atomic_inc_32(&cmd->nc_nvme->n_internal_err);
1116 1137 if (cmd->nc_xfer != NULL)
1117 1138 bd_error(cmd->nc_xfer, BD_ERR_NTRDY);
1118 1139 return (EIO);
1119 1140
1120 1141 case NVME_CQE_SC_GEN_ABORT_REQUEST:
1121 1142 /*
1122 1143 * Command Abort Requested. This normally happens only when a
1123 1144 * command times out.
1124 1145 */
1125 1146 /* TODO: post ereport or change blkdev to handle this? */
1126 1147 atomic_inc_32(&cmd->nc_nvme->n_abort_rq_err);
1127 1148 return (ECANCELED);
1128 1149
1129 1150 case NVME_CQE_SC_GEN_ABORT_PWRLOSS:
1130 1151 /* Command Aborted due to Power Loss Notification */
1131 1152 ddi_fm_service_impact(cmd->nc_nvme->n_dip, DDI_SERVICE_LOST);
1132 1153 cmd->nc_nvme->n_dead = B_TRUE;
1133 1154 return (EIO);
1134 1155
1135 1156 case NVME_CQE_SC_GEN_ABORT_SQ_DEL:
1136 1157 /* Command Aborted due to SQ Deletion */
1137 1158 atomic_inc_32(&cmd->nc_nvme->n_abort_sq_del);
1138 1159 return (EIO);
1139 1160
1140 1161 case NVME_CQE_SC_GEN_NVM_CAP_EXC:
1141 1162 /* Capacity Exceeded */
1142 1163 atomic_inc_32(&cmd->nc_nvme->n_nvm_cap_exc);
1143 1164 if (cmd->nc_xfer != NULL)
1144 1165 bd_error(cmd->nc_xfer, BD_ERR_MEDIA);
1145 1166 return (EIO);
1146 1167
1147 1168 case NVME_CQE_SC_GEN_NVM_NS_NOTRDY:
1148 1169 /* Namespace Not Ready */
1149 1170 atomic_inc_32(&cmd->nc_nvme->n_nvm_ns_notrdy);
1150 1171 if (cmd->nc_xfer != NULL)
1151 1172 bd_error(cmd->nc_xfer, BD_ERR_NTRDY);
1152 1173 return (EIO);
1153 1174
1154 1175 default:
1155 1176 return (nvme_check_unknown_cmd_status(cmd));
1156 1177 }
1157 1178 }
1158 1179
1159 1180 static int
1160 1181 nvme_check_specific_cmd_status(nvme_cmd_t *cmd)
1161 1182 {
1162 1183 nvme_cqe_t *cqe = &cmd->nc_cqe;
1163 1184
1164 1185 switch (cqe->cqe_sf.sf_sc) {
1165 1186 case NVME_CQE_SC_SPC_INV_CQ:
1166 1187 /* Completion Queue Invalid */
1167 1188 ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_CREATE_SQUEUE);
1168 1189 atomic_inc_32(&cmd->nc_nvme->n_inv_cq_err);
1169 1190 return (EINVAL);
1170 1191
1171 1192 case NVME_CQE_SC_SPC_INV_QID:
1172 1193 /* Invalid Queue Identifier */
1173 1194 ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_CREATE_SQUEUE ||
1174 1195 cmd->nc_sqe.sqe_opc == NVME_OPC_DELETE_SQUEUE ||
1175 1196 cmd->nc_sqe.sqe_opc == NVME_OPC_CREATE_CQUEUE ||
1176 1197 cmd->nc_sqe.sqe_opc == NVME_OPC_DELETE_CQUEUE);
1177 1198 atomic_inc_32(&cmd->nc_nvme->n_inv_qid_err);
1178 1199 return (EINVAL);
1179 1200
1180 1201 case NVME_CQE_SC_SPC_MAX_QSZ_EXC:
1181 1202 /* Max Queue Size Exceeded */
1182 1203 ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_CREATE_SQUEUE ||
1183 1204 cmd->nc_sqe.sqe_opc == NVME_OPC_CREATE_CQUEUE);
1184 1205 atomic_inc_32(&cmd->nc_nvme->n_max_qsz_exc);
1185 1206 return (EINVAL);
1186 1207
1187 1208 case NVME_CQE_SC_SPC_ABRT_CMD_EXC:
1188 1209 /* Abort Command Limit Exceeded */
1189 1210 ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_ABORT);
1190 1211 dev_err(cmd->nc_nvme->n_dip, CE_PANIC, "programming error: "
1191 1212 "abort command limit exceeded in cmd %p", (void *)cmd);
1192 1213 return (0);
1193 1214
1194 1215 case NVME_CQE_SC_SPC_ASYNC_EVREQ_EXC:
1195 1216 /* Async Event Request Limit Exceeded */
1196 1217 ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_ASYNC_EVENT);
1197 1218 dev_err(cmd->nc_nvme->n_dip, CE_PANIC, "programming error: "
1198 1219 "async event request limit exceeded in cmd %p",
1199 1220 (void *)cmd);
1200 1221 return (0);
1201 1222
1202 1223 case NVME_CQE_SC_SPC_INV_INT_VECT:
1203 1224 /* Invalid Interrupt Vector */
1204 1225 ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_CREATE_CQUEUE);
1205 1226 atomic_inc_32(&cmd->nc_nvme->n_inv_int_vect);
1206 1227 return (EINVAL);
1207 1228
1208 1229 case NVME_CQE_SC_SPC_INV_LOG_PAGE:
1209 1230 /* Invalid Log Page */
1210 1231 ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_GET_LOG_PAGE);
1211 1232 atomic_inc_32(&cmd->nc_nvme->n_inv_log_page);
1212 1233 return (EINVAL);
1213 1234
1214 1235 case NVME_CQE_SC_SPC_INV_FORMAT:
1215 1236 /* Invalid Format */
1216 1237 ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_NVM_FORMAT);
1217 1238 atomic_inc_32(&cmd->nc_nvme->n_inv_format);
1218 1239 if (cmd->nc_xfer != NULL)
1219 1240 bd_error(cmd->nc_xfer, BD_ERR_ILLRQ);
1220 1241 return (EINVAL);
1221 1242
1222 1243 case NVME_CQE_SC_SPC_INV_Q_DEL:
1223 1244 /* Invalid Queue Deletion */
1224 1245 ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_DELETE_CQUEUE);
1225 1246 atomic_inc_32(&cmd->nc_nvme->n_inv_q_del);
1226 1247 return (EINVAL);
1227 1248
1228 1249 case NVME_CQE_SC_SPC_NVM_CNFL_ATTR:
1229 1250 /* Conflicting Attributes */
1230 1251 ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_NVM_DSET_MGMT ||
1231 1252 cmd->nc_sqe.sqe_opc == NVME_OPC_NVM_READ ||
1232 1253 cmd->nc_sqe.sqe_opc == NVME_OPC_NVM_WRITE);
1233 1254 atomic_inc_32(&cmd->nc_nvme->n_cnfl_attr);
1234 1255 if (cmd->nc_xfer != NULL)
1235 1256 bd_error(cmd->nc_xfer, BD_ERR_ILLRQ);
1236 1257 return (EINVAL);
1237 1258
1238 1259 case NVME_CQE_SC_SPC_NVM_INV_PROT:
1239 1260 /* Invalid Protection Information */
1240 1261 ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_NVM_COMPARE ||
1241 1262 cmd->nc_sqe.sqe_opc == NVME_OPC_NVM_READ ||
1242 1263 cmd->nc_sqe.sqe_opc == NVME_OPC_NVM_WRITE);
1243 1264 atomic_inc_32(&cmd->nc_nvme->n_inv_prot);
1244 1265 if (cmd->nc_xfer != NULL)
1245 1266 bd_error(cmd->nc_xfer, BD_ERR_ILLRQ);
1246 1267 return (EINVAL);
1247 1268
1248 1269 case NVME_CQE_SC_SPC_NVM_READONLY:
1249 1270 /* Write to Read Only Range */
1250 1271 ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_NVM_WRITE);
1251 1272 atomic_inc_32(&cmd->nc_nvme->n_readonly);
1252 1273 if (cmd->nc_xfer != NULL)
1253 1274 bd_error(cmd->nc_xfer, BD_ERR_ILLRQ);
1254 1275 return (EROFS);
1255 1276
1256 1277 default:
1257 1278 return (nvme_check_unknown_cmd_status(cmd));
1258 1279 }
1259 1280 }
1260 1281
1261 1282 static inline int
1262 1283 nvme_check_cmd_status(nvme_cmd_t *cmd)
1263 1284 {
1264 1285 nvme_cqe_t *cqe = &cmd->nc_cqe;
1265 1286
1266 1287 /*
1267 1288 * Take a shortcut if the controller is dead, or if
1268 1289 * command status indicates no error.
1269 1290 */
1270 1291 if (cmd->nc_nvme->n_dead)
1271 1292 return (EIO);
1272 1293
1273 1294 if (cqe->cqe_sf.sf_sct == NVME_CQE_SCT_GENERIC &&
1274 1295 cqe->cqe_sf.sf_sc == NVME_CQE_SC_GEN_SUCCESS)
1275 1296 return (0);
1276 1297
1277 1298 if (cqe->cqe_sf.sf_sct == NVME_CQE_SCT_GENERIC)
1278 1299 return (nvme_check_generic_cmd_status(cmd));
1279 1300 else if (cqe->cqe_sf.sf_sct == NVME_CQE_SCT_SPECIFIC)
1280 1301 return (nvme_check_specific_cmd_status(cmd));
1281 1302 else if (cqe->cqe_sf.sf_sct == NVME_CQE_SCT_INTEGRITY)
1282 1303 return (nvme_check_integrity_cmd_status(cmd));
1283 1304 else if (cqe->cqe_sf.sf_sct == NVME_CQE_SCT_VENDOR)
1284 1305 return (nvme_check_vendor_cmd_status(cmd));
1285 1306
1286 1307 return (nvme_check_unknown_cmd_status(cmd));
1287 1308 }
1288 1309
1289 1310 static int
1290 1311 nvme_abort_cmd(nvme_cmd_t *abort_cmd, uint_t sec)
1291 1312 {
1292 1313 nvme_t *nvme = abort_cmd->nc_nvme;
1293 1314 nvme_cmd_t *cmd = nvme_alloc_cmd(nvme, KM_SLEEP);
1294 1315 nvme_abort_cmd_t ac = { 0 };
1295 1316 int ret = 0;
1296 1317
1297 1318 sema_p(&nvme->n_abort_sema);
1298 1319
1299 1320 ac.b.ac_cid = abort_cmd->nc_sqe.sqe_cid;
1300 1321 ac.b.ac_sqid = abort_cmd->nc_sqid;
1301 1322
1302 1323 cmd->nc_sqid = 0;
1303 1324 cmd->nc_sqe.sqe_opc = NVME_OPC_ABORT;
1304 1325 cmd->nc_callback = nvme_wakeup_cmd;
1305 1326 cmd->nc_sqe.sqe_cdw10 = ac.r;
1306 1327
1307 1328 /*
1308 1329 * Send the ABORT to the hardware. The ABORT command will return _after_
1309 1330 * the aborted command has completed (aborted or otherwise), but since
1310 1331 * we still hold the aborted command's mutex its callback hasn't been
1311 1332 * processed yet.
1312 1333 */
1313 1334 nvme_admin_cmd(cmd, sec);
1314 1335 sema_v(&nvme->n_abort_sema);
1315 1336
1316 1337 if ((ret = nvme_check_cmd_status(cmd)) != 0) {
1317 1338 dev_err(nvme->n_dip, CE_WARN,
1318 1339 "!ABORT failed with sct = %x, sc = %x",
1319 1340 cmd->nc_cqe.cqe_sf.sf_sct, cmd->nc_cqe.cqe_sf.sf_sc);
1320 1341 atomic_inc_32(&nvme->n_abort_failed);
1321 1342 } else {
1322 1343 dev_err(nvme->n_dip, CE_WARN,
1323 1344 "!ABORT of command %d/%d %ssuccessful",
1324 1345 abort_cmd->nc_sqe.sqe_cid, abort_cmd->nc_sqid,
1325 1346 cmd->nc_cqe.cqe_dw0 & 1 ? "un" : "");
1326 1347 if ((cmd->nc_cqe.cqe_dw0 & 1) == 0)
1327 1348 atomic_inc_32(&nvme->n_cmd_aborted);
1328 1349 }
1329 1350
1330 1351 nvme_free_cmd(cmd);
1331 1352 return (ret);
1332 1353 }
1333 1354
1334 1355 /*
1335 1356 * nvme_wait_cmd -- wait for command completion or timeout
1336 1357 *
1337 1358 * In case of a serious error or a timeout of the abort command the hardware
1338 1359 * will be declared dead and FMA will be notified.
1339 1360 */
1340 1361 static void
1341 1362 nvme_wait_cmd(nvme_cmd_t *cmd, uint_t sec)
1342 1363 {
1343 1364 clock_t timeout = ddi_get_lbolt() + drv_usectohz(sec * MICROSEC);
1344 1365 nvme_t *nvme = cmd->nc_nvme;
1345 1366 nvme_reg_csts_t csts;
1346 1367 nvme_qpair_t *qp;
1347 1368
1348 1369 ASSERT(mutex_owned(&cmd->nc_mutex));
1349 1370
1350 1371 while (!cmd->nc_completed) {
1351 1372 if (cv_timedwait(&cmd->nc_cv, &cmd->nc_mutex, timeout) == -1)
1352 1373 break;
1353 1374 }
1354 1375
1355 1376 if (cmd->nc_completed)
1356 1377 return;
1357 1378
1358 1379 /*
1359 1380 * The command timed out.
1360 1381 *
1361 1382 * Check controller for fatal status, any errors associated with the
1362 1383 * register or DMA handle, or for a double timeout (abort command timed
1363 1384 * out). If necessary log a warning and call FMA.
1364 1385 */
1365 1386 csts.r = nvme_get32(nvme, NVME_REG_CSTS);
1366 1387 dev_err(nvme->n_dip, CE_WARN, "!command %d/%d timeout, "
1367 1388 "OPC = %x, CFS = %d", cmd->nc_sqe.sqe_cid, cmd->nc_sqid,
1368 1389 cmd->nc_sqe.sqe_opc, csts.b.csts_cfs);
1369 1390 atomic_inc_32(&nvme->n_cmd_timeout);
1370 1391
1371 1392 if (csts.b.csts_cfs ||
1372 1393 nvme_check_regs_hdl(nvme) ||
1373 1394 nvme_check_dma_hdl(cmd->nc_dma) ||
1374 1395 cmd->nc_sqe.sqe_opc == NVME_OPC_ABORT) {
1375 1396 ddi_fm_service_impact(nvme->n_dip, DDI_SERVICE_LOST);
1376 1397 nvme->n_dead = B_TRUE;
1377 1398 } else if (nvme_abort_cmd(cmd, sec) == 0) {
1378 1399 /*
1379 1400 * If the abort succeeded the command should complete
1380 1401 * immediately with an appropriate status.
1381 1402 */
1382 1403 while (!cmd->nc_completed)
1383 1404 cv_wait(&cmd->nc_cv, &cmd->nc_mutex);
1384 1405
1385 1406 return;
1386 1407 }
1387 1408
1388 1409 qp = nvme->n_ioq[cmd->nc_sqid];
1389 1410
1390 1411 mutex_enter(&qp->nq_mutex);
1391 1412 (void) nvme_unqueue_cmd(nvme, qp, cmd->nc_sqe.sqe_cid);
1392 1413 mutex_exit(&qp->nq_mutex);
1393 1414
1394 1415 /*
1395 1416 * As we don't know what the presumed dead hardware might still do with
1396 1417 * the DMA memory, we'll put the command on the lost commands list if it
1397 1418 * has any DMA memory.
1398 1419 */
1399 1420 if (cmd->nc_dma != NULL) {
1400 1421 mutex_enter(&nvme_lc_mutex);
1401 1422 list_insert_head(&nvme_lost_cmds, cmd);
1402 1423 mutex_exit(&nvme_lc_mutex);
1403 1424 }
1404 1425 }
1405 1426
1406 1427 static void
1407 1428 nvme_wakeup_cmd(void *arg)
1408 1429 {
1409 1430 nvme_cmd_t *cmd = arg;
1410 1431
1411 1432 mutex_enter(&cmd->nc_mutex);
1412 1433 cmd->nc_completed = B_TRUE;
1413 1434 cv_signal(&cmd->nc_cv);
1414 1435 mutex_exit(&cmd->nc_mutex);
1415 1436 }
1416 1437
1417 1438 static void
1418 1439 nvme_async_event_task(void *arg)
1419 1440 {
1420 1441 nvme_cmd_t *cmd = arg;
1421 1442 nvme_t *nvme = cmd->nc_nvme;
1422 1443 nvme_error_log_entry_t *error_log = NULL;
1423 1444 nvme_health_log_t *health_log = NULL;
1424 1445 size_t logsize = 0;
1425 1446 nvme_async_event_t event;
1426 1447
1427 1448 /*
1428 1449 * Check for errors associated with the async request itself. The only
1429 1450 * command-specific error is "async event limit exceeded", which
1430 1451 * indicates a programming error in the driver and causes a panic in
1431 1452 * nvme_check_cmd_status().
1432 1453 *
1433 1454 * Other possible errors are various scenarios where the async request
1434 1455 * was aborted, or internal errors in the device. Internal errors are
1435 1456 * reported to FMA, the command aborts need no special handling here.
1436 1457 *
1437 1458 * And finally, at least qemu nvme does not support async events,
1438 1459 * and will return NVME_CQE_SC_GEN_INV_OPC | DNR. If so, we
1439 1460 * will avoid posting async events.
1440 1461 */
1441 1462
1442 1463 if (nvme_check_cmd_status(cmd) != 0) {
1443 1464 dev_err(cmd->nc_nvme->n_dip, CE_WARN,
1444 1465 "!async event request returned failure, sct = %x, "
1445 1466 "sc = %x, dnr = %d, m = %d", cmd->nc_cqe.cqe_sf.sf_sct,
1446 1467 cmd->nc_cqe.cqe_sf.sf_sc, cmd->nc_cqe.cqe_sf.sf_dnr,
1447 1468 cmd->nc_cqe.cqe_sf.sf_m);
1448 1469
1449 1470 if (cmd->nc_cqe.cqe_sf.sf_sct == NVME_CQE_SCT_GENERIC &&
1450 1471 cmd->nc_cqe.cqe_sf.sf_sc == NVME_CQE_SC_GEN_INTERNAL_ERR) {
1451 1472 cmd->nc_nvme->n_dead = B_TRUE;
1452 1473 ddi_fm_service_impact(cmd->nc_nvme->n_dip,
1453 1474 DDI_SERVICE_LOST);
1454 1475 }
1455 1476
1456 1477 if (cmd->nc_cqe.cqe_sf.sf_sct == NVME_CQE_SCT_GENERIC &&
1457 1478 cmd->nc_cqe.cqe_sf.sf_sc == NVME_CQE_SC_GEN_INV_OPC &&
1458 1479 cmd->nc_cqe.cqe_sf.sf_dnr == 1) {
1459 1480 nvme->n_async_event_supported = B_FALSE;
1460 1481 }
1461 1482
1462 1483 nvme_free_cmd(cmd);
1463 1484 return;
1464 1485 }
1465 1486
1466 1487
1467 1488 event.r = cmd->nc_cqe.cqe_dw0;
1468 1489
1469 1490 /* Clear CQE and re-submit the async request. */
1470 1491 bzero(&cmd->nc_cqe, sizeof (nvme_cqe_t));
1471 1492 nvme_submit_admin_cmd(nvme->n_adminq, cmd);
1472 1493
1473 1494 switch (event.b.ae_type) {
1474 1495 case NVME_ASYNC_TYPE_ERROR:
1475 1496 if (event.b.ae_logpage == NVME_LOGPAGE_ERROR) {
1476 1497 (void) nvme_get_logpage(nvme, (void **)&error_log,
1477 1498 &logsize, event.b.ae_logpage);
1478 1499 } else {
1479 1500 dev_err(nvme->n_dip, CE_WARN, "!wrong logpage in "
1480 1501 "async event reply: %d", event.b.ae_logpage);
1481 1502 atomic_inc_32(&nvme->n_wrong_logpage);
1482 1503 }
1483 1504
1484 1505 switch (event.b.ae_info) {
1485 1506 case NVME_ASYNC_ERROR_INV_SQ:
1486 1507 dev_err(nvme->n_dip, CE_PANIC, "programming error: "
1487 1508 "invalid submission queue");
1488 1509 return;
1489 1510
1490 1511 case NVME_ASYNC_ERROR_INV_DBL:
1491 1512 dev_err(nvme->n_dip, CE_PANIC, "programming error: "
1492 1513 "invalid doorbell write value");
1493 1514 return;
1494 1515
1495 1516 case NVME_ASYNC_ERROR_DIAGFAIL:
1496 1517 dev_err(nvme->n_dip, CE_WARN, "!diagnostic failure");
1497 1518 ddi_fm_service_impact(nvme->n_dip, DDI_SERVICE_LOST);
1498 1519 nvme->n_dead = B_TRUE;
1499 1520 atomic_inc_32(&nvme->n_diagfail_event);
1500 1521 break;
1501 1522
1502 1523 case NVME_ASYNC_ERROR_PERSISTENT:
1503 1524 dev_err(nvme->n_dip, CE_WARN, "!persistent internal "
1504 1525 "device error");
1505 1526 ddi_fm_service_impact(nvme->n_dip, DDI_SERVICE_LOST);
1506 1527 nvme->n_dead = B_TRUE;
1507 1528 atomic_inc_32(&nvme->n_persistent_event);
1508 1529 break;
1509 1530
1510 1531 case NVME_ASYNC_ERROR_TRANSIENT:
1511 1532 dev_err(nvme->n_dip, CE_WARN, "!transient internal "
1512 1533 "device error");
1513 1534 /* TODO: send ereport */
1514 1535 atomic_inc_32(&nvme->n_transient_event);
1515 1536 break;
1516 1537
1517 1538 case NVME_ASYNC_ERROR_FW_LOAD:
1518 1539 dev_err(nvme->n_dip, CE_WARN,
1519 1540 "!firmware image load error");
1520 1541 atomic_inc_32(&nvme->n_fw_load_event);
1521 1542 break;
1522 1543 }
1523 1544 break;
1524 1545
1525 1546 case NVME_ASYNC_TYPE_HEALTH:
1526 1547 if (event.b.ae_logpage == NVME_LOGPAGE_HEALTH) {
1527 1548 (void) nvme_get_logpage(nvme, (void **)&health_log,
1528 1549 &logsize, event.b.ae_logpage, -1);
1529 1550 } else {
1530 1551 dev_err(nvme->n_dip, CE_WARN, "!wrong logpage in "
1531 1552 "async event reply: %d", event.b.ae_logpage);
1532 1553 atomic_inc_32(&nvme->n_wrong_logpage);
1533 1554 }
1534 1555
1535 1556 switch (event.b.ae_info) {
1536 1557 case NVME_ASYNC_HEALTH_RELIABILITY:
1537 1558 dev_err(nvme->n_dip, CE_WARN,
1538 1559 "!device reliability compromised");
1539 1560 /* TODO: send ereport */
1540 1561 atomic_inc_32(&nvme->n_reliability_event);
1541 1562 break;
1542 1563
1543 1564 case NVME_ASYNC_HEALTH_TEMPERATURE:
1544 1565 dev_err(nvme->n_dip, CE_WARN,
1545 1566 "!temperature above threshold");
1546 1567 /* TODO: send ereport */
1547 1568 atomic_inc_32(&nvme->n_temperature_event);
1548 1569 break;
1549 1570
1550 1571 case NVME_ASYNC_HEALTH_SPARE:
1551 1572 dev_err(nvme->n_dip, CE_WARN,
1552 1573 "!spare space below threshold");
1553 1574 /* TODO: send ereport */
1554 1575 atomic_inc_32(&nvme->n_spare_event);
1555 1576 break;
1556 1577 }
1557 1578 break;
1558 1579
1559 1580 case NVME_ASYNC_TYPE_VENDOR:
1560 1581 dev_err(nvme->n_dip, CE_WARN, "!vendor specific async event "
1561 1582 "received, info = %x, logpage = %x", event.b.ae_info,
1562 1583 event.b.ae_logpage);
1563 1584 atomic_inc_32(&nvme->n_vendor_event);
1564 1585 break;
1565 1586
1566 1587 default:
1567 1588 dev_err(nvme->n_dip, CE_WARN, "!unknown async event received, "
1568 1589 "type = %x, info = %x, logpage = %x", event.b.ae_type,
1569 1590 event.b.ae_info, event.b.ae_logpage);
1570 1591 atomic_inc_32(&nvme->n_unknown_event);
1571 1592 break;
1572 1593 }
1573 1594
1574 1595 if (error_log)
1575 1596 kmem_free(error_log, logsize);
1576 1597
1577 1598 if (health_log)
1578 1599 kmem_free(health_log, logsize);
1579 1600 }
1580 1601
1581 1602 static void
1582 1603 nvme_admin_cmd(nvme_cmd_t *cmd, int sec)
1583 1604 {
1584 1605 mutex_enter(&cmd->nc_mutex);
1585 1606 nvme_submit_admin_cmd(cmd->nc_nvme->n_adminq, cmd);
1586 1607 nvme_wait_cmd(cmd, sec);
1587 1608 mutex_exit(&cmd->nc_mutex);
1588 1609 }
1589 1610
1590 1611 static void
1591 1612 nvme_async_event(nvme_t *nvme)
1592 1613 {
1593 1614 nvme_cmd_t *cmd;
1594 1615
1595 1616 cmd = nvme_alloc_cmd(nvme, KM_SLEEP);
1596 1617 cmd->nc_sqid = 0;
1597 1618 cmd->nc_sqe.sqe_opc = NVME_OPC_ASYNC_EVENT;
1598 1619 cmd->nc_callback = nvme_async_event_task;
1599 1620 cmd->nc_dontpanic = B_TRUE;
1600 1621
1601 1622 nvme_submit_admin_cmd(nvme->n_adminq, cmd);
1602 1623 }
1603 1624
1604 1625 static int
1605 1626 nvme_format_nvm(nvme_t *nvme, uint32_t nsid, uint8_t lbaf, boolean_t ms,
1606 1627 uint8_t pi, boolean_t pil, uint8_t ses)
1607 1628 {
1608 1629 nvme_cmd_t *cmd = nvme_alloc_cmd(nvme, KM_SLEEP);
1609 1630 nvme_format_nvm_t format_nvm = { 0 };
1610 1631 int ret;
1611 1632
1612 1633 format_nvm.b.fm_lbaf = lbaf & 0xf;
1613 1634 format_nvm.b.fm_ms = ms ? 1 : 0;
1614 1635 format_nvm.b.fm_pi = pi & 0x7;
1615 1636 format_nvm.b.fm_pil = pil ? 1 : 0;
1616 1637 format_nvm.b.fm_ses = ses & 0x7;
1617 1638
1618 1639 cmd->nc_sqid = 0;
1619 1640 cmd->nc_callback = nvme_wakeup_cmd;
1620 1641 cmd->nc_sqe.sqe_nsid = nsid;
1621 1642 cmd->nc_sqe.sqe_opc = NVME_OPC_NVM_FORMAT;
1622 1643 cmd->nc_sqe.sqe_cdw10 = format_nvm.r;
1623 1644
1624 1645 /*
1625 1646 * Some devices like Samsung SM951 don't allow formatting of all
1626 1647 * namespaces in one command. Handle that gracefully.
1627 1648 */
1628 1649 if (nsid == (uint32_t)-1)
1629 1650 cmd->nc_dontpanic = B_TRUE;
1630 1651
1631 1652 nvme_admin_cmd(cmd, nvme_format_cmd_timeout);
1632 1653
1633 1654 if ((ret = nvme_check_cmd_status(cmd)) != 0) {
1634 1655 dev_err(nvme->n_dip, CE_WARN,
1635 1656 "!FORMAT failed with sct = %x, sc = %x",
1636 1657 cmd->nc_cqe.cqe_sf.sf_sct, cmd->nc_cqe.cqe_sf.sf_sc);
1637 1658 }
1638 1659
1639 1660 nvme_free_cmd(cmd);
1640 1661 return (ret);
1641 1662 }
1642 1663
1643 1664 static int
1644 1665 nvme_get_logpage(nvme_t *nvme, void **buf, size_t *bufsize, uint8_t logpage,
1645 1666 ...)
1646 1667 {
1647 1668 nvme_cmd_t *cmd = nvme_alloc_cmd(nvme, KM_SLEEP);
1648 1669 nvme_getlogpage_t getlogpage = { 0 };
1649 1670 va_list ap;
1650 1671 int ret;
1651 1672
1652 1673 va_start(ap, logpage);
1653 1674
1654 1675 cmd->nc_sqid = 0;
1655 1676 cmd->nc_callback = nvme_wakeup_cmd;
1656 1677 cmd->nc_sqe.sqe_opc = NVME_OPC_GET_LOG_PAGE;
1657 1678
1658 1679 getlogpage.b.lp_lid = logpage;
1659 1680
1660 1681 switch (logpage) {
1661 1682 case NVME_LOGPAGE_ERROR:
1662 1683 cmd->nc_sqe.sqe_nsid = (uint32_t)-1;
1663 1684 /*
1664 1685 * The GET LOG PAGE command can use at most 2 pages to return
1665 1686 * data, PRP lists are not supported.
1666 1687 */
1667 1688 *bufsize = MIN(2 * nvme->n_pagesize,
1668 1689 nvme->n_error_log_len * sizeof (nvme_error_log_entry_t));
1669 1690 break;
1670 1691
1671 1692 case NVME_LOGPAGE_HEALTH:
1672 1693 cmd->nc_sqe.sqe_nsid = va_arg(ap, uint32_t);
1673 1694 *bufsize = sizeof (nvme_health_log_t);
1674 1695 break;
1675 1696
1676 1697 case NVME_LOGPAGE_FWSLOT:
1677 1698 cmd->nc_sqe.sqe_nsid = (uint32_t)-1;
1678 1699 *bufsize = sizeof (nvme_fwslot_log_t);
1679 1700 break;
1680 1701
1681 1702 default:
1682 1703 dev_err(nvme->n_dip, CE_WARN, "!unknown log page requested: %d",
1683 1704 logpage);
1684 1705 atomic_inc_32(&nvme->n_unknown_logpage);
1685 1706 ret = EINVAL;
1686 1707 goto fail;
1687 1708 }
1688 1709
1689 1710 va_end(ap);
1690 1711
1691 1712 getlogpage.b.lp_numd = *bufsize / sizeof (uint32_t) - 1;
1692 1713
1693 1714 cmd->nc_sqe.sqe_cdw10 = getlogpage.r;
1694 1715
1695 1716 if (nvme_zalloc_dma(nvme, getlogpage.b.lp_numd * sizeof (uint32_t),
1696 1717 DDI_DMA_READ, &nvme->n_prp_dma_attr, &cmd->nc_dma) != DDI_SUCCESS) {
1697 1718 dev_err(nvme->n_dip, CE_WARN,
1698 1719 "!nvme_zalloc_dma failed for GET LOG PAGE");
1699 1720 ret = ENOMEM;
1700 1721 goto fail;
1701 1722 }
1702 1723
1703 1724 if (cmd->nc_dma->nd_ncookie > 2) {
1704 1725 dev_err(nvme->n_dip, CE_WARN,
1705 1726 "!too many DMA cookies for GET LOG PAGE");
1706 1727 atomic_inc_32(&nvme->n_too_many_cookies);
1707 1728 ret = ENOMEM;
1708 1729 goto fail;
1709 1730 }
1710 1731
1711 1732 cmd->nc_sqe.sqe_dptr.d_prp[0] = cmd->nc_dma->nd_cookie.dmac_laddress;
1712 1733 if (cmd->nc_dma->nd_ncookie > 1) {
1713 1734 ddi_dma_nextcookie(cmd->nc_dma->nd_dmah,
1714 1735 &cmd->nc_dma->nd_cookie);
1715 1736 cmd->nc_sqe.sqe_dptr.d_prp[1] =
1716 1737 cmd->nc_dma->nd_cookie.dmac_laddress;
1717 1738 }
1718 1739
1719 1740 nvme_admin_cmd(cmd, nvme_admin_cmd_timeout);
1720 1741
1721 1742 if ((ret = nvme_check_cmd_status(cmd)) != 0) {
1722 1743 dev_err(nvme->n_dip, CE_WARN,
1723 1744 "!GET LOG PAGE failed with sct = %x, sc = %x",
1724 1745 cmd->nc_cqe.cqe_sf.sf_sct, cmd->nc_cqe.cqe_sf.sf_sc);
1725 1746 goto fail;
1726 1747 }
1727 1748
1728 1749 *buf = kmem_alloc(*bufsize, KM_SLEEP);
1729 1750 bcopy(cmd->nc_dma->nd_memp, *buf, *bufsize);
1730 1751
1731 1752 fail:
1732 1753 nvme_free_cmd(cmd);
1733 1754
1734 1755 return (ret);
1735 1756 }
1736 1757
1737 1758 static int
1738 1759 nvme_identify(nvme_t *nvme, uint32_t nsid, void **buf)
1739 1760 {
1740 1761 nvme_cmd_t *cmd = nvme_alloc_cmd(nvme, KM_SLEEP);
1741 1762 int ret;
1742 1763
1743 1764 if (buf == NULL)
1744 1765 return (EINVAL);
1745 1766
1746 1767 cmd->nc_sqid = 0;
1747 1768 cmd->nc_callback = nvme_wakeup_cmd;
1748 1769 cmd->nc_sqe.sqe_opc = NVME_OPC_IDENTIFY;
1749 1770 cmd->nc_sqe.sqe_nsid = nsid;
1750 1771 cmd->nc_sqe.sqe_cdw10 = nsid ? NVME_IDENTIFY_NSID : NVME_IDENTIFY_CTRL;
1751 1772
1752 1773 if (nvme_zalloc_dma(nvme, NVME_IDENTIFY_BUFSIZE, DDI_DMA_READ,
1753 1774 &nvme->n_prp_dma_attr, &cmd->nc_dma) != DDI_SUCCESS) {
1754 1775 dev_err(nvme->n_dip, CE_WARN,
1755 1776 "!nvme_zalloc_dma failed for IDENTIFY");
1756 1777 ret = ENOMEM;
1757 1778 goto fail;
1758 1779 }
1759 1780
1760 1781 if (cmd->nc_dma->nd_ncookie > 2) {
1761 1782 dev_err(nvme->n_dip, CE_WARN,
1762 1783 "!too many DMA cookies for IDENTIFY");
1763 1784 atomic_inc_32(&nvme->n_too_many_cookies);
1764 1785 ret = ENOMEM;
1765 1786 goto fail;
1766 1787 }
1767 1788
1768 1789 cmd->nc_sqe.sqe_dptr.d_prp[0] = cmd->nc_dma->nd_cookie.dmac_laddress;
1769 1790 if (cmd->nc_dma->nd_ncookie > 1) {
1770 1791 ddi_dma_nextcookie(cmd->nc_dma->nd_dmah,
1771 1792 &cmd->nc_dma->nd_cookie);
1772 1793 cmd->nc_sqe.sqe_dptr.d_prp[1] =
1773 1794 cmd->nc_dma->nd_cookie.dmac_laddress;
1774 1795 }
1775 1796
1776 1797 nvme_admin_cmd(cmd, nvme_admin_cmd_timeout);
1777 1798
1778 1799 if ((ret = nvme_check_cmd_status(cmd)) != 0) {
1779 1800 dev_err(nvme->n_dip, CE_WARN,
1780 1801 "!IDENTIFY failed with sct = %x, sc = %x",
1781 1802 cmd->nc_cqe.cqe_sf.sf_sct, cmd->nc_cqe.cqe_sf.sf_sc);
1782 1803 goto fail;
1783 1804 }
1784 1805
1785 1806 *buf = kmem_alloc(NVME_IDENTIFY_BUFSIZE, KM_SLEEP);
1786 1807 bcopy(cmd->nc_dma->nd_memp, *buf, NVME_IDENTIFY_BUFSIZE);
1787 1808
1788 1809 fail:
1789 1810 nvme_free_cmd(cmd);
1790 1811
1791 1812 return (ret);
1792 1813 }
1793 1814
1794 1815 static int
1795 1816 nvme_set_features(nvme_t *nvme, uint32_t nsid, uint8_t feature, uint32_t val,
1796 1817 uint32_t *res)
1797 1818 {
1798 1819 _NOTE(ARGUNUSED(nsid));
1799 1820 nvme_cmd_t *cmd = nvme_alloc_cmd(nvme, KM_SLEEP);
1800 1821 int ret = EINVAL;
1801 1822
1802 1823 ASSERT(res != NULL);
1803 1824
1804 1825 cmd->nc_sqid = 0;
1805 1826 cmd->nc_callback = nvme_wakeup_cmd;
1806 1827 cmd->nc_sqe.sqe_opc = NVME_OPC_SET_FEATURES;
1807 1828 cmd->nc_sqe.sqe_cdw10 = feature;
1808 1829 cmd->nc_sqe.sqe_cdw11 = val;
1809 1830
1810 1831 switch (feature) {
1811 1832 case NVME_FEAT_WRITE_CACHE:
1812 1833 if (!nvme->n_write_cache_present)
1813 1834 goto fail;
1814 1835 break;
1815 1836
1816 1837 case NVME_FEAT_NQUEUES:
1817 1838 break;
1818 1839
1819 1840 default:
1820 1841 goto fail;
1821 1842 }
1822 1843
1823 1844 nvme_admin_cmd(cmd, nvme_admin_cmd_timeout);
1824 1845
1825 1846 if ((ret = nvme_check_cmd_status(cmd)) != 0) {
1826 1847 dev_err(nvme->n_dip, CE_WARN,
1827 1848 "!SET FEATURES %d failed with sct = %x, sc = %x",
1828 1849 feature, cmd->nc_cqe.cqe_sf.sf_sct,
1829 1850 cmd->nc_cqe.cqe_sf.sf_sc);
1830 1851 goto fail;
1831 1852 }
1832 1853
1833 1854 *res = cmd->nc_cqe.cqe_dw0;
1834 1855
1835 1856 fail:
1836 1857 nvme_free_cmd(cmd);
1837 1858 return (ret);
1838 1859 }
1839 1860
1840 1861 static int
1841 1862 nvme_get_features(nvme_t *nvme, uint32_t nsid, uint8_t feature, uint32_t *res,
1842 1863 void **buf, size_t *bufsize)
1843 1864 {
1844 1865 nvme_cmd_t *cmd = nvme_alloc_cmd(nvme, KM_SLEEP);
1845 1866 int ret = EINVAL;
1846 1867
1847 1868 ASSERT(res != NULL);
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1848 1869
1849 1870 if (bufsize != NULL)
1850 1871 *bufsize = 0;
1851 1872
1852 1873 cmd->nc_sqid = 0;
1853 1874 cmd->nc_callback = nvme_wakeup_cmd;
1854 1875 cmd->nc_sqe.sqe_opc = NVME_OPC_GET_FEATURES;
1855 1876 cmd->nc_sqe.sqe_cdw10 = feature;
1856 1877 cmd->nc_sqe.sqe_cdw11 = *res;
1857 1878
1879 + /*
1880 + * For some of the optional features there doesn't seem to be a method
1881 + * of detecting whether it is supported other than using it. This will
1882 + * cause "Invalid Field in Command" error, which is normally considered
1883 + * a programming error. Set the nc_dontpanic flag to override the panic
1884 + * in nvme_check_generic_cmd_status().
1885 + */
1858 1886 switch (feature) {
1859 1887 case NVME_FEAT_ARBITRATION:
1860 1888 case NVME_FEAT_POWER_MGMT:
1861 1889 case NVME_FEAT_TEMPERATURE:
1862 - case NVME_FEAT_ERROR:
1863 1890 case NVME_FEAT_NQUEUES:
1864 1891 case NVME_FEAT_INTR_COAL:
1865 1892 case NVME_FEAT_INTR_VECT:
1866 1893 case NVME_FEAT_WRITE_ATOM:
1867 1894 case NVME_FEAT_ASYNC_EVENT:
1868 - case NVME_FEAT_PROGRESS:
1869 1895 break;
1870 1896
1897 + case NVME_FEAT_ERROR:
1898 + /*
1899 + * Per-namespace Deallocated or Unwritten Logical Block
1900 + * Error Enable (DULBE) feature was added after initial NVMe
1901 + * specification, but we currently only check this feature with
1902 + * NS ID of 0 (the controller itself), and some controllers get
1903 + * upset, reporting the error. For the moment, override the
1904 + * panic by setting the nc_dontpanic flag.
1905 + */
1906 + cmd->nc_dontpanic = B_TRUE;
1907 + break;
1908 +
1871 1909 case NVME_FEAT_WRITE_CACHE:
1872 1910 if (!nvme->n_write_cache_present)
1873 1911 goto fail;
1874 1912 break;
1875 1913
1876 1914 case NVME_FEAT_LBA_RANGE:
1877 1915 if (!nvme->n_lba_range_supported)
1878 1916 goto fail;
1879 1917
1880 - /*
1881 - * The LBA Range Type feature is optional. There doesn't seem
1882 - * be a method of detecting whether it is supported other than
1883 - * using it. This will cause a "invalid field in command" error,
1884 - * which is normally considered a programming error and causes
1885 - * panic in nvme_check_generic_cmd_status().
1886 - */
1887 1918 cmd->nc_dontpanic = B_TRUE;
1888 1919 cmd->nc_sqe.sqe_nsid = nsid;
1889 1920 ASSERT(bufsize != NULL);
1890 1921 *bufsize = NVME_LBA_RANGE_BUFSIZE;
1891 -
1892 1922 break;
1893 1923
1894 1924 case NVME_FEAT_AUTO_PST:
1895 1925 if (!nvme->n_auto_pst_supported)
1896 1926 goto fail;
1897 1927
1898 1928 ASSERT(bufsize != NULL);
1899 1929 *bufsize = NVME_AUTO_PST_BUFSIZE;
1900 1930 break;
1901 1931
1932 + case NVME_FEAT_PROGRESS:
1933 + if (!nvme->n_progress_supported)
1934 + goto fail;
1935 +
1936 + cmd->nc_dontpanic = B_TRUE;
1937 + break;
1938 +
1902 1939 default:
1903 1940 goto fail;
1904 1941 }
1905 1942
1906 1943 if (bufsize != NULL && *bufsize != 0) {
1907 1944 if (nvme_zalloc_dma(nvme, *bufsize, DDI_DMA_READ,
1908 1945 &nvme->n_prp_dma_attr, &cmd->nc_dma) != DDI_SUCCESS) {
1909 1946 dev_err(nvme->n_dip, CE_WARN,
1910 1947 "!nvme_zalloc_dma failed for GET FEATURES");
1911 1948 ret = ENOMEM;
1912 1949 goto fail;
1913 1950 }
1914 1951
1915 1952 if (cmd->nc_dma->nd_ncookie > 2) {
1916 1953 dev_err(nvme->n_dip, CE_WARN,
1917 1954 "!too many DMA cookies for GET FEATURES");
1918 1955 atomic_inc_32(&nvme->n_too_many_cookies);
1919 1956 ret = ENOMEM;
1920 1957 goto fail;
1921 1958 }
1922 1959
1923 1960 cmd->nc_sqe.sqe_dptr.d_prp[0] =
1924 1961 cmd->nc_dma->nd_cookie.dmac_laddress;
1925 1962 if (cmd->nc_dma->nd_ncookie > 1) {
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1926 1963 ddi_dma_nextcookie(cmd->nc_dma->nd_dmah,
1927 1964 &cmd->nc_dma->nd_cookie);
1928 1965 cmd->nc_sqe.sqe_dptr.d_prp[1] =
1929 1966 cmd->nc_dma->nd_cookie.dmac_laddress;
1930 1967 }
1931 1968 }
1932 1969
1933 1970 nvme_admin_cmd(cmd, nvme_admin_cmd_timeout);
1934 1971
1935 1972 if ((ret = nvme_check_cmd_status(cmd)) != 0) {
1936 - if (feature == NVME_FEAT_LBA_RANGE &&
1937 - cmd->nc_cqe.cqe_sf.sf_sct == NVME_CQE_SCT_GENERIC &&
1938 - cmd->nc_cqe.cqe_sf.sf_sc == NVME_CQE_SC_GEN_INV_FLD)
1939 - nvme->n_lba_range_supported = B_FALSE;
1940 - else
1973 + boolean_t known = B_TRUE;
1974 +
1975 + /* Check if this is unsupported optional feature */
1976 + if (cmd->nc_cqe.cqe_sf.sf_sct == NVME_CQE_SCT_GENERIC &&
1977 + cmd->nc_cqe.cqe_sf.sf_sc == NVME_CQE_SC_GEN_INV_FLD) {
1978 + switch (feature) {
1979 + case NVME_FEAT_LBA_RANGE:
1980 + nvme->n_lba_range_supported = B_FALSE;
1981 + break;
1982 + case NVME_FEAT_PROGRESS:
1983 + nvme->n_progress_supported = B_FALSE;
1984 + break;
1985 + default:
1986 + known = B_FALSE;
1987 + break;
1988 + }
1989 + } else {
1990 + known = B_FALSE;
1991 + }
1992 +
1993 + /* Report the error otherwise */
1994 + if (!known) {
1941 1995 dev_err(nvme->n_dip, CE_WARN,
1942 1996 "!GET FEATURES %d failed with sct = %x, sc = %x",
1943 1997 feature, cmd->nc_cqe.cqe_sf.sf_sct,
1944 1998 cmd->nc_cqe.cqe_sf.sf_sc);
1999 + }
2000 +
1945 2001 goto fail;
1946 2002 }
1947 2003
1948 2004 if (bufsize != NULL && *bufsize != 0) {
1949 2005 ASSERT(buf != NULL);
1950 2006 *buf = kmem_alloc(*bufsize, KM_SLEEP);
1951 2007 bcopy(cmd->nc_dma->nd_memp, *buf, *bufsize);
1952 2008 }
1953 2009
1954 2010 *res = cmd->nc_cqe.cqe_dw0;
1955 2011
1956 2012 fail:
1957 2013 nvme_free_cmd(cmd);
1958 2014 return (ret);
1959 2015 }
1960 2016
1961 2017 static int
1962 2018 nvme_write_cache_set(nvme_t *nvme, boolean_t enable)
1963 2019 {
1964 2020 nvme_write_cache_t nwc = { 0 };
1965 2021
1966 2022 if (enable)
1967 2023 nwc.b.wc_wce = 1;
1968 2024
1969 2025 return (nvme_set_features(nvme, 0, NVME_FEAT_WRITE_CACHE, nwc.r,
1970 2026 &nwc.r));
1971 2027 }
1972 2028
1973 2029 static int
1974 2030 nvme_set_nqueues(nvme_t *nvme, uint16_t *nqueues)
1975 2031 {
1976 2032 nvme_nqueues_t nq = { 0 };
1977 2033 int ret;
1978 2034
1979 2035 nq.b.nq_nsq = nq.b.nq_ncq = *nqueues - 1;
1980 2036
1981 2037 ret = nvme_set_features(nvme, 0, NVME_FEAT_NQUEUES, nq.r, &nq.r);
1982 2038
1983 2039 if (ret == 0) {
1984 2040 /*
1985 2041 * Always use the same number of submission and completion
1986 2042 * queues, and never use more than the requested number of
1987 2043 * queues.
1988 2044 */
1989 2045 *nqueues = MIN(*nqueues, MIN(nq.b.nq_nsq, nq.b.nq_ncq) + 1);
1990 2046 }
1991 2047
1992 2048 return (ret);
1993 2049 }
1994 2050
1995 2051 static int
1996 2052 nvme_create_io_qpair(nvme_t *nvme, nvme_qpair_t *qp, uint16_t idx)
1997 2053 {
1998 2054 nvme_cmd_t *cmd = nvme_alloc_cmd(nvme, KM_SLEEP);
1999 2055 nvme_create_queue_dw10_t dw10 = { 0 };
2000 2056 nvme_create_cq_dw11_t c_dw11 = { 0 };
2001 2057 nvme_create_sq_dw11_t s_dw11 = { 0 };
2002 2058 int ret;
2003 2059
2004 2060 dw10.b.q_qid = idx;
2005 2061 dw10.b.q_qsize = qp->nq_nentry - 1;
2006 2062
2007 2063 c_dw11.b.cq_pc = 1;
2008 2064 c_dw11.b.cq_ien = 1;
2009 2065 c_dw11.b.cq_iv = idx % nvme->n_intr_cnt;
2010 2066
2011 2067 cmd->nc_sqid = 0;
2012 2068 cmd->nc_callback = nvme_wakeup_cmd;
2013 2069 cmd->nc_sqe.sqe_opc = NVME_OPC_CREATE_CQUEUE;
2014 2070 cmd->nc_sqe.sqe_cdw10 = dw10.r;
2015 2071 cmd->nc_sqe.sqe_cdw11 = c_dw11.r;
2016 2072 cmd->nc_sqe.sqe_dptr.d_prp[0] = qp->nq_cqdma->nd_cookie.dmac_laddress;
2017 2073
2018 2074 nvme_admin_cmd(cmd, nvme_admin_cmd_timeout);
2019 2075
2020 2076 if ((ret = nvme_check_cmd_status(cmd)) != 0) {
2021 2077 dev_err(nvme->n_dip, CE_WARN,
2022 2078 "!CREATE CQUEUE failed with sct = %x, sc = %x",
2023 2079 cmd->nc_cqe.cqe_sf.sf_sct, cmd->nc_cqe.cqe_sf.sf_sc);
2024 2080 goto fail;
2025 2081 }
2026 2082
2027 2083 nvme_free_cmd(cmd);
2028 2084
2029 2085 s_dw11.b.sq_pc = 1;
2030 2086 s_dw11.b.sq_cqid = idx;
2031 2087
2032 2088 cmd = nvme_alloc_cmd(nvme, KM_SLEEP);
2033 2089 cmd->nc_sqid = 0;
2034 2090 cmd->nc_callback = nvme_wakeup_cmd;
2035 2091 cmd->nc_sqe.sqe_opc = NVME_OPC_CREATE_SQUEUE;
2036 2092 cmd->nc_sqe.sqe_cdw10 = dw10.r;
2037 2093 cmd->nc_sqe.sqe_cdw11 = s_dw11.r;
2038 2094 cmd->nc_sqe.sqe_dptr.d_prp[0] = qp->nq_sqdma->nd_cookie.dmac_laddress;
2039 2095
2040 2096 nvme_admin_cmd(cmd, nvme_admin_cmd_timeout);
2041 2097
2042 2098 if ((ret = nvme_check_cmd_status(cmd)) != 0) {
2043 2099 dev_err(nvme->n_dip, CE_WARN,
2044 2100 "!CREATE SQUEUE failed with sct = %x, sc = %x",
2045 2101 cmd->nc_cqe.cqe_sf.sf_sct, cmd->nc_cqe.cqe_sf.sf_sc);
2046 2102 goto fail;
2047 2103 }
2048 2104
2049 2105 fail:
2050 2106 nvme_free_cmd(cmd);
2051 2107
2052 2108 return (ret);
2053 2109 }
2054 2110
2055 2111 static boolean_t
2056 2112 nvme_reset(nvme_t *nvme, boolean_t quiesce)
2057 2113 {
2058 2114 nvme_reg_csts_t csts;
2059 2115 int i;
2060 2116
2061 2117 nvme_put32(nvme, NVME_REG_CC, 0);
2062 2118
2063 2119 csts.r = nvme_get32(nvme, NVME_REG_CSTS);
2064 2120 if (csts.b.csts_rdy == 1) {
2065 2121 nvme_put32(nvme, NVME_REG_CC, 0);
2066 2122 for (i = 0; i != nvme->n_timeout * 10; i++) {
2067 2123 csts.r = nvme_get32(nvme, NVME_REG_CSTS);
2068 2124 if (csts.b.csts_rdy == 0)
2069 2125 break;
2070 2126
2071 2127 if (quiesce)
2072 2128 drv_usecwait(50000);
2073 2129 else
2074 2130 delay(drv_usectohz(50000));
2075 2131 }
2076 2132 }
2077 2133
2078 2134 nvme_put32(nvme, NVME_REG_AQA, 0);
2079 2135 nvme_put32(nvme, NVME_REG_ASQ, 0);
2080 2136 nvme_put32(nvme, NVME_REG_ACQ, 0);
2081 2137
2082 2138 csts.r = nvme_get32(nvme, NVME_REG_CSTS);
2083 2139 return (csts.b.csts_rdy == 0 ? B_TRUE : B_FALSE);
2084 2140 }
2085 2141
2086 2142 static void
2087 2143 nvme_shutdown(nvme_t *nvme, int mode, boolean_t quiesce)
2088 2144 {
2089 2145 nvme_reg_cc_t cc;
2090 2146 nvme_reg_csts_t csts;
2091 2147 int i;
2092 2148
2093 2149 ASSERT(mode == NVME_CC_SHN_NORMAL || mode == NVME_CC_SHN_ABRUPT);
2094 2150
2095 2151 cc.r = nvme_get32(nvme, NVME_REG_CC);
2096 2152 cc.b.cc_shn = mode & 0x3;
2097 2153 nvme_put32(nvme, NVME_REG_CC, cc.r);
2098 2154
2099 2155 for (i = 0; i != 10; i++) {
2100 2156 csts.r = nvme_get32(nvme, NVME_REG_CSTS);
2101 2157 if (csts.b.csts_shst == NVME_CSTS_SHN_COMPLETE)
2102 2158 break;
2103 2159
2104 2160 if (quiesce)
2105 2161 drv_usecwait(100000);
2106 2162 else
2107 2163 delay(drv_usectohz(100000));
2108 2164 }
2109 2165 }
2110 2166
2111 2167
2112 2168 static void
2113 2169 nvme_prepare_devid(nvme_t *nvme, uint32_t nsid)
2114 2170 {
2115 2171 /*
2116 2172 * Section 7.7 of the spec describes how to get a unique ID for
2117 2173 * the controller: the vendor ID, the model name and the serial
2118 2174 * number shall be unique when combined.
2119 2175 *
2120 2176 * If a namespace has no EUI64 we use the above and add the hex
2121 2177 * namespace ID to get a unique ID for the namespace.
2122 2178 */
2123 2179 char model[sizeof (nvme->n_idctl->id_model) + 1];
2124 2180 char serial[sizeof (nvme->n_idctl->id_serial) + 1];
2125 2181
2126 2182 bcopy(nvme->n_idctl->id_model, model, sizeof (nvme->n_idctl->id_model));
2127 2183 bcopy(nvme->n_idctl->id_serial, serial,
2128 2184 sizeof (nvme->n_idctl->id_serial));
2129 2185
2130 2186 model[sizeof (nvme->n_idctl->id_model)] = '\0';
2131 2187 serial[sizeof (nvme->n_idctl->id_serial)] = '\0';
2132 2188
2133 2189 nvme->n_ns[nsid - 1].ns_devid = kmem_asprintf("%4X-%s-%s-%X",
2134 2190 nvme->n_idctl->id_vid, model, serial, nsid);
2135 2191 }
2136 2192
2137 2193 static int
2138 2194 nvme_init_ns(nvme_t *nvme, int nsid)
2139 2195 {
2140 2196 nvme_namespace_t *ns = &nvme->n_ns[nsid - 1];
2141 2197 nvme_identify_nsid_t *idns;
2142 2198 int last_rp;
2143 2199
2144 2200 ns->ns_nvme = nvme;
2145 2201
2146 2202 if (nvme_identify(nvme, nsid, (void **)&idns) != 0) {
2147 2203 dev_err(nvme->n_dip, CE_WARN,
2148 2204 "!failed to identify namespace %d", nsid);
2149 2205 return (DDI_FAILURE);
2150 2206 }
2151 2207
2152 2208 ns->ns_idns = idns;
2153 2209 ns->ns_id = nsid;
2154 2210 ns->ns_block_count = idns->id_nsize;
2155 2211 ns->ns_block_size =
2156 2212 1 << idns->id_lbaf[idns->id_flbas.lba_format].lbaf_lbads;
2157 2213 ns->ns_best_block_size = ns->ns_block_size;
2158 2214
2159 2215 /*
2160 2216 * Get the EUI64 if present. Use it for devid and device node names.
2161 2217 */
2162 2218 if (NVME_VERSION_ATLEAST(&nvme->n_version, 1, 1))
2163 2219 bcopy(idns->id_eui64, ns->ns_eui64, sizeof (ns->ns_eui64));
2164 2220
2165 2221 /*LINTED: E_BAD_PTR_CAST_ALIGN*/
2166 2222 if (*(uint64_t *)ns->ns_eui64 != 0) {
2167 2223 uint8_t *eui64 = ns->ns_eui64;
2168 2224
2169 2225 (void) snprintf(ns->ns_name, sizeof (ns->ns_name),
2170 2226 "%02x%02x%02x%02x%02x%02x%02x%02x",
2171 2227 eui64[0], eui64[1], eui64[2], eui64[3],
2172 2228 eui64[4], eui64[5], eui64[6], eui64[7]);
2173 2229 } else {
2174 2230 (void) snprintf(ns->ns_name, sizeof (ns->ns_name), "%d",
2175 2231 ns->ns_id);
2176 2232
2177 2233 nvme_prepare_devid(nvme, ns->ns_id);
2178 2234 }
2179 2235
2180 2236 /*
2181 2237 * Find the LBA format with no metadata and the best relative
2182 2238 * performance. A value of 3 means "degraded", 0 is best.
2183 2239 */
2184 2240 last_rp = 3;
2185 2241 for (int j = 0; j <= idns->id_nlbaf; j++) {
2186 2242 if (idns->id_lbaf[j].lbaf_lbads == 0)
2187 2243 break;
2188 2244 if (idns->id_lbaf[j].lbaf_ms != 0)
2189 2245 continue;
2190 2246 if (idns->id_lbaf[j].lbaf_rp >= last_rp)
2191 2247 continue;
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2192 2248 last_rp = idns->id_lbaf[j].lbaf_rp;
2193 2249 ns->ns_best_block_size =
2194 2250 1 << idns->id_lbaf[j].lbaf_lbads;
2195 2251 }
2196 2252
2197 2253 if (ns->ns_best_block_size < nvme->n_min_block_size)
2198 2254 ns->ns_best_block_size = nvme->n_min_block_size;
2199 2255
2200 2256 /*
2201 2257 * We currently don't support namespaces that use either:
2202 - * - thin provisioning
2203 2258 * - protection information
2204 2259 * - illegal block size (< 512)
2205 2260 */
2206 - if (idns->id_nsfeat.f_thin ||
2207 - idns->id_dps.dp_pinfo) {
2261 + if (idns->id_dps.dp_pinfo) {
2208 2262 dev_err(nvme->n_dip, CE_WARN,
2209 - "!ignoring namespace %d, unsupported features: "
2210 - "thin = %d, pinfo = %d", nsid,
2211 - idns->id_nsfeat.f_thin, idns->id_dps.dp_pinfo);
2263 + "!ignoring namespace %d, unsupported feature: "
2264 + "pinfo = %d", nsid, idns->id_dps.dp_pinfo);
2212 2265 ns->ns_ignore = B_TRUE;
2213 2266 } else if (ns->ns_block_size < 512) {
2214 2267 dev_err(nvme->n_dip, CE_WARN,
2215 2268 "!ignoring namespace %d, unsupported block size %"PRIu64,
2216 2269 nsid, (uint64_t)ns->ns_block_size);
2217 2270 ns->ns_ignore = B_TRUE;
2218 2271 } else {
2219 2272 ns->ns_ignore = B_FALSE;
2220 2273 }
2221 2274
2222 2275 return (DDI_SUCCESS);
2223 2276 }
2224 2277
2225 2278 static int
2226 2279 nvme_init(nvme_t *nvme)
2227 2280 {
2228 2281 nvme_reg_cc_t cc = { 0 };
2229 2282 nvme_reg_aqa_t aqa = { 0 };
2230 2283 nvme_reg_asq_t asq = { 0 };
2231 2284 nvme_reg_acq_t acq = { 0 };
2232 2285 nvme_reg_cap_t cap;
2233 2286 nvme_reg_vs_t vs;
2234 2287 nvme_reg_csts_t csts;
2235 2288 int i = 0;
2236 2289 uint16_t nqueues;
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2237 2290 char model[sizeof (nvme->n_idctl->id_model) + 1];
2238 2291 char *vendor, *product;
2239 2292
2240 2293 /* Check controller version */
2241 2294 vs.r = nvme_get32(nvme, NVME_REG_VS);
2242 2295 nvme->n_version.v_major = vs.b.vs_mjr;
2243 2296 nvme->n_version.v_minor = vs.b.vs_mnr;
2244 2297 dev_err(nvme->n_dip, CE_CONT, "?NVMe spec version %d.%d",
2245 2298 nvme->n_version.v_major, nvme->n_version.v_minor);
2246 2299
2247 - if (NVME_VERSION_HIGHER(&nvme->n_version,
2248 - nvme_version_major, nvme_version_minor)) {
2249 - dev_err(nvme->n_dip, CE_WARN, "!no support for version > %d.%d",
2250 - nvme_version_major, nvme_version_minor);
2300 + if (nvme->n_version.v_major > nvme_version_major) {
2301 + dev_err(nvme->n_dip, CE_WARN, "!no support for version > %d.x",
2302 + nvme_version_major);
2251 2303 if (nvme->n_strict_version)
2252 2304 goto fail;
2253 2305 }
2254 2306
2255 2307 /* retrieve controller configuration */
2256 2308 cap.r = nvme_get64(nvme, NVME_REG_CAP);
2257 2309
2258 2310 if ((cap.b.cap_css & NVME_CAP_CSS_NVM) == 0) {
2259 2311 dev_err(nvme->n_dip, CE_WARN,
2260 2312 "!NVM command set not supported by hardware");
2261 2313 goto fail;
2262 2314 }
2263 2315
2264 2316 nvme->n_nssr_supported = cap.b.cap_nssrs;
2265 2317 nvme->n_doorbell_stride = 4 << cap.b.cap_dstrd;
2266 2318 nvme->n_timeout = cap.b.cap_to;
2267 2319 nvme->n_arbitration_mechanisms = cap.b.cap_ams;
2268 2320 nvme->n_cont_queues_reqd = cap.b.cap_cqr;
2269 2321 nvme->n_max_queue_entries = cap.b.cap_mqes + 1;
2270 2322
2271 2323 /*
2272 2324 * The MPSMIN and MPSMAX fields in the CAP register use 0 to specify
2273 2325 * the base page size of 4k (1<<12), so add 12 here to get the real
2274 2326 * page size value.
2275 2327 */
2276 2328 nvme->n_pageshift = MIN(MAX(cap.b.cap_mpsmin + 12, PAGESHIFT),
2277 2329 cap.b.cap_mpsmax + 12);
2278 2330 nvme->n_pagesize = 1UL << (nvme->n_pageshift);
2279 2331
2280 2332 /*
2281 2333 * Set up Queue DMA to transfer at least 1 page-aligned page at a time.
2282 2334 */
2283 2335 nvme->n_queue_dma_attr.dma_attr_align = nvme->n_pagesize;
2284 2336 nvme->n_queue_dma_attr.dma_attr_minxfer = nvme->n_pagesize;
2285 2337
2286 2338 /*
2287 2339 * Set up PRP DMA to transfer 1 page-aligned page at a time.
2288 2340 * Maxxfer may be increased after we identified the controller limits.
2289 2341 */
2290 2342 nvme->n_prp_dma_attr.dma_attr_maxxfer = nvme->n_pagesize;
2291 2343 nvme->n_prp_dma_attr.dma_attr_minxfer = nvme->n_pagesize;
2292 2344 nvme->n_prp_dma_attr.dma_attr_align = nvme->n_pagesize;
2293 2345 nvme->n_prp_dma_attr.dma_attr_seg = nvme->n_pagesize - 1;
2294 2346
2295 2347 /*
2296 2348 * Reset controller if it's still in ready state.
2297 2349 */
2298 2350 if (nvme_reset(nvme, B_FALSE) == B_FALSE) {
2299 2351 dev_err(nvme->n_dip, CE_WARN, "!unable to reset controller");
2300 2352 ddi_fm_service_impact(nvme->n_dip, DDI_SERVICE_LOST);
2301 2353 nvme->n_dead = B_TRUE;
2302 2354 goto fail;
2303 2355 }
2304 2356
2305 2357 /*
2306 2358 * Create the admin queue pair.
2307 2359 */
2308 2360 if (nvme_alloc_qpair(nvme, nvme->n_admin_queue_len, &nvme->n_adminq, 0)
2309 2361 != DDI_SUCCESS) {
2310 2362 dev_err(nvme->n_dip, CE_WARN,
2311 2363 "!unable to allocate admin qpair");
2312 2364 goto fail;
2313 2365 }
2314 2366 nvme->n_ioq = kmem_alloc(sizeof (nvme_qpair_t *), KM_SLEEP);
2315 2367 nvme->n_ioq[0] = nvme->n_adminq;
2316 2368
2317 2369 nvme->n_progress |= NVME_ADMIN_QUEUE;
2318 2370
2319 2371 (void) ddi_prop_update_int(DDI_DEV_T_NONE, nvme->n_dip,
2320 2372 "admin-queue-len", nvme->n_admin_queue_len);
2321 2373
2322 2374 aqa.b.aqa_asqs = aqa.b.aqa_acqs = nvme->n_admin_queue_len - 1;
2323 2375 asq = nvme->n_adminq->nq_sqdma->nd_cookie.dmac_laddress;
2324 2376 acq = nvme->n_adminq->nq_cqdma->nd_cookie.dmac_laddress;
2325 2377
2326 2378 ASSERT((asq & (nvme->n_pagesize - 1)) == 0);
2327 2379 ASSERT((acq & (nvme->n_pagesize - 1)) == 0);
2328 2380
2329 2381 nvme_put32(nvme, NVME_REG_AQA, aqa.r);
2330 2382 nvme_put64(nvme, NVME_REG_ASQ, asq);
2331 2383 nvme_put64(nvme, NVME_REG_ACQ, acq);
2332 2384
2333 2385 cc.b.cc_ams = 0; /* use Round-Robin arbitration */
2334 2386 cc.b.cc_css = 0; /* use NVM command set */
2335 2387 cc.b.cc_mps = nvme->n_pageshift - 12;
2336 2388 cc.b.cc_shn = 0; /* no shutdown in progress */
2337 2389 cc.b.cc_en = 1; /* enable controller */
2338 2390 cc.b.cc_iosqes = 6; /* submission queue entry is 2^6 bytes long */
2339 2391 cc.b.cc_iocqes = 4; /* completion queue entry is 2^4 bytes long */
2340 2392
2341 2393 nvme_put32(nvme, NVME_REG_CC, cc.r);
2342 2394
2343 2395 /*
2344 2396 * Wait for the controller to become ready.
2345 2397 */
2346 2398 csts.r = nvme_get32(nvme, NVME_REG_CSTS);
2347 2399 if (csts.b.csts_rdy == 0) {
2348 2400 for (i = 0; i != nvme->n_timeout * 10; i++) {
2349 2401 delay(drv_usectohz(50000));
2350 2402 csts.r = nvme_get32(nvme, NVME_REG_CSTS);
2351 2403
2352 2404 if (csts.b.csts_cfs == 1) {
2353 2405 dev_err(nvme->n_dip, CE_WARN,
2354 2406 "!controller fatal status at init");
2355 2407 ddi_fm_service_impact(nvme->n_dip,
2356 2408 DDI_SERVICE_LOST);
2357 2409 nvme->n_dead = B_TRUE;
2358 2410 goto fail;
2359 2411 }
2360 2412
2361 2413 if (csts.b.csts_rdy == 1)
2362 2414 break;
2363 2415 }
2364 2416 }
2365 2417
2366 2418 if (csts.b.csts_rdy == 0) {
2367 2419 dev_err(nvme->n_dip, CE_WARN, "!controller not ready");
2368 2420 ddi_fm_service_impact(nvme->n_dip, DDI_SERVICE_LOST);
2369 2421 nvme->n_dead = B_TRUE;
2370 2422 goto fail;
2371 2423 }
2372 2424
2373 2425 /*
2374 2426 * Assume an abort command limit of 1. We'll destroy and re-init
2375 2427 * that later when we know the true abort command limit.
2376 2428 */
2377 2429 sema_init(&nvme->n_abort_sema, 1, NULL, SEMA_DRIVER, NULL);
2378 2430
2379 2431 /*
2380 2432 * Setup initial interrupt for admin queue.
2381 2433 */
2382 2434 if ((nvme_setup_interrupts(nvme, DDI_INTR_TYPE_MSIX, 1)
2383 2435 != DDI_SUCCESS) &&
2384 2436 (nvme_setup_interrupts(nvme, DDI_INTR_TYPE_MSI, 1)
2385 2437 != DDI_SUCCESS) &&
2386 2438 (nvme_setup_interrupts(nvme, DDI_INTR_TYPE_FIXED, 1)
2387 2439 != DDI_SUCCESS)) {
2388 2440 dev_err(nvme->n_dip, CE_WARN,
2389 2441 "!failed to setup initial interrupt");
2390 2442 goto fail;
2391 2443 }
2392 2444
2393 2445 /*
2394 2446 * Post an asynchronous event command to catch errors.
2395 2447 * We assume the asynchronous events are supported as required by
2396 2448 * specification (Figure 40 in section 5 of NVMe 1.2).
2397 2449 * However, since at least qemu does not follow the specification,
2398 2450 * we need a mechanism to protect ourselves.
2399 2451 */
2400 2452 nvme->n_async_event_supported = B_TRUE;
2401 2453 nvme_async_event(nvme);
2402 2454
2403 2455 /*
2404 2456 * Identify Controller
2405 2457 */
2406 2458 if (nvme_identify(nvme, 0, (void **)&nvme->n_idctl) != 0) {
2407 2459 dev_err(nvme->n_dip, CE_WARN,
2408 2460 "!failed to identify controller");
2409 2461 goto fail;
2410 2462 }
2411 2463
2412 2464 /*
2413 2465 * Get Vendor & Product ID
2414 2466 */
2415 2467 bcopy(nvme->n_idctl->id_model, model, sizeof (nvme->n_idctl->id_model));
2416 2468 model[sizeof (nvme->n_idctl->id_model)] = '\0';
2417 2469 sata_split_model(model, &vendor, &product);
2418 2470
2419 2471 if (vendor == NULL)
2420 2472 nvme->n_vendor = strdup("NVMe");
2421 2473 else
2422 2474 nvme->n_vendor = strdup(vendor);
2423 2475
2424 2476 nvme->n_product = strdup(product);
2425 2477
2426 2478 /*
2427 2479 * Get controller limits.
2428 2480 */
2429 2481 nvme->n_async_event_limit = MAX(NVME_MIN_ASYNC_EVENT_LIMIT,
2430 2482 MIN(nvme->n_admin_queue_len / 10,
2431 2483 MIN(nvme->n_idctl->id_aerl + 1, nvme->n_async_event_limit)));
2432 2484
2433 2485 (void) ddi_prop_update_int(DDI_DEV_T_NONE, nvme->n_dip,
2434 2486 "async-event-limit", nvme->n_async_event_limit);
2435 2487
2436 2488 nvme->n_abort_command_limit = nvme->n_idctl->id_acl + 1;
2437 2489
2438 2490 /*
2439 2491 * Reinitialize the semaphore with the true abort command limit
2440 2492 * supported by the hardware. It's not necessary to disable interrupts
2441 2493 * as only command aborts use the semaphore, and no commands are
2442 2494 * executed or aborted while we're here.
2443 2495 */
2444 2496 sema_destroy(&nvme->n_abort_sema);
2445 2497 sema_init(&nvme->n_abort_sema, nvme->n_abort_command_limit - 1, NULL,
2446 2498 SEMA_DRIVER, NULL);
2447 2499
2448 2500 nvme->n_progress |= NVME_CTRL_LIMITS;
2449 2501
2450 2502 if (nvme->n_idctl->id_mdts == 0)
2451 2503 nvme->n_max_data_transfer_size = nvme->n_pagesize * 65536;
2452 2504 else
2453 2505 nvme->n_max_data_transfer_size =
2454 2506 1ull << (nvme->n_pageshift + nvme->n_idctl->id_mdts);
2455 2507
2456 2508 nvme->n_error_log_len = nvme->n_idctl->id_elpe + 1;
2457 2509
2458 2510 /*
2459 2511 * Limit n_max_data_transfer_size to what we can handle in one PRP.
2460 2512 * Chained PRPs are currently unsupported.
2461 2513 *
2462 2514 * This is a no-op on hardware which doesn't support a transfer size
2463 2515 * big enough to require chained PRPs.
2464 2516 */
2465 2517 nvme->n_max_data_transfer_size = MIN(nvme->n_max_data_transfer_size,
2466 2518 (nvme->n_pagesize / sizeof (uint64_t) * nvme->n_pagesize));
2467 2519
2468 2520 nvme->n_prp_dma_attr.dma_attr_maxxfer = nvme->n_max_data_transfer_size;
2469 2521
2470 2522 /*
2471 2523 * Make sure the minimum/maximum queue entry sizes are not
2472 2524 * larger/smaller than the default.
2473 2525 */
2474 2526
2475 2527 if (((1 << nvme->n_idctl->id_sqes.qes_min) > sizeof (nvme_sqe_t)) ||
2476 2528 ((1 << nvme->n_idctl->id_sqes.qes_max) < sizeof (nvme_sqe_t)) ||
2477 2529 ((1 << nvme->n_idctl->id_cqes.qes_min) > sizeof (nvme_cqe_t)) ||
2478 2530 ((1 << nvme->n_idctl->id_cqes.qes_max) < sizeof (nvme_cqe_t)))
2479 2531 goto fail;
2480 2532
2481 2533 /*
2482 2534 * Check for the presence of a Volatile Write Cache. If present,
2483 2535 * enable or disable based on the value of the property
2484 2536 * volatile-write-cache-enable (default is enabled).
2485 2537 */
2486 2538 nvme->n_write_cache_present =
2487 2539 nvme->n_idctl->id_vwc.vwc_present == 0 ? B_FALSE : B_TRUE;
2488 2540
2489 2541 (void) ddi_prop_update_int(DDI_DEV_T_NONE, nvme->n_dip,
2490 2542 "volatile-write-cache-present",
2491 2543 nvme->n_write_cache_present ? 1 : 0);
2492 2544
2493 2545 if (!nvme->n_write_cache_present) {
2494 2546 nvme->n_write_cache_enabled = B_FALSE;
2495 2547 } else if (nvme_write_cache_set(nvme, nvme->n_write_cache_enabled)
2496 2548 != 0) {
2497 2549 dev_err(nvme->n_dip, CE_WARN,
2498 2550 "!failed to %sable volatile write cache",
2499 2551 nvme->n_write_cache_enabled ? "en" : "dis");
2500 2552 /*
2501 2553 * Assume the cache is (still) enabled.
2502 2554 */
2503 2555 nvme->n_write_cache_enabled = B_TRUE;
2504 2556 }
2505 2557
2506 2558 (void) ddi_prop_update_int(DDI_DEV_T_NONE, nvme->n_dip,
2507 2559 "volatile-write-cache-enable",
2508 2560 nvme->n_write_cache_enabled ? 1 : 0);
2509 2561
2510 2562 /*
2511 2563 * Assume LBA Range Type feature is supported. If it isn't this
2512 2564 * will be set to B_FALSE by nvme_get_features().
2513 2565 */
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2514 2566 nvme->n_lba_range_supported = B_TRUE;
2515 2567
2516 2568 /*
2517 2569 * Check support for Autonomous Power State Transition.
2518 2570 */
2519 2571 if (NVME_VERSION_ATLEAST(&nvme->n_version, 1, 1))
2520 2572 nvme->n_auto_pst_supported =
2521 2573 nvme->n_idctl->id_apsta.ap_sup == 0 ? B_FALSE : B_TRUE;
2522 2574
2523 2575 /*
2576 + * Assume Software Progress Marker feature is supported. If it isn't
2577 + * this will be set to B_FALSE by nvme_get_features().
2578 + */
2579 + nvme->n_progress_supported = B_TRUE;
2580 +
2581 + /*
2524 2582 * Identify Namespaces
2525 2583 */
2526 2584 nvme->n_namespace_count = nvme->n_idctl->id_nn;
2585 +
2586 + if (nvme->n_namespace_count == 0) {
2587 + dev_err(nvme->n_dip, CE_WARN,
2588 + "!controllers without namespaces are not supported");
2589 + goto fail;
2590 + }
2591 +
2527 2592 if (nvme->n_namespace_count > NVME_MINOR_MAX) {
2528 2593 dev_err(nvme->n_dip, CE_WARN,
2529 2594 "!too many namespaces: %d, limiting to %d\n",
2530 2595 nvme->n_namespace_count, NVME_MINOR_MAX);
2531 2596 nvme->n_namespace_count = NVME_MINOR_MAX;
2532 2597 }
2533 2598
2534 2599 nvme->n_ns = kmem_zalloc(sizeof (nvme_namespace_t) *
2535 2600 nvme->n_namespace_count, KM_SLEEP);
2536 2601
2537 2602 for (i = 0; i != nvme->n_namespace_count; i++) {
2538 2603 mutex_init(&nvme->n_ns[i].ns_minor.nm_mutex, NULL, MUTEX_DRIVER,
2539 2604 NULL);
2540 2605 if (nvme_init_ns(nvme, i + 1) != DDI_SUCCESS)
2541 2606 goto fail;
2542 2607 }
2543 2608
2544 2609 /*
2545 2610 * Try to set up MSI/MSI-X interrupts.
2546 2611 */
2547 2612 if ((nvme->n_intr_types & (DDI_INTR_TYPE_MSI | DDI_INTR_TYPE_MSIX))
2548 2613 != 0) {
2549 2614 nvme_release_interrupts(nvme);
2550 2615
2551 2616 nqueues = MIN(UINT16_MAX, ncpus);
2552 2617
2553 2618 if ((nvme_setup_interrupts(nvme, DDI_INTR_TYPE_MSIX,
2554 2619 nqueues) != DDI_SUCCESS) &&
2555 2620 (nvme_setup_interrupts(nvme, DDI_INTR_TYPE_MSI,
2556 2621 nqueues) != DDI_SUCCESS)) {
2557 2622 dev_err(nvme->n_dip, CE_WARN,
2558 2623 "!failed to setup MSI/MSI-X interrupts");
2559 2624 goto fail;
2560 2625 }
2561 2626 }
2562 2627
2563 2628 nqueues = nvme->n_intr_cnt;
2564 2629
2565 2630 /*
2566 2631 * Create I/O queue pairs.
2567 2632 */
2568 2633
2569 2634 if (nvme_set_nqueues(nvme, &nqueues) != 0) {
2570 2635 dev_err(nvme->n_dip, CE_WARN,
2571 2636 "!failed to set number of I/O queues to %d",
2572 2637 nvme->n_intr_cnt);
2573 2638 goto fail;
2574 2639 }
2575 2640
2576 2641 /*
2577 2642 * Reallocate I/O queue array
2578 2643 */
2579 2644 kmem_free(nvme->n_ioq, sizeof (nvme_qpair_t *));
2580 2645 nvme->n_ioq = kmem_zalloc(sizeof (nvme_qpair_t *) *
2581 2646 (nqueues + 1), KM_SLEEP);
2582 2647 nvme->n_ioq[0] = nvme->n_adminq;
2583 2648
2584 2649 nvme->n_ioq_count = nqueues;
2585 2650
2586 2651 /*
2587 2652 * If we got less queues than we asked for we might as well give
2588 2653 * some of the interrupt vectors back to the system.
2589 2654 */
2590 2655 if (nvme->n_ioq_count < nvme->n_intr_cnt) {
2591 2656 nvme_release_interrupts(nvme);
2592 2657
2593 2658 if (nvme_setup_interrupts(nvme, nvme->n_intr_type,
2594 2659 nvme->n_ioq_count) != DDI_SUCCESS) {
2595 2660 dev_err(nvme->n_dip, CE_WARN,
2596 2661 "!failed to reduce number of interrupts");
2597 2662 goto fail;
2598 2663 }
2599 2664 }
2600 2665
2601 2666 /*
2602 2667 * Alloc & register I/O queue pairs
2603 2668 */
2604 2669 nvme->n_io_queue_len =
2605 2670 MIN(nvme->n_io_queue_len, nvme->n_max_queue_entries);
2606 2671 (void) ddi_prop_update_int(DDI_DEV_T_NONE, nvme->n_dip, "io-queue-len",
2607 2672 nvme->n_io_queue_len);
2608 2673
2609 2674 for (i = 1; i != nvme->n_ioq_count + 1; i++) {
2610 2675 if (nvme_alloc_qpair(nvme, nvme->n_io_queue_len,
2611 2676 &nvme->n_ioq[i], i) != DDI_SUCCESS) {
2612 2677 dev_err(nvme->n_dip, CE_WARN,
2613 2678 "!unable to allocate I/O qpair %d", i);
2614 2679 goto fail;
2615 2680 }
2616 2681
2617 2682 if (nvme_create_io_qpair(nvme, nvme->n_ioq[i], i) != 0) {
2618 2683 dev_err(nvme->n_dip, CE_WARN,
2619 2684 "!unable to create I/O qpair %d", i);
2620 2685 goto fail;
2621 2686 }
2622 2687 }
2623 2688
2624 2689 /*
2625 2690 * Post more asynchronous events commands to reduce event reporting
2626 2691 * latency as suggested by the spec.
2627 2692 */
2628 2693 if (nvme->n_async_event_supported) {
2629 2694 for (i = 1; i != nvme->n_async_event_limit; i++)
2630 2695 nvme_async_event(nvme);
2631 2696 }
2632 2697
2633 2698 return (DDI_SUCCESS);
2634 2699
2635 2700 fail:
2636 2701 (void) nvme_reset(nvme, B_FALSE);
2637 2702 return (DDI_FAILURE);
2638 2703 }
2639 2704
2640 2705 static uint_t
2641 2706 nvme_intr(caddr_t arg1, caddr_t arg2)
2642 2707 {
2643 2708 /*LINTED: E_PTR_BAD_CAST_ALIGN*/
2644 2709 nvme_t *nvme = (nvme_t *)arg1;
2645 2710 int inum = (int)(uintptr_t)arg2;
2646 2711 int ccnt = 0;
2647 2712 int qnum;
2648 2713 nvme_cmd_t *cmd;
2649 2714
2650 2715 if (inum >= nvme->n_intr_cnt)
2651 2716 return (DDI_INTR_UNCLAIMED);
2652 2717
2653 2718 if (nvme->n_dead)
2654 2719 return (nvme->n_intr_type == DDI_INTR_TYPE_FIXED ?
2655 2720 DDI_INTR_UNCLAIMED : DDI_INTR_CLAIMED);
2656 2721
2657 2722 /*
2658 2723 * The interrupt vector a queue uses is calculated as queue_idx %
2659 2724 * intr_cnt in nvme_create_io_qpair(). Iterate through the queue array
2660 2725 * in steps of n_intr_cnt to process all queues using this vector.
2661 2726 */
2662 2727 for (qnum = inum;
2663 2728 qnum < nvme->n_ioq_count + 1 && nvme->n_ioq[qnum] != NULL;
2664 2729 qnum += nvme->n_intr_cnt) {
2665 2730 while ((cmd = nvme_retrieve_cmd(nvme, nvme->n_ioq[qnum]))) {
2666 2731 taskq_dispatch_ent((taskq_t *)cmd->nc_nvme->n_cmd_taskq,
2667 2732 cmd->nc_callback, cmd, TQ_NOSLEEP, &cmd->nc_tqent);
2668 2733 ccnt++;
2669 2734 }
2670 2735 }
2671 2736
2672 2737 return (ccnt > 0 ? DDI_INTR_CLAIMED : DDI_INTR_UNCLAIMED);
2673 2738 }
2674 2739
2675 2740 static void
2676 2741 nvme_release_interrupts(nvme_t *nvme)
2677 2742 {
2678 2743 int i;
2679 2744
2680 2745 for (i = 0; i < nvme->n_intr_cnt; i++) {
2681 2746 if (nvme->n_inth[i] == NULL)
2682 2747 break;
2683 2748
2684 2749 if (nvme->n_intr_cap & DDI_INTR_FLAG_BLOCK)
2685 2750 (void) ddi_intr_block_disable(&nvme->n_inth[i], 1);
2686 2751 else
2687 2752 (void) ddi_intr_disable(nvme->n_inth[i]);
2688 2753
2689 2754 (void) ddi_intr_remove_handler(nvme->n_inth[i]);
2690 2755 (void) ddi_intr_free(nvme->n_inth[i]);
2691 2756 }
2692 2757
2693 2758 kmem_free(nvme->n_inth, nvme->n_inth_sz);
2694 2759 nvme->n_inth = NULL;
2695 2760 nvme->n_inth_sz = 0;
2696 2761
2697 2762 nvme->n_progress &= ~NVME_INTERRUPTS;
2698 2763 }
2699 2764
2700 2765 static int
2701 2766 nvme_setup_interrupts(nvme_t *nvme, int intr_type, int nqpairs)
2702 2767 {
2703 2768 int nintrs, navail, count;
2704 2769 int ret;
2705 2770 int i;
2706 2771
2707 2772 if (nvme->n_intr_types == 0) {
2708 2773 ret = ddi_intr_get_supported_types(nvme->n_dip,
2709 2774 &nvme->n_intr_types);
2710 2775 if (ret != DDI_SUCCESS) {
2711 2776 dev_err(nvme->n_dip, CE_WARN,
2712 2777 "!%s: ddi_intr_get_supported types failed",
2713 2778 __func__);
2714 2779 return (ret);
2715 2780 }
2716 2781 #ifdef __x86
2717 2782 if (get_hwenv() == HW_VMWARE)
2718 2783 nvme->n_intr_types &= ~DDI_INTR_TYPE_MSIX;
2719 2784 #endif
2720 2785 }
2721 2786
2722 2787 if ((nvme->n_intr_types & intr_type) == 0)
2723 2788 return (DDI_FAILURE);
2724 2789
2725 2790 ret = ddi_intr_get_nintrs(nvme->n_dip, intr_type, &nintrs);
2726 2791 if (ret != DDI_SUCCESS) {
2727 2792 dev_err(nvme->n_dip, CE_WARN, "!%s: ddi_intr_get_nintrs failed",
2728 2793 __func__);
2729 2794 return (ret);
2730 2795 }
2731 2796
2732 2797 ret = ddi_intr_get_navail(nvme->n_dip, intr_type, &navail);
2733 2798 if (ret != DDI_SUCCESS) {
2734 2799 dev_err(nvme->n_dip, CE_WARN, "!%s: ddi_intr_get_navail failed",
2735 2800 __func__);
2736 2801 return (ret);
2737 2802 }
2738 2803
2739 2804 /* We want at most one interrupt per queue pair. */
2740 2805 if (navail > nqpairs)
2741 2806 navail = nqpairs;
2742 2807
2743 2808 nvme->n_inth_sz = sizeof (ddi_intr_handle_t) * navail;
2744 2809 nvme->n_inth = kmem_zalloc(nvme->n_inth_sz, KM_SLEEP);
2745 2810
2746 2811 ret = ddi_intr_alloc(nvme->n_dip, nvme->n_inth, intr_type, 0, navail,
2747 2812 &count, 0);
2748 2813 if (ret != DDI_SUCCESS) {
2749 2814 dev_err(nvme->n_dip, CE_WARN, "!%s: ddi_intr_alloc failed",
2750 2815 __func__);
2751 2816 goto fail;
2752 2817 }
2753 2818
2754 2819 nvme->n_intr_cnt = count;
2755 2820
2756 2821 ret = ddi_intr_get_pri(nvme->n_inth[0], &nvme->n_intr_pri);
2757 2822 if (ret != DDI_SUCCESS) {
2758 2823 dev_err(nvme->n_dip, CE_WARN, "!%s: ddi_intr_get_pri failed",
2759 2824 __func__);
2760 2825 goto fail;
2761 2826 }
2762 2827
2763 2828 for (i = 0; i < count; i++) {
2764 2829 ret = ddi_intr_add_handler(nvme->n_inth[i], nvme_intr,
2765 2830 (void *)nvme, (void *)(uintptr_t)i);
2766 2831 if (ret != DDI_SUCCESS) {
2767 2832 dev_err(nvme->n_dip, CE_WARN,
2768 2833 "!%s: ddi_intr_add_handler failed", __func__);
2769 2834 goto fail;
2770 2835 }
2771 2836 }
2772 2837
2773 2838 (void) ddi_intr_get_cap(nvme->n_inth[0], &nvme->n_intr_cap);
2774 2839
2775 2840 for (i = 0; i < count; i++) {
2776 2841 if (nvme->n_intr_cap & DDI_INTR_FLAG_BLOCK)
2777 2842 ret = ddi_intr_block_enable(&nvme->n_inth[i], 1);
2778 2843 else
2779 2844 ret = ddi_intr_enable(nvme->n_inth[i]);
2780 2845
2781 2846 if (ret != DDI_SUCCESS) {
2782 2847 dev_err(nvme->n_dip, CE_WARN,
2783 2848 "!%s: enabling interrupt %d failed", __func__, i);
2784 2849 goto fail;
2785 2850 }
2786 2851 }
2787 2852
2788 2853 nvme->n_intr_type = intr_type;
2789 2854
2790 2855 nvme->n_progress |= NVME_INTERRUPTS;
2791 2856
2792 2857 return (DDI_SUCCESS);
2793 2858
2794 2859 fail:
2795 2860 nvme_release_interrupts(nvme);
2796 2861
2797 2862 return (ret);
2798 2863 }
2799 2864
2800 2865 static int
2801 2866 nvme_fm_errcb(dev_info_t *dip, ddi_fm_error_t *fm_error, const void *arg)
2802 2867 {
2803 2868 _NOTE(ARGUNUSED(arg));
2804 2869
2805 2870 pci_ereport_post(dip, fm_error, NULL);
2806 2871 return (fm_error->fme_status);
2807 2872 }
2808 2873
2809 2874 static int
2810 2875 nvme_attach(dev_info_t *dip, ddi_attach_cmd_t cmd)
2811 2876 {
2812 2877 nvme_t *nvme;
2813 2878 int instance;
2814 2879 int nregs;
2815 2880 off_t regsize;
2816 2881 int i;
2817 2882 char name[32];
2818 2883
2819 2884 if (cmd != DDI_ATTACH)
2820 2885 return (DDI_FAILURE);
2821 2886
2822 2887 instance = ddi_get_instance(dip);
2823 2888
2824 2889 if (ddi_soft_state_zalloc(nvme_state, instance) != DDI_SUCCESS)
2825 2890 return (DDI_FAILURE);
2826 2891
2827 2892 nvme = ddi_get_soft_state(nvme_state, instance);
2828 2893 ddi_set_driver_private(dip, nvme);
2829 2894 nvme->n_dip = dip;
2830 2895
2831 2896 mutex_init(&nvme->n_minor.nm_mutex, NULL, MUTEX_DRIVER, NULL);
2832 2897
2833 2898 nvme->n_strict_version = ddi_prop_get_int(DDI_DEV_T_ANY, dip,
2834 2899 DDI_PROP_DONTPASS, "strict-version", 1) == 1 ? B_TRUE : B_FALSE;
2835 2900 nvme->n_ignore_unknown_vendor_status = ddi_prop_get_int(DDI_DEV_T_ANY,
2836 2901 dip, DDI_PROP_DONTPASS, "ignore-unknown-vendor-status", 0) == 1 ?
2837 2902 B_TRUE : B_FALSE;
2838 2903 nvme->n_admin_queue_len = ddi_prop_get_int(DDI_DEV_T_ANY, dip,
2839 2904 DDI_PROP_DONTPASS, "admin-queue-len", NVME_DEFAULT_ADMIN_QUEUE_LEN);
2840 2905 nvme->n_io_queue_len = ddi_prop_get_int(DDI_DEV_T_ANY, dip,
2841 2906 DDI_PROP_DONTPASS, "io-queue-len", NVME_DEFAULT_IO_QUEUE_LEN);
2842 2907 nvme->n_async_event_limit = ddi_prop_get_int(DDI_DEV_T_ANY, dip,
2843 2908 DDI_PROP_DONTPASS, "async-event-limit",
2844 2909 NVME_DEFAULT_ASYNC_EVENT_LIMIT);
2845 2910 nvme->n_write_cache_enabled = ddi_prop_get_int(DDI_DEV_T_ANY, dip,
2846 2911 DDI_PROP_DONTPASS, "volatile-write-cache-enable", 1) != 0 ?
2847 2912 B_TRUE : B_FALSE;
2848 2913 nvme->n_min_block_size = ddi_prop_get_int(DDI_DEV_T_ANY, dip,
2849 2914 DDI_PROP_DONTPASS, "min-phys-block-size",
2850 2915 NVME_DEFAULT_MIN_BLOCK_SIZE);
2851 2916
2852 2917 if (!ISP2(nvme->n_min_block_size) ||
2853 2918 (nvme->n_min_block_size < NVME_DEFAULT_MIN_BLOCK_SIZE)) {
2854 2919 dev_err(dip, CE_WARN, "!min-phys-block-size %s, "
2855 2920 "using default %d", ISP2(nvme->n_min_block_size) ?
2856 2921 "too low" : "not a power of 2",
2857 2922 NVME_DEFAULT_MIN_BLOCK_SIZE);
2858 2923 nvme->n_min_block_size = NVME_DEFAULT_MIN_BLOCK_SIZE;
2859 2924 }
2860 2925
2861 2926 if (nvme->n_admin_queue_len < NVME_MIN_ADMIN_QUEUE_LEN)
2862 2927 nvme->n_admin_queue_len = NVME_MIN_ADMIN_QUEUE_LEN;
2863 2928 else if (nvme->n_admin_queue_len > NVME_MAX_ADMIN_QUEUE_LEN)
2864 2929 nvme->n_admin_queue_len = NVME_MAX_ADMIN_QUEUE_LEN;
2865 2930
2866 2931 if (nvme->n_io_queue_len < NVME_MIN_IO_QUEUE_LEN)
2867 2932 nvme->n_io_queue_len = NVME_MIN_IO_QUEUE_LEN;
2868 2933
2869 2934 if (nvme->n_async_event_limit < 1)
2870 2935 nvme->n_async_event_limit = NVME_DEFAULT_ASYNC_EVENT_LIMIT;
2871 2936
2872 2937 nvme->n_reg_acc_attr = nvme_reg_acc_attr;
2873 2938 nvme->n_queue_dma_attr = nvme_queue_dma_attr;
2874 2939 nvme->n_prp_dma_attr = nvme_prp_dma_attr;
2875 2940 nvme->n_sgl_dma_attr = nvme_sgl_dma_attr;
2876 2941
2877 2942 /*
2878 2943 * Setup FMA support.
2879 2944 */
2880 2945 nvme->n_fm_cap = ddi_getprop(DDI_DEV_T_ANY, dip,
2881 2946 DDI_PROP_CANSLEEP | DDI_PROP_DONTPASS, "fm-capable",
2882 2947 DDI_FM_EREPORT_CAPABLE | DDI_FM_ACCCHK_CAPABLE |
2883 2948 DDI_FM_DMACHK_CAPABLE | DDI_FM_ERRCB_CAPABLE);
2884 2949
2885 2950 ddi_fm_init(dip, &nvme->n_fm_cap, &nvme->n_fm_ibc);
2886 2951
2887 2952 if (nvme->n_fm_cap) {
2888 2953 if (nvme->n_fm_cap & DDI_FM_ACCCHK_CAPABLE)
2889 2954 nvme->n_reg_acc_attr.devacc_attr_access =
2890 2955 DDI_FLAGERR_ACC;
2891 2956
2892 2957 if (nvme->n_fm_cap & DDI_FM_DMACHK_CAPABLE) {
2893 2958 nvme->n_prp_dma_attr.dma_attr_flags |= DDI_DMA_FLAGERR;
2894 2959 nvme->n_sgl_dma_attr.dma_attr_flags |= DDI_DMA_FLAGERR;
2895 2960 }
2896 2961
2897 2962 if (DDI_FM_EREPORT_CAP(nvme->n_fm_cap) ||
2898 2963 DDI_FM_ERRCB_CAP(nvme->n_fm_cap))
2899 2964 pci_ereport_setup(dip);
2900 2965
2901 2966 if (DDI_FM_ERRCB_CAP(nvme->n_fm_cap))
2902 2967 ddi_fm_handler_register(dip, nvme_fm_errcb,
2903 2968 (void *)nvme);
2904 2969 }
2905 2970
2906 2971 nvme->n_progress |= NVME_FMA_INIT;
2907 2972
2908 2973 /*
2909 2974 * The spec defines several register sets. Only the controller
2910 2975 * registers (set 1) are currently used.
2911 2976 */
2912 2977 if (ddi_dev_nregs(dip, &nregs) == DDI_FAILURE ||
2913 2978 nregs < 2 ||
2914 2979 ddi_dev_regsize(dip, 1, ®size) == DDI_FAILURE)
2915 2980 goto fail;
2916 2981
2917 2982 if (ddi_regs_map_setup(dip, 1, &nvme->n_regs, 0, regsize,
2918 2983 &nvme->n_reg_acc_attr, &nvme->n_regh) != DDI_SUCCESS) {
2919 2984 dev_err(dip, CE_WARN, "!failed to map regset 1");
2920 2985 goto fail;
2921 2986 }
2922 2987
2923 2988 nvme->n_progress |= NVME_REGS_MAPPED;
2924 2989
2925 2990 /*
2926 2991 * Create taskq for command completion.
2927 2992 */
2928 2993 (void) snprintf(name, sizeof (name), "%s%d_cmd_taskq",
2929 2994 ddi_driver_name(dip), ddi_get_instance(dip));
2930 2995 nvme->n_cmd_taskq = ddi_taskq_create(dip, name, MIN(UINT16_MAX, ncpus),
2931 2996 TASKQ_DEFAULTPRI, 0);
2932 2997 if (nvme->n_cmd_taskq == NULL) {
2933 2998 dev_err(dip, CE_WARN, "!failed to create cmd taskq");
2934 2999 goto fail;
2935 3000 }
2936 3001
2937 3002 /*
2938 3003 * Create PRP DMA cache
2939 3004 */
2940 3005 (void) snprintf(name, sizeof (name), "%s%d_prp_cache",
2941 3006 ddi_driver_name(dip), ddi_get_instance(dip));
2942 3007 nvme->n_prp_cache = kmem_cache_create(name, sizeof (nvme_dma_t),
2943 3008 0, nvme_prp_dma_constructor, nvme_prp_dma_destructor,
2944 3009 NULL, (void *)nvme, NULL, 0);
2945 3010
2946 3011 if (nvme_init(nvme) != DDI_SUCCESS)
2947 3012 goto fail;
2948 3013
2949 3014 /*
2950 3015 * Attach the blkdev driver for each namespace.
2951 3016 */
2952 3017 for (i = 0; i != nvme->n_namespace_count; i++) {
2953 3018 if (ddi_create_minor_node(nvme->n_dip, nvme->n_ns[i].ns_name,
2954 3019 S_IFCHR, NVME_MINOR(ddi_get_instance(nvme->n_dip), i + 1),
2955 3020 DDI_NT_NVME_ATTACHMENT_POINT, 0) != DDI_SUCCESS) {
2956 3021 dev_err(dip, CE_WARN,
2957 3022 "!failed to create minor node for namespace %d", i);
2958 3023 goto fail;
2959 3024 }
2960 3025
2961 3026 if (nvme->n_ns[i].ns_ignore)
2962 3027 continue;
2963 3028
2964 3029 nvme->n_ns[i].ns_bd_hdl = bd_alloc_handle(&nvme->n_ns[i],
2965 3030 &nvme_bd_ops, &nvme->n_prp_dma_attr, KM_SLEEP);
2966 3031
2967 3032 if (nvme->n_ns[i].ns_bd_hdl == NULL) {
2968 3033 dev_err(dip, CE_WARN,
2969 3034 "!failed to get blkdev handle for namespace %d", i);
2970 3035 goto fail;
2971 3036 }
2972 3037
2973 3038 if (bd_attach_handle(dip, nvme->n_ns[i].ns_bd_hdl)
2974 3039 != DDI_SUCCESS) {
2975 3040 dev_err(dip, CE_WARN,
2976 3041 "!failed to attach blkdev handle for namespace %d",
2977 3042 i);
2978 3043 goto fail;
2979 3044 }
2980 3045 }
2981 3046
2982 3047 if (ddi_create_minor_node(dip, "devctl", S_IFCHR,
2983 3048 NVME_MINOR(ddi_get_instance(dip), 0), DDI_NT_NVME_NEXUS, 0)
2984 3049 != DDI_SUCCESS) {
2985 3050 dev_err(dip, CE_WARN, "nvme_attach: "
2986 3051 "cannot create devctl minor node");
2987 3052 goto fail;
2988 3053 }
2989 3054
2990 3055 return (DDI_SUCCESS);
2991 3056
2992 3057 fail:
2993 3058 /* attach successful anyway so that FMA can retire the device */
2994 3059 if (nvme->n_dead)
2995 3060 return (DDI_SUCCESS);
2996 3061
2997 3062 (void) nvme_detach(dip, DDI_DETACH);
2998 3063
2999 3064 return (DDI_FAILURE);
3000 3065 }
3001 3066
3002 3067 static int
3003 3068 nvme_detach(dev_info_t *dip, ddi_detach_cmd_t cmd)
3004 3069 {
3005 3070 int instance, i;
3006 3071 nvme_t *nvme;
3007 3072
3008 3073 if (cmd != DDI_DETACH)
3009 3074 return (DDI_FAILURE);
3010 3075
3011 3076 instance = ddi_get_instance(dip);
3012 3077
3013 3078 nvme = ddi_get_soft_state(nvme_state, instance);
3014 3079
3015 3080 if (nvme == NULL)
3016 3081 return (DDI_FAILURE);
3017 3082
3018 3083 ddi_remove_minor_node(dip, "devctl");
3019 3084 mutex_destroy(&nvme->n_minor.nm_mutex);
3020 3085
3021 3086 if (nvme->n_ns) {
3022 3087 for (i = 0; i != nvme->n_namespace_count; i++) {
3023 3088 ddi_remove_minor_node(dip, nvme->n_ns[i].ns_name);
3024 3089 mutex_destroy(&nvme->n_ns[i].ns_minor.nm_mutex);
3025 3090
3026 3091 if (nvme->n_ns[i].ns_bd_hdl) {
3027 3092 (void) bd_detach_handle(
3028 3093 nvme->n_ns[i].ns_bd_hdl);
3029 3094 bd_free_handle(nvme->n_ns[i].ns_bd_hdl);
3030 3095 }
3031 3096
3032 3097 if (nvme->n_ns[i].ns_idns)
3033 3098 kmem_free(nvme->n_ns[i].ns_idns,
3034 3099 sizeof (nvme_identify_nsid_t));
3035 3100 if (nvme->n_ns[i].ns_devid)
3036 3101 strfree(nvme->n_ns[i].ns_devid);
3037 3102 }
3038 3103
3039 3104 kmem_free(nvme->n_ns, sizeof (nvme_namespace_t) *
3040 3105 nvme->n_namespace_count);
3041 3106 }
3042 3107
3043 3108 if (nvme->n_progress & NVME_INTERRUPTS)
3044 3109 nvme_release_interrupts(nvme);
3045 3110
3046 3111 if (nvme->n_cmd_taskq)
3047 3112 ddi_taskq_wait(nvme->n_cmd_taskq);
3048 3113
3049 3114 if (nvme->n_ioq_count > 0) {
3050 3115 for (i = 1; i != nvme->n_ioq_count + 1; i++) {
3051 3116 if (nvme->n_ioq[i] != NULL) {
3052 3117 /* TODO: send destroy queue commands */
3053 3118 nvme_free_qpair(nvme->n_ioq[i]);
3054 3119 }
3055 3120 }
3056 3121
3057 3122 kmem_free(nvme->n_ioq, sizeof (nvme_qpair_t *) *
3058 3123 (nvme->n_ioq_count + 1));
3059 3124 }
3060 3125
3061 3126 if (nvme->n_prp_cache != NULL) {
3062 3127 kmem_cache_destroy(nvme->n_prp_cache);
3063 3128 }
3064 3129
3065 3130 if (nvme->n_progress & NVME_REGS_MAPPED) {
3066 3131 nvme_shutdown(nvme, NVME_CC_SHN_NORMAL, B_FALSE);
3067 3132 (void) nvme_reset(nvme, B_FALSE);
3068 3133 }
3069 3134
3070 3135 if (nvme->n_cmd_taskq)
3071 3136 ddi_taskq_destroy(nvme->n_cmd_taskq);
3072 3137
3073 3138 if (nvme->n_progress & NVME_CTRL_LIMITS)
3074 3139 sema_destroy(&nvme->n_abort_sema);
3075 3140
3076 3141 if (nvme->n_progress & NVME_ADMIN_QUEUE)
3077 3142 nvme_free_qpair(nvme->n_adminq);
3078 3143
3079 3144 if (nvme->n_idctl)
3080 3145 kmem_free(nvme->n_idctl, NVME_IDENTIFY_BUFSIZE);
3081 3146
3082 3147 if (nvme->n_progress & NVME_REGS_MAPPED)
3083 3148 ddi_regs_map_free(&nvme->n_regh);
3084 3149
3085 3150 if (nvme->n_progress & NVME_FMA_INIT) {
3086 3151 if (DDI_FM_ERRCB_CAP(nvme->n_fm_cap))
3087 3152 ddi_fm_handler_unregister(nvme->n_dip);
3088 3153
3089 3154 if (DDI_FM_EREPORT_CAP(nvme->n_fm_cap) ||
3090 3155 DDI_FM_ERRCB_CAP(nvme->n_fm_cap))
3091 3156 pci_ereport_teardown(nvme->n_dip);
3092 3157
3093 3158 ddi_fm_fini(nvme->n_dip);
3094 3159 }
3095 3160
3096 3161 if (nvme->n_vendor != NULL)
3097 3162 strfree(nvme->n_vendor);
3098 3163
3099 3164 if (nvme->n_product != NULL)
3100 3165 strfree(nvme->n_product);
3101 3166
3102 3167 ddi_soft_state_free(nvme_state, instance);
3103 3168
3104 3169 return (DDI_SUCCESS);
3105 3170 }
3106 3171
3107 3172 static int
3108 3173 nvme_quiesce(dev_info_t *dip)
3109 3174 {
3110 3175 int instance;
3111 3176 nvme_t *nvme;
3112 3177
3113 3178 instance = ddi_get_instance(dip);
3114 3179
3115 3180 nvme = ddi_get_soft_state(nvme_state, instance);
3116 3181
3117 3182 if (nvme == NULL)
3118 3183 return (DDI_FAILURE);
3119 3184
3120 3185 nvme_shutdown(nvme, NVME_CC_SHN_ABRUPT, B_TRUE);
3121 3186
3122 3187 (void) nvme_reset(nvme, B_TRUE);
3123 3188
3124 3189 return (DDI_FAILURE);
3125 3190 }
3126 3191
3127 3192 static int
3128 3193 nvme_fill_prp(nvme_cmd_t *cmd, bd_xfer_t *xfer)
3129 3194 {
3130 3195 nvme_t *nvme = cmd->nc_nvme;
3131 3196 int nprp_page, nprp;
3132 3197 uint64_t *prp;
3133 3198
3134 3199 if (xfer->x_ndmac == 0)
3135 3200 return (DDI_FAILURE);
3136 3201
3137 3202 cmd->nc_sqe.sqe_dptr.d_prp[0] = xfer->x_dmac.dmac_laddress;
3138 3203 ddi_dma_nextcookie(xfer->x_dmah, &xfer->x_dmac);
3139 3204
3140 3205 if (xfer->x_ndmac == 1) {
3141 3206 cmd->nc_sqe.sqe_dptr.d_prp[1] = 0;
3142 3207 return (DDI_SUCCESS);
3143 3208 } else if (xfer->x_ndmac == 2) {
3144 3209 cmd->nc_sqe.sqe_dptr.d_prp[1] = xfer->x_dmac.dmac_laddress;
3145 3210 return (DDI_SUCCESS);
3146 3211 }
3147 3212
3148 3213 xfer->x_ndmac--;
3149 3214
3150 3215 nprp_page = nvme->n_pagesize / sizeof (uint64_t) - 1;
3151 3216 ASSERT(nprp_page > 0);
3152 3217 nprp = (xfer->x_ndmac + nprp_page - 1) / nprp_page;
3153 3218
3154 3219 /*
3155 3220 * We currently don't support chained PRPs and set up our DMA
3156 3221 * attributes to reflect that. If we still get an I/O request
3157 3222 * that needs a chained PRP something is very wrong.
3158 3223 */
3159 3224 VERIFY(nprp == 1);
3160 3225
3161 3226 cmd->nc_dma = kmem_cache_alloc(nvme->n_prp_cache, KM_SLEEP);
3162 3227 bzero(cmd->nc_dma->nd_memp, cmd->nc_dma->nd_len);
3163 3228
3164 3229 cmd->nc_sqe.sqe_dptr.d_prp[1] = cmd->nc_dma->nd_cookie.dmac_laddress;
3165 3230
3166 3231 /*LINTED: E_PTR_BAD_CAST_ALIGN*/
3167 3232 for (prp = (uint64_t *)cmd->nc_dma->nd_memp;
3168 3233 xfer->x_ndmac > 0;
3169 3234 prp++, xfer->x_ndmac--) {
3170 3235 *prp = xfer->x_dmac.dmac_laddress;
3171 3236 ddi_dma_nextcookie(xfer->x_dmah, &xfer->x_dmac);
3172 3237 }
3173 3238
3174 3239 (void) ddi_dma_sync(cmd->nc_dma->nd_dmah, 0, cmd->nc_dma->nd_len,
3175 3240 DDI_DMA_SYNC_FORDEV);
3176 3241 return (DDI_SUCCESS);
3177 3242 }
3178 3243
3179 3244 static nvme_cmd_t *
3180 3245 nvme_create_nvm_cmd(nvme_namespace_t *ns, uint8_t opc, bd_xfer_t *xfer)
3181 3246 {
3182 3247 nvme_t *nvme = ns->ns_nvme;
3183 3248 nvme_cmd_t *cmd;
3184 3249
3185 3250 /*
3186 3251 * Blkdev only sets BD_XFER_POLL when dumping, so don't sleep.
3187 3252 */
3188 3253 cmd = nvme_alloc_cmd(nvme, (xfer->x_flags & BD_XFER_POLL) ?
3189 3254 KM_NOSLEEP : KM_SLEEP);
3190 3255
3191 3256 if (cmd == NULL)
3192 3257 return (NULL);
3193 3258
3194 3259 cmd->nc_sqe.sqe_opc = opc;
3195 3260 cmd->nc_callback = nvme_bd_xfer_done;
3196 3261 cmd->nc_xfer = xfer;
3197 3262
3198 3263 switch (opc) {
3199 3264 case NVME_OPC_NVM_WRITE:
3200 3265 case NVME_OPC_NVM_READ:
3201 3266 VERIFY(xfer->x_nblks <= 0x10000);
3202 3267
3203 3268 cmd->nc_sqe.sqe_nsid = ns->ns_id;
3204 3269
3205 3270 cmd->nc_sqe.sqe_cdw10 = xfer->x_blkno & 0xffffffffu;
3206 3271 cmd->nc_sqe.sqe_cdw11 = (xfer->x_blkno >> 32);
3207 3272 cmd->nc_sqe.sqe_cdw12 = (uint16_t)(xfer->x_nblks - 1);
3208 3273
3209 3274 if (nvme_fill_prp(cmd, xfer) != DDI_SUCCESS)
3210 3275 goto fail;
3211 3276 break;
3212 3277
3213 3278 case NVME_OPC_NVM_FLUSH:
3214 3279 cmd->nc_sqe.sqe_nsid = ns->ns_id;
3215 3280 break;
3216 3281
3217 3282 default:
3218 3283 goto fail;
3219 3284 }
3220 3285
3221 3286 return (cmd);
3222 3287
3223 3288 fail:
3224 3289 nvme_free_cmd(cmd);
3225 3290 return (NULL);
3226 3291 }
3227 3292
3228 3293 static void
3229 3294 nvme_bd_xfer_done(void *arg)
3230 3295 {
3231 3296 nvme_cmd_t *cmd = arg;
3232 3297 bd_xfer_t *xfer = cmd->nc_xfer;
3233 3298 int error = 0;
3234 3299
3235 3300 error = nvme_check_cmd_status(cmd);
3236 3301 nvme_free_cmd(cmd);
3237 3302
3238 3303 bd_xfer_done(xfer, error);
3239 3304 }
3240 3305
3241 3306 static void
3242 3307 nvme_bd_driveinfo(void *arg, bd_drive_t *drive)
3243 3308 {
3244 3309 nvme_namespace_t *ns = arg;
3245 3310 nvme_t *nvme = ns->ns_nvme;
3246 3311
3247 3312 /*
3248 3313 * blkdev maintains one queue size per instance (namespace),
3249 3314 * but all namespace share the I/O queues.
3250 3315 * TODO: need to figure out a sane default, or use per-NS I/O queues,
3251 3316 * or change blkdev to handle EAGAIN
3252 3317 */
3253 3318 drive->d_qsize = nvme->n_ioq_count * nvme->n_io_queue_len
3254 3319 / nvme->n_namespace_count;
3255 3320
3256 3321 /*
3257 3322 * d_maxxfer is not set, which means the value is taken from the DMA
3258 3323 * attributes specified to bd_alloc_handle.
3259 3324 */
3260 3325
3261 3326 drive->d_removable = B_FALSE;
3262 3327 drive->d_hotpluggable = B_FALSE;
3263 3328
3264 3329 bcopy(ns->ns_eui64, drive->d_eui64, sizeof (drive->d_eui64));
3265 3330 drive->d_target = ns->ns_id;
3266 3331 drive->d_lun = 0;
3267 3332
3268 3333 drive->d_model = nvme->n_idctl->id_model;
3269 3334 drive->d_model_len = sizeof (nvme->n_idctl->id_model);
3270 3335 drive->d_vendor = nvme->n_vendor;
3271 3336 drive->d_vendor_len = strlen(nvme->n_vendor);
3272 3337 drive->d_product = nvme->n_product;
3273 3338 drive->d_product_len = strlen(nvme->n_product);
3274 3339 drive->d_serial = nvme->n_idctl->id_serial;
3275 3340 drive->d_serial_len = sizeof (nvme->n_idctl->id_serial);
3276 3341 drive->d_revision = nvme->n_idctl->id_fwrev;
3277 3342 drive->d_revision_len = sizeof (nvme->n_idctl->id_fwrev);
3278 3343 }
3279 3344
3280 3345 static int
3281 3346 nvme_bd_mediainfo(void *arg, bd_media_t *media)
3282 3347 {
3283 3348 nvme_namespace_t *ns = arg;
3284 3349
3285 3350 media->m_nblks = ns->ns_block_count;
3286 3351 media->m_blksize = ns->ns_block_size;
3287 3352 media->m_readonly = B_FALSE;
3288 3353 media->m_solidstate = B_TRUE;
3289 3354
3290 3355 media->m_pblksize = ns->ns_best_block_size;
3291 3356
3292 3357 return (0);
3293 3358 }
3294 3359
3295 3360 static int
3296 3361 nvme_bd_cmd(nvme_namespace_t *ns, bd_xfer_t *xfer, uint8_t opc)
3297 3362 {
3298 3363 nvme_t *nvme = ns->ns_nvme;
3299 3364 nvme_cmd_t *cmd;
3300 3365 nvme_qpair_t *ioq;
3301 3366 boolean_t poll;
3302 3367 int ret;
3303 3368
3304 3369 if (nvme->n_dead)
3305 3370 return (EIO);
3306 3371
3307 3372 cmd = nvme_create_nvm_cmd(ns, opc, xfer);
3308 3373 if (cmd == NULL)
3309 3374 return (ENOMEM);
3310 3375
3311 3376 cmd->nc_sqid = (CPU->cpu_id % nvme->n_ioq_count) + 1;
3312 3377 ASSERT(cmd->nc_sqid <= nvme->n_ioq_count);
3313 3378 ioq = nvme->n_ioq[cmd->nc_sqid];
3314 3379
3315 3380 /*
3316 3381 * Get the polling flag before submitting the command. The command may
3317 3382 * complete immediately after it was submitted, which means we must
3318 3383 * treat both cmd and xfer as if they have been freed already.
3319 3384 */
3320 3385 poll = (xfer->x_flags & BD_XFER_POLL) != 0;
3321 3386
3322 3387 ret = nvme_submit_io_cmd(ioq, cmd);
3323 3388
3324 3389 if (ret != 0)
3325 3390 return (ret);
3326 3391
3327 3392 if (!poll)
3328 3393 return (0);
3329 3394
3330 3395 do {
3331 3396 cmd = nvme_retrieve_cmd(nvme, ioq);
3332 3397 if (cmd != NULL)
3333 3398 nvme_bd_xfer_done(cmd);
3334 3399 else
3335 3400 drv_usecwait(10);
3336 3401 } while (ioq->nq_active_cmds != 0);
3337 3402
3338 3403 return (0);
3339 3404 }
3340 3405
3341 3406 static int
3342 3407 nvme_bd_read(void *arg, bd_xfer_t *xfer)
3343 3408 {
3344 3409 nvme_namespace_t *ns = arg;
3345 3410
3346 3411 return (nvme_bd_cmd(ns, xfer, NVME_OPC_NVM_READ));
3347 3412 }
3348 3413
3349 3414 static int
3350 3415 nvme_bd_write(void *arg, bd_xfer_t *xfer)
3351 3416 {
3352 3417 nvme_namespace_t *ns = arg;
3353 3418
3354 3419 return (nvme_bd_cmd(ns, xfer, NVME_OPC_NVM_WRITE));
3355 3420 }
3356 3421
3357 3422 static int
3358 3423 nvme_bd_sync(void *arg, bd_xfer_t *xfer)
3359 3424 {
3360 3425 nvme_namespace_t *ns = arg;
3361 3426
3362 3427 if (ns->ns_nvme->n_dead)
3363 3428 return (EIO);
3364 3429
3365 3430 /*
3366 3431 * If the volatile write cache is not present or not enabled the FLUSH
3367 3432 * command is a no-op, so we can take a shortcut here.
3368 3433 */
3369 3434 if (!ns->ns_nvme->n_write_cache_present) {
3370 3435 bd_xfer_done(xfer, ENOTSUP);
3371 3436 return (0);
3372 3437 }
3373 3438
3374 3439 if (!ns->ns_nvme->n_write_cache_enabled) {
3375 3440 bd_xfer_done(xfer, 0);
3376 3441 return (0);
3377 3442 }
3378 3443
3379 3444 return (nvme_bd_cmd(ns, xfer, NVME_OPC_NVM_FLUSH));
3380 3445 }
3381 3446
3382 3447 static int
3383 3448 nvme_bd_devid(void *arg, dev_info_t *devinfo, ddi_devid_t *devid)
3384 3449 {
3385 3450 nvme_namespace_t *ns = arg;
3386 3451
3387 3452 /*LINTED: E_BAD_PTR_CAST_ALIGN*/
3388 3453 if (*(uint64_t *)ns->ns_eui64 != 0) {
3389 3454 return (ddi_devid_init(devinfo, DEVID_SCSI3_WWN,
3390 3455 sizeof (ns->ns_eui64), ns->ns_eui64, devid));
3391 3456 } else {
3392 3457 return (ddi_devid_init(devinfo, DEVID_ENCAP,
3393 3458 strlen(ns->ns_devid), ns->ns_devid, devid));
3394 3459 }
3395 3460 }
3396 3461
3397 3462 static int
3398 3463 nvme_open(dev_t *devp, int flag, int otyp, cred_t *cred_p)
3399 3464 {
3400 3465 #ifndef __lock_lint
3401 3466 _NOTE(ARGUNUSED(cred_p));
3402 3467 #endif
3403 3468 minor_t minor = getminor(*devp);
3404 3469 nvme_t *nvme = ddi_get_soft_state(nvme_state, NVME_MINOR_INST(minor));
3405 3470 int nsid = NVME_MINOR_NSID(minor);
3406 3471 nvme_minor_state_t *nm;
3407 3472 int rv = 0;
3408 3473
3409 3474 if (otyp != OTYP_CHR)
3410 3475 return (EINVAL);
3411 3476
3412 3477 if (nvme == NULL)
3413 3478 return (ENXIO);
3414 3479
3415 3480 if (nsid > nvme->n_namespace_count)
3416 3481 return (ENXIO);
3417 3482
3418 3483 if (nvme->n_dead)
3419 3484 return (EIO);
3420 3485
3421 3486 nm = nsid == 0 ? &nvme->n_minor : &nvme->n_ns[nsid - 1].ns_minor;
3422 3487
3423 3488 mutex_enter(&nm->nm_mutex);
3424 3489 if (nm->nm_oexcl) {
3425 3490 rv = EBUSY;
3426 3491 goto out;
3427 3492 }
3428 3493
3429 3494 if (flag & FEXCL) {
3430 3495 if (nm->nm_ocnt != 0) {
3431 3496 rv = EBUSY;
3432 3497 goto out;
3433 3498 }
3434 3499 nm->nm_oexcl = B_TRUE;
3435 3500 }
3436 3501
3437 3502 nm->nm_ocnt++;
3438 3503
3439 3504 out:
3440 3505 mutex_exit(&nm->nm_mutex);
3441 3506 return (rv);
3442 3507
3443 3508 }
3444 3509
3445 3510 static int
3446 3511 nvme_close(dev_t dev, int flag, int otyp, cred_t *cred_p)
3447 3512 {
3448 3513 #ifndef __lock_lint
3449 3514 _NOTE(ARGUNUSED(cred_p));
3450 3515 _NOTE(ARGUNUSED(flag));
3451 3516 #endif
3452 3517 minor_t minor = getminor(dev);
3453 3518 nvme_t *nvme = ddi_get_soft_state(nvme_state, NVME_MINOR_INST(minor));
3454 3519 int nsid = NVME_MINOR_NSID(minor);
3455 3520 nvme_minor_state_t *nm;
3456 3521
3457 3522 if (otyp != OTYP_CHR)
3458 3523 return (ENXIO);
3459 3524
3460 3525 if (nvme == NULL)
3461 3526 return (ENXIO);
3462 3527
3463 3528 if (nsid > nvme->n_namespace_count)
3464 3529 return (ENXIO);
3465 3530
3466 3531 nm = nsid == 0 ? &nvme->n_minor : &nvme->n_ns[nsid - 1].ns_minor;
3467 3532
3468 3533 mutex_enter(&nm->nm_mutex);
3469 3534 if (nm->nm_oexcl)
3470 3535 nm->nm_oexcl = B_FALSE;
3471 3536
3472 3537 ASSERT(nm->nm_ocnt > 0);
3473 3538 nm->nm_ocnt--;
3474 3539 mutex_exit(&nm->nm_mutex);
3475 3540
3476 3541 return (0);
3477 3542 }
3478 3543
3479 3544 static int
3480 3545 nvme_ioctl_identify(nvme_t *nvme, int nsid, nvme_ioctl_t *nioc, int mode,
3481 3546 cred_t *cred_p)
3482 3547 {
3483 3548 _NOTE(ARGUNUSED(cred_p));
3484 3549 int rv = 0;
3485 3550 void *idctl;
3486 3551
3487 3552 if ((mode & FREAD) == 0)
3488 3553 return (EPERM);
3489 3554
3490 3555 if (nioc->n_len < NVME_IDENTIFY_BUFSIZE)
3491 3556 return (EINVAL);
3492 3557
3493 3558 if ((rv = nvme_identify(nvme, nsid, (void **)&idctl)) != 0)
3494 3559 return (rv);
3495 3560
3496 3561 if (ddi_copyout(idctl, (void *)nioc->n_buf, NVME_IDENTIFY_BUFSIZE, mode)
3497 3562 != 0)
3498 3563 rv = EFAULT;
3499 3564
3500 3565 kmem_free(idctl, NVME_IDENTIFY_BUFSIZE);
3501 3566
3502 3567 return (rv);
3503 3568 }
3504 3569
3505 3570 static int
3506 3571 nvme_ioctl_capabilities(nvme_t *nvme, int nsid, nvme_ioctl_t *nioc,
3507 3572 int mode, cred_t *cred_p)
3508 3573 {
3509 3574 _NOTE(ARGUNUSED(nsid, cred_p));
3510 3575 int rv = 0;
3511 3576 nvme_reg_cap_t cap = { 0 };
3512 3577 nvme_capabilities_t nc;
3513 3578
3514 3579 if ((mode & FREAD) == 0)
3515 3580 return (EPERM);
3516 3581
3517 3582 if (nioc->n_len < sizeof (nc))
3518 3583 return (EINVAL);
3519 3584
3520 3585 cap.r = nvme_get64(nvme, NVME_REG_CAP);
3521 3586
3522 3587 /*
3523 3588 * The MPSMIN and MPSMAX fields in the CAP register use 0 to
3524 3589 * specify the base page size of 4k (1<<12), so add 12 here to
3525 3590 * get the real page size value.
3526 3591 */
3527 3592 nc.mpsmax = 1 << (12 + cap.b.cap_mpsmax);
3528 3593 nc.mpsmin = 1 << (12 + cap.b.cap_mpsmin);
3529 3594
3530 3595 if (ddi_copyout(&nc, (void *)nioc->n_buf, sizeof (nc), mode) != 0)
3531 3596 rv = EFAULT;
3532 3597
3533 3598 return (rv);
3534 3599 }
3535 3600
3536 3601 static int
3537 3602 nvme_ioctl_get_logpage(nvme_t *nvme, int nsid, nvme_ioctl_t *nioc,
3538 3603 int mode, cred_t *cred_p)
3539 3604 {
3540 3605 _NOTE(ARGUNUSED(cred_p));
3541 3606 void *log = NULL;
3542 3607 size_t bufsize = 0;
3543 3608 int rv = 0;
3544 3609
3545 3610 if ((mode & FREAD) == 0)
3546 3611 return (EPERM);
3547 3612
3548 3613 switch (nioc->n_arg) {
3549 3614 case NVME_LOGPAGE_ERROR:
3550 3615 if (nsid != 0)
3551 3616 return (EINVAL);
3552 3617 break;
3553 3618 case NVME_LOGPAGE_HEALTH:
3554 3619 if (nsid != 0 && nvme->n_idctl->id_lpa.lp_smart == 0)
3555 3620 return (EINVAL);
3556 3621
3557 3622 if (nsid == 0)
3558 3623 nsid = (uint32_t)-1;
3559 3624
3560 3625 break;
3561 3626 case NVME_LOGPAGE_FWSLOT:
3562 3627 if (nsid != 0)
3563 3628 return (EINVAL);
3564 3629 break;
3565 3630 default:
3566 3631 return (EINVAL);
3567 3632 }
3568 3633
3569 3634 if (nvme_get_logpage(nvme, &log, &bufsize, nioc->n_arg, nsid)
3570 3635 != DDI_SUCCESS)
3571 3636 return (EIO);
3572 3637
3573 3638 if (nioc->n_len < bufsize) {
3574 3639 kmem_free(log, bufsize);
3575 3640 return (EINVAL);
3576 3641 }
3577 3642
3578 3643 if (ddi_copyout(log, (void *)nioc->n_buf, bufsize, mode) != 0)
3579 3644 rv = EFAULT;
3580 3645
3581 3646 nioc->n_len = bufsize;
3582 3647 kmem_free(log, bufsize);
3583 3648
3584 3649 return (rv);
3585 3650 }
3586 3651
3587 3652 static int
3588 3653 nvme_ioctl_get_features(nvme_t *nvme, int nsid, nvme_ioctl_t *nioc,
3589 3654 int mode, cred_t *cred_p)
3590 3655 {
3591 3656 _NOTE(ARGUNUSED(cred_p));
3592 3657 void *buf = NULL;
3593 3658 size_t bufsize = 0;
3594 3659 uint32_t res = 0;
3595 3660 uint8_t feature;
3596 3661 int rv = 0;
3597 3662
3598 3663 if ((mode & FREAD) == 0)
3599 3664 return (EPERM);
3600 3665
3601 3666 if ((nioc->n_arg >> 32) > 0xff)
3602 3667 return (EINVAL);
3603 3668
3604 3669 feature = (uint8_t)(nioc->n_arg >> 32);
3605 3670
3606 3671 switch (feature) {
3607 3672 case NVME_FEAT_ARBITRATION:
3608 3673 case NVME_FEAT_POWER_MGMT:
3609 3674 case NVME_FEAT_TEMPERATURE:
3610 3675 case NVME_FEAT_ERROR:
3611 3676 case NVME_FEAT_NQUEUES:
3612 3677 case NVME_FEAT_INTR_COAL:
3613 3678 case NVME_FEAT_WRITE_ATOM:
3614 3679 case NVME_FEAT_ASYNC_EVENT:
3615 3680 case NVME_FEAT_PROGRESS:
3616 3681 if (nsid != 0)
3617 3682 return (EINVAL);
3618 3683 break;
3619 3684
3620 3685 case NVME_FEAT_INTR_VECT:
3621 3686 if (nsid != 0)
3622 3687 return (EINVAL);
3623 3688
3624 3689 res = nioc->n_arg & 0xffffffffUL;
3625 3690 if (res >= nvme->n_intr_cnt)
3626 3691 return (EINVAL);
3627 3692 break;
3628 3693
3629 3694 case NVME_FEAT_LBA_RANGE:
3630 3695 if (nvme->n_lba_range_supported == B_FALSE)
3631 3696 return (EINVAL);
3632 3697
3633 3698 if (nsid == 0 ||
3634 3699 nsid > nvme->n_namespace_count)
3635 3700 return (EINVAL);
3636 3701
3637 3702 break;
3638 3703
3639 3704 case NVME_FEAT_WRITE_CACHE:
3640 3705 if (nsid != 0)
3641 3706 return (EINVAL);
3642 3707
3643 3708 if (!nvme->n_write_cache_present)
3644 3709 return (EINVAL);
3645 3710
3646 3711 break;
3647 3712
3648 3713 case NVME_FEAT_AUTO_PST:
3649 3714 if (nsid != 0)
3650 3715 return (EINVAL);
3651 3716
3652 3717 if (!nvme->n_auto_pst_supported)
3653 3718 return (EINVAL);
3654 3719
3655 3720 break;
3656 3721
3657 3722 default:
3658 3723 return (EINVAL);
3659 3724 }
3660 3725
3661 3726 rv = nvme_get_features(nvme, nsid, feature, &res, &buf, &bufsize);
3662 3727 if (rv != 0)
3663 3728 return (rv);
3664 3729
3665 3730 if (nioc->n_len < bufsize) {
3666 3731 kmem_free(buf, bufsize);
3667 3732 return (EINVAL);
3668 3733 }
3669 3734
3670 3735 if (buf && ddi_copyout(buf, (void*)nioc->n_buf, bufsize, mode) != 0)
3671 3736 rv = EFAULT;
3672 3737
3673 3738 kmem_free(buf, bufsize);
3674 3739 nioc->n_arg = res;
3675 3740 nioc->n_len = bufsize;
3676 3741
3677 3742 return (rv);
3678 3743 }
3679 3744
3680 3745 static int
3681 3746 nvme_ioctl_intr_cnt(nvme_t *nvme, int nsid, nvme_ioctl_t *nioc, int mode,
3682 3747 cred_t *cred_p)
3683 3748 {
3684 3749 _NOTE(ARGUNUSED(nsid, mode, cred_p));
3685 3750
3686 3751 if ((mode & FREAD) == 0)
3687 3752 return (EPERM);
3688 3753
3689 3754 nioc->n_arg = nvme->n_intr_cnt;
3690 3755 return (0);
3691 3756 }
3692 3757
3693 3758 static int
3694 3759 nvme_ioctl_version(nvme_t *nvme, int nsid, nvme_ioctl_t *nioc, int mode,
3695 3760 cred_t *cred_p)
3696 3761 {
3697 3762 _NOTE(ARGUNUSED(nsid, cred_p));
3698 3763 int rv = 0;
3699 3764
3700 3765 if ((mode & FREAD) == 0)
3701 3766 return (EPERM);
3702 3767
3703 3768 if (nioc->n_len < sizeof (nvme->n_version))
3704 3769 return (ENOMEM);
3705 3770
3706 3771 if (ddi_copyout(&nvme->n_version, (void *)nioc->n_buf,
3707 3772 sizeof (nvme->n_version), mode) != 0)
3708 3773 rv = EFAULT;
3709 3774
3710 3775 return (rv);
3711 3776 }
3712 3777
3713 3778 static int
3714 3779 nvme_ioctl_format(nvme_t *nvme, int nsid, nvme_ioctl_t *nioc, int mode,
3715 3780 cred_t *cred_p)
3716 3781 {
3717 3782 _NOTE(ARGUNUSED(mode));
3718 3783 nvme_format_nvm_t frmt = { 0 };
3719 3784 int c_nsid = nsid != 0 ? nsid - 1 : 0;
3720 3785
3721 3786 if ((mode & FWRITE) == 0 || secpolicy_sys_config(cred_p, B_FALSE) != 0)
3722 3787 return (EPERM);
3723 3788
3724 3789 frmt.r = nioc->n_arg & 0xffffffff;
3725 3790
3726 3791 /*
3727 3792 * Check whether the FORMAT NVM command is supported.
3728 3793 */
3729 3794 if (nvme->n_idctl->id_oacs.oa_format == 0)
3730 3795 return (EINVAL);
3731 3796
3732 3797 /*
3733 3798 * Don't allow format or secure erase of individual namespace if that
3734 3799 * would cause a format or secure erase of all namespaces.
3735 3800 */
3736 3801 if (nsid != 0 && nvme->n_idctl->id_fna.fn_format != 0)
3737 3802 return (EINVAL);
3738 3803
3739 3804 if (nsid != 0 && frmt.b.fm_ses != NVME_FRMT_SES_NONE &&
3740 3805 nvme->n_idctl->id_fna.fn_sec_erase != 0)
3741 3806 return (EINVAL);
3742 3807
3743 3808 /*
3744 3809 * Don't allow formatting with Protection Information.
3745 3810 */
3746 3811 if (frmt.b.fm_pi != 0 || frmt.b.fm_pil != 0 || frmt.b.fm_ms != 0)
3747 3812 return (EINVAL);
3748 3813
3749 3814 /*
3750 3815 * Don't allow formatting using an illegal LBA format, or any LBA format
3751 3816 * that uses metadata.
3752 3817 */
3753 3818 if (frmt.b.fm_lbaf > nvme->n_ns[c_nsid].ns_idns->id_nlbaf ||
3754 3819 nvme->n_ns[c_nsid].ns_idns->id_lbaf[frmt.b.fm_lbaf].lbaf_ms != 0)
3755 3820 return (EINVAL);
3756 3821
3757 3822 /*
3758 3823 * Don't allow formatting using an illegal Secure Erase setting.
3759 3824 */
3760 3825 if (frmt.b.fm_ses > NVME_FRMT_MAX_SES ||
3761 3826 (frmt.b.fm_ses == NVME_FRMT_SES_CRYPTO &&
3762 3827 nvme->n_idctl->id_fna.fn_crypt_erase == 0))
3763 3828 return (EINVAL);
3764 3829
3765 3830 if (nsid == 0)
3766 3831 nsid = (uint32_t)-1;
3767 3832
3768 3833 return (nvme_format_nvm(nvme, nsid, frmt.b.fm_lbaf, B_FALSE, 0, B_FALSE,
3769 3834 frmt.b.fm_ses));
3770 3835 }
3771 3836
3772 3837 static int
3773 3838 nvme_ioctl_detach(nvme_t *nvme, int nsid, nvme_ioctl_t *nioc, int mode,
3774 3839 cred_t *cred_p)
3775 3840 {
3776 3841 _NOTE(ARGUNUSED(nioc, mode));
3777 3842 int rv = 0;
3778 3843
3779 3844 if ((mode & FWRITE) == 0 || secpolicy_sys_config(cred_p, B_FALSE) != 0)
3780 3845 return (EPERM);
3781 3846
3782 3847 if (nsid == 0)
3783 3848 return (EINVAL);
3784 3849
3785 3850 rv = bd_detach_handle(nvme->n_ns[nsid - 1].ns_bd_hdl);
3786 3851 if (rv != DDI_SUCCESS)
3787 3852 rv = EBUSY;
3788 3853
3789 3854 return (rv);
3790 3855 }
3791 3856
3792 3857 static int
3793 3858 nvme_ioctl_attach(nvme_t *nvme, int nsid, nvme_ioctl_t *nioc, int mode,
3794 3859 cred_t *cred_p)
3795 3860 {
3796 3861 _NOTE(ARGUNUSED(nioc, mode));
3797 3862 nvme_identify_nsid_t *idns;
3798 3863 int rv = 0;
3799 3864
3800 3865 if ((mode & FWRITE) == 0 || secpolicy_sys_config(cred_p, B_FALSE) != 0)
3801 3866 return (EPERM);
3802 3867
3803 3868 if (nsid == 0)
3804 3869 return (EINVAL);
3805 3870
3806 3871 /*
3807 3872 * Identify namespace again, free old identify data.
3808 3873 */
3809 3874 idns = nvme->n_ns[nsid - 1].ns_idns;
3810 3875 if (nvme_init_ns(nvme, nsid) != DDI_SUCCESS)
3811 3876 return (EIO);
3812 3877
3813 3878 kmem_free(idns, sizeof (nvme_identify_nsid_t));
3814 3879
3815 3880 rv = bd_attach_handle(nvme->n_dip, nvme->n_ns[nsid - 1].ns_bd_hdl);
3816 3881 if (rv != DDI_SUCCESS)
3817 3882 rv = EBUSY;
3818 3883
3819 3884 return (rv);
3820 3885 }
3821 3886
3822 3887 static int
3823 3888 nvme_ioctl(dev_t dev, int cmd, intptr_t arg, int mode, cred_t *cred_p,
3824 3889 int *rval_p)
3825 3890 {
3826 3891 #ifndef __lock_lint
3827 3892 _NOTE(ARGUNUSED(rval_p));
3828 3893 #endif
3829 3894 minor_t minor = getminor(dev);
3830 3895 nvme_t *nvme = ddi_get_soft_state(nvme_state, NVME_MINOR_INST(minor));
3831 3896 int nsid = NVME_MINOR_NSID(minor);
3832 3897 int rv = 0;
3833 3898 nvme_ioctl_t nioc;
3834 3899
3835 3900 int (*nvme_ioctl[])(nvme_t *, int, nvme_ioctl_t *, int, cred_t *) = {
3836 3901 NULL,
3837 3902 nvme_ioctl_identify,
3838 3903 nvme_ioctl_identify,
3839 3904 nvme_ioctl_capabilities,
3840 3905 nvme_ioctl_get_logpage,
3841 3906 nvme_ioctl_get_features,
3842 3907 nvme_ioctl_intr_cnt,
3843 3908 nvme_ioctl_version,
3844 3909 nvme_ioctl_format,
3845 3910 nvme_ioctl_detach,
3846 3911 nvme_ioctl_attach
3847 3912 };
3848 3913
3849 3914 if (nvme == NULL)
3850 3915 return (ENXIO);
3851 3916
3852 3917 if (nsid > nvme->n_namespace_count)
3853 3918 return (ENXIO);
3854 3919
3855 3920 if (IS_DEVCTL(cmd))
3856 3921 return (ndi_devctl_ioctl(nvme->n_dip, cmd, arg, mode, 0));
3857 3922
3858 3923 #ifdef _MULTI_DATAMODEL
3859 3924 switch (ddi_model_convert_from(mode & FMODELS)) {
3860 3925 case DDI_MODEL_ILP32: {
3861 3926 nvme_ioctl32_t nioc32;
3862 3927 if (ddi_copyin((void*)arg, &nioc32, sizeof (nvme_ioctl32_t),
3863 3928 mode) != 0)
3864 3929 return (EFAULT);
3865 3930 nioc.n_len = nioc32.n_len;
3866 3931 nioc.n_buf = nioc32.n_buf;
3867 3932 nioc.n_arg = nioc32.n_arg;
3868 3933 break;
3869 3934 }
3870 3935 case DDI_MODEL_NONE:
3871 3936 #endif
3872 3937 if (ddi_copyin((void*)arg, &nioc, sizeof (nvme_ioctl_t), mode)
3873 3938 != 0)
3874 3939 return (EFAULT);
3875 3940 #ifdef _MULTI_DATAMODEL
3876 3941 break;
3877 3942 }
3878 3943 #endif
3879 3944
3880 3945 if (nvme->n_dead && cmd != NVME_IOC_DETACH)
3881 3946 return (EIO);
3882 3947
3883 3948
3884 3949 if (cmd == NVME_IOC_IDENTIFY_CTRL) {
3885 3950 /*
3886 3951 * This makes NVME_IOC_IDENTIFY_CTRL work the same on devctl and
3887 3952 * attachment point nodes.
3888 3953 */
3889 3954 nsid = 0;
3890 3955 } else if (cmd == NVME_IOC_IDENTIFY_NSID && nsid == 0) {
3891 3956 /*
3892 3957 * This makes NVME_IOC_IDENTIFY_NSID work on a devctl node, it
3893 3958 * will always return identify data for namespace 1.
3894 3959 */
3895 3960 nsid = 1;
3896 3961 }
3897 3962
3898 3963 if (IS_NVME_IOC(cmd) && nvme_ioctl[NVME_IOC_CMD(cmd)] != NULL)
3899 3964 rv = nvme_ioctl[NVME_IOC_CMD(cmd)](nvme, nsid, &nioc, mode,
3900 3965 cred_p);
3901 3966 else
3902 3967 rv = EINVAL;
3903 3968
3904 3969 #ifdef _MULTI_DATAMODEL
3905 3970 switch (ddi_model_convert_from(mode & FMODELS)) {
3906 3971 case DDI_MODEL_ILP32: {
3907 3972 nvme_ioctl32_t nioc32;
3908 3973
3909 3974 nioc32.n_len = (size32_t)nioc.n_len;
3910 3975 nioc32.n_buf = (uintptr32_t)nioc.n_buf;
3911 3976 nioc32.n_arg = nioc.n_arg;
3912 3977
3913 3978 if (ddi_copyout(&nioc32, (void *)arg, sizeof (nvme_ioctl32_t),
3914 3979 mode) != 0)
3915 3980 return (EFAULT);
3916 3981 break;
3917 3982 }
3918 3983 case DDI_MODEL_NONE:
3919 3984 #endif
3920 3985 if (ddi_copyout(&nioc, (void *)arg, sizeof (nvme_ioctl_t), mode)
3921 3986 != 0)
3922 3987 return (EFAULT);
3923 3988 #ifdef _MULTI_DATAMODEL
3924 3989 break;
3925 3990 }
3926 3991 #endif
3927 3992
3928 3993 return (rv);
3929 3994 }
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