1 /*
2 * This file and its contents are supplied under the terms of the
3 * Common Development and Distribution License ("CDDL"), version 1.0.
4 * You may only use this file in accordance with the terms of version
5 * 1.0 of the CDDL.
6 *
7 * A full copy of the text of the CDDL should have accompanied this
8 * source. A copy of the CDDL is also available via the Internet at
9 * http://www.illumos.org/license/CDDL.
10 */
11
12 /*
13 * Copyright 2018 Nexenta Systems, Inc.
14 * Copyright 2016 Tegile Systems, Inc. All rights reserved.
15 * Copyright (c) 2016 The MathWorks, Inc. All rights reserved.
16 * Copyright 2018 Joyent, Inc.
17 */
18
19 /*
20 * blkdev driver for NVMe compliant storage devices
21 *
22 * This driver was written to conform to version 1.2.1 of the NVMe
23 * specification. It may work with newer versions, but that is completely
24 * untested and disabled by default.
25 *
26 * The driver has only been tested on x86 systems and will not work on big-
27 * endian systems without changes to the code accessing registers and data
28 * structures used by the hardware.
29 *
30 *
31 * Interrupt Usage:
32 *
33 * The driver will use a single interrupt while configuring the device as the
34 * specification requires, but contrary to the specification it will try to use
35 * a single-message MSI(-X) or FIXED interrupt. Later in the attach process it
36 * will switch to multiple-message MSI(-X) if supported. The driver wants to
37 * have one interrupt vector per CPU, but it will work correctly if less are
38 * available. Interrupts can be shared by queues, the interrupt handler will
39 * iterate through the I/O queue array by steps of n_intr_cnt. Usually only
40 * the admin queue will share an interrupt with one I/O queue. The interrupt
41 * handler will retrieve completed commands from all queues sharing an interrupt
42 * vector and will post them to a taskq for completion processing.
43 *
44 *
45 * Command Processing:
46 *
47 * NVMe devices can have up to 65535 I/O queue pairs, with each queue holding up
48 * to 65536 I/O commands. The driver will configure one I/O queue pair per
49 * available interrupt vector, with the queue length usually much smaller than
50 * the maximum of 65536. If the hardware doesn't provide enough queues, fewer
51 * interrupt vectors will be used.
52 *
53 * Additionally the hardware provides a single special admin queue pair that can
54 * hold up to 4096 admin commands.
55 *
56 * From the hardware perspective both queues of a queue pair are independent,
57 * but they share some driver state: the command array (holding pointers to
58 * commands currently being processed by the hardware) and the active command
59 * counter. Access to a queue pair and the shared state is protected by
60 * nq_mutex.
61 *
62 * When a command is submitted to a queue pair the active command counter is
63 * incremented and a pointer to the command is stored in the command array. The
64 * array index is used as command identifier (CID) in the submission queue
65 * entry. Some commands may take a very long time to complete, and if the queue
66 * wraps around in that time a submission may find the next array slot to still
67 * be used by a long-running command. In this case the array is sequentially
68 * searched for the next free slot. The length of the command array is the same
69 * as the configured queue length. Queue overrun is prevented by the semaphore,
70 * so a command submission may block if the queue is full.
71 *
72 *
73 * Polled I/O Support:
74 *
75 * For kernel core dump support the driver can do polled I/O. As interrupts are
76 * turned off while dumping the driver will just submit a command in the regular
77 * way, and then repeatedly attempt a command retrieval until it gets the
78 * command back.
79 *
80 *
81 * Namespace Support:
82 *
83 * NVMe devices can have multiple namespaces, each being a independent data
84 * store. The driver supports multiple namespaces and creates a blkdev interface
85 * for each namespace found. Namespaces can have various attributes to support
86 * protection information. This driver does not support any of this and ignores
87 * namespaces that have these attributes.
88 *
89 * As of NVMe 1.1 namespaces can have an 64bit Extended Unique Identifier
90 * (EUI64). This driver uses the EUI64 if present to generate the devid and
91 * passes it to blkdev to use it in the device node names. As this is currently
92 * untested namespaces with EUI64 are ignored by default.
93 *
94 * We currently support only (2 << NVME_MINOR_INST_SHIFT) - 2 namespaces in a
95 * single controller. This is an artificial limit imposed by the driver to be
96 * able to address a reasonable number of controllers and namespaces using a
97 * 32bit minor node number.
98 *
99 *
100 * Minor nodes:
101 *
102 * For each NVMe device the driver exposes one minor node for the controller and
103 * one minor node for each namespace. The only operations supported by those
104 * minor nodes are open(9E), close(9E), and ioctl(9E). This serves as the
105 * interface for the nvmeadm(1M) utility.
106 *
107 *
108 * Blkdev Interface:
109 *
110 * This driver uses blkdev to do all the heavy lifting involved with presenting
111 * a disk device to the system. As a result, the processing of I/O requests is
112 * relatively simple as blkdev takes care of partitioning, boundary checks, DMA
113 * setup, and splitting of transfers into manageable chunks.
114 *
115 * I/O requests coming in from blkdev are turned into NVM commands and posted to
116 * an I/O queue. The queue is selected by taking the CPU id modulo the number of
117 * queues. There is currently no timeout handling of I/O commands.
118 *
119 * Blkdev also supports querying device/media information and generating a
120 * devid. The driver reports the best block size as determined by the namespace
121 * format back to blkdev as physical block size to support partition and block
122 * alignment. The devid is either based on the namespace EUI64, if present, or
123 * composed using the device vendor ID, model number, serial number, and the
124 * namespace ID.
125 *
126 *
127 * Error Handling:
128 *
129 * Error handling is currently limited to detecting fatal hardware errors,
130 * either by asynchronous events, or synchronously through command status or
131 * admin command timeouts. In case of severe errors the device is fenced off,
132 * all further requests will return EIO. FMA is then called to fault the device.
133 *
134 * The hardware has a limit for outstanding asynchronous event requests. Before
135 * this limit is known the driver assumes it is at least 1 and posts a single
136 * asynchronous request. Later when the limit is known more asynchronous event
137 * requests are posted to allow quicker reception of error information. When an
138 * asynchronous event is posted by the hardware the driver will parse the error
139 * status fields and log information or fault the device, depending on the
140 * severity of the asynchronous event. The asynchronous event request is then
141 * reused and posted to the admin queue again.
142 *
143 * On command completion the command status is checked for errors. In case of
144 * errors indicating a driver bug the driver panics. Almost all other error
145 * status values just cause EIO to be returned.
146 *
147 * Command timeouts are currently detected for all admin commands except
148 * asynchronous event requests. If a command times out and the hardware appears
149 * to be healthy the driver attempts to abort the command. The original command
150 * timeout is also applied to the abort command. If the abort times out too the
151 * driver assumes the device to be dead, fences it off, and calls FMA to retire
152 * it. In all other cases the aborted command should return immediately with a
153 * status indicating it was aborted, and the driver will wait indefinitely for
154 * that to happen. No timeout handling of normal I/O commands is presently done.
155 *
156 * Any command that times out due to the controller dropping dead will be put on
157 * nvme_lost_cmds list if it references DMA memory. This will prevent the DMA
158 * memory being reused by the system and later be written to by a "dead" NVMe
159 * controller.
160 *
161 *
162 * Locking:
163 *
164 * Each queue pair has its own nq_mutex, which must be held when accessing the
165 * associated queue registers or the shared state of the queue pair. Callers of
166 * nvme_unqueue_cmd() must make sure that nq_mutex is held, while
167 * nvme_submit_{admin,io}_cmd() and nvme_retrieve_cmd() take care of this
168 * themselves.
169 *
170 * Each command also has its own nc_mutex, which is associated with the
171 * condition variable nc_cv. It is only used on admin commands which are run
172 * synchronously. In that case it must be held across calls to
173 * nvme_submit_{admin,io}_cmd() and nvme_wait_cmd(), which is taken care of by
174 * nvme_admin_cmd(). It must also be held whenever the completion state of the
175 * command is changed or while a admin command timeout is handled.
176 *
177 * If both nc_mutex and nq_mutex must be held, nc_mutex must be acquired first.
178 * More than one nc_mutex may only be held when aborting commands. In this case,
179 * the nc_mutex of the command to be aborted must be held across the call to
180 * nvme_abort_cmd() to prevent the command from completing while the abort is in
181 * progress.
182 *
183 * Each minor node has its own nm_mutex, which protects the open count nm_ocnt
184 * and exclusive-open flag nm_oexcl.
185 *
186 *
187 * Quiesce / Fast Reboot:
188 *
189 * The driver currently does not support fast reboot. A quiesce(9E) entry point
190 * is still provided which is used to send a shutdown notification to the
191 * device.
192 *
193 *
194 * Driver Configuration:
195 *
196 * The following driver properties can be changed to control some aspects of the
197 * drivers operation:
198 * - strict-version: can be set to 0 to allow devices conforming to newer
199 * major versions to be used
200 * - ignore-unknown-vendor-status: can be set to 1 to not handle any vendor
201 * specific command status as a fatal error leading device faulting
202 * - admin-queue-len: the maximum length of the admin queue (16-4096)
203 * - io-queue-len: the maximum length of the I/O queues (16-65536)
204 * - async-event-limit: the maximum number of asynchronous event requests to be
205 * posted by the driver
206 * - volatile-write-cache-enable: can be set to 0 to disable the volatile write
207 * cache
208 * - min-phys-block-size: the minimum physical block size to report to blkdev,
209 * which is among other things the basis for ZFS vdev ashift
210 *
211 *
212 * TODO:
213 * - figure out sane default for I/O queue depth reported to blkdev
214 * - FMA handling of media errors
215 * - support for devices supporting very large I/O requests using chained PRPs
216 * - support for configuring hardware parameters like interrupt coalescing
217 * - support for media formatting and hard partitioning into namespaces
218 * - support for big-endian systems
219 * - support for fast reboot
220 * - support for firmware updates
221 * - support for NVMe Subsystem Reset (1.1)
222 * - support for Scatter/Gather lists (1.1)
223 * - support for Reservations (1.1)
224 * - support for power management
225 */
226
227 #include <sys/byteorder.h>
228 #ifdef _BIG_ENDIAN
229 #error nvme driver needs porting for big-endian platforms
230 #endif
231
232 #include <sys/modctl.h>
233 #include <sys/conf.h>
234 #include <sys/devops.h>
235 #include <sys/ddi.h>
236 #include <sys/sunddi.h>
237 #include <sys/sunndi.h>
238 #include <sys/bitmap.h>
239 #include <sys/sysmacros.h>
240 #include <sys/param.h>
241 #include <sys/varargs.h>
242 #include <sys/cpuvar.h>
243 #include <sys/disp.h>
244 #include <sys/blkdev.h>
245 #include <sys/atomic.h>
246 #include <sys/archsystm.h>
247 #include <sys/sata/sata_hba.h>
248 #include <sys/stat.h>
249 #include <sys/policy.h>
250 #include <sys/list.h>
251
252 #include <sys/nvme.h>
253
254 #ifdef __x86
255 #include <sys/x86_archext.h>
256 #endif
257
258 #include "nvme_reg.h"
259 #include "nvme_var.h"
260
261 /*
262 * Assertions to make sure that we've properly captured various aspects of the
263 * packed structures and haven't broken them during updates.
264 */
265 CTASSERT(sizeof (nvme_identify_ctrl_t) == 0x1000);
266 CTASSERT(offsetof(nvme_identify_ctrl_t, id_oacs) == 256);
267 CTASSERT(offsetof(nvme_identify_ctrl_t, id_sqes) == 512);
268 CTASSERT(offsetof(nvme_identify_ctrl_t, id_subnqn) == 768);
269 CTASSERT(offsetof(nvme_identify_ctrl_t, id_nvmof) == 1792);
270 CTASSERT(offsetof(nvme_identify_ctrl_t, id_psd) == 2048);
271 CTASSERT(offsetof(nvme_identify_ctrl_t, id_vs) == 3072);
272
273 CTASSERT(sizeof (nvme_identify_nsid_t) == 0x1000);
274 CTASSERT(offsetof(nvme_identify_nsid_t, id_fpi) == 32);
275 CTASSERT(offsetof(nvme_identify_nsid_t, id_nguid) == 104);
276 CTASSERT(offsetof(nvme_identify_nsid_t, id_lbaf) == 128);
277 CTASSERT(offsetof(nvme_identify_nsid_t, id_vs) == 384);
278
279 CTASSERT(sizeof (nvme_identify_primary_caps_t) == 0x1000);
280 CTASSERT(offsetof(nvme_identify_primary_caps_t, nipc_vqfrt) == 32);
281 CTASSERT(offsetof(nvme_identify_primary_caps_t, nipc_vifrt) == 64);
282
283
284 /* NVMe spec version supported */
285 static const int nvme_version_major = 1;
286
287 /* tunable for admin command timeout in seconds, default is 1s */
288 int nvme_admin_cmd_timeout = 1;
289
290 /* tunable for FORMAT NVM command timeout in seconds, default is 600s */
291 int nvme_format_cmd_timeout = 600;
292
293 static int nvme_attach(dev_info_t *, ddi_attach_cmd_t);
294 static int nvme_detach(dev_info_t *, ddi_detach_cmd_t);
295 static int nvme_quiesce(dev_info_t *);
296 static int nvme_fm_errcb(dev_info_t *, ddi_fm_error_t *, const void *);
297 static int nvme_setup_interrupts(nvme_t *, int, int);
298 static void nvme_release_interrupts(nvme_t *);
299 static uint_t nvme_intr(caddr_t, caddr_t);
300
301 static void nvme_shutdown(nvme_t *, int, boolean_t);
302 static boolean_t nvme_reset(nvme_t *, boolean_t);
303 static int nvme_init(nvme_t *);
304 static nvme_cmd_t *nvme_alloc_cmd(nvme_t *, int);
305 static void nvme_free_cmd(nvme_cmd_t *);
306 static nvme_cmd_t *nvme_create_nvm_cmd(nvme_namespace_t *, uint8_t,
307 bd_xfer_t *);
308 static void nvme_admin_cmd(nvme_cmd_t *, int);
309 static void nvme_submit_admin_cmd(nvme_qpair_t *, nvme_cmd_t *);
310 static int nvme_submit_io_cmd(nvme_qpair_t *, nvme_cmd_t *);
311 static void nvme_submit_cmd_common(nvme_qpair_t *, nvme_cmd_t *);
312 static nvme_cmd_t *nvme_unqueue_cmd(nvme_t *, nvme_qpair_t *, int);
313 static nvme_cmd_t *nvme_retrieve_cmd(nvme_t *, nvme_qpair_t *);
314 static void nvme_wait_cmd(nvme_cmd_t *, uint_t);
315 static void nvme_wakeup_cmd(void *);
316 static void nvme_async_event_task(void *);
317
318 static int nvme_check_unknown_cmd_status(nvme_cmd_t *);
319 static int nvme_check_vendor_cmd_status(nvme_cmd_t *);
320 static int nvme_check_integrity_cmd_status(nvme_cmd_t *);
321 static int nvme_check_specific_cmd_status(nvme_cmd_t *);
322 static int nvme_check_generic_cmd_status(nvme_cmd_t *);
323 static inline int nvme_check_cmd_status(nvme_cmd_t *);
324
325 static int nvme_abort_cmd(nvme_cmd_t *, uint_t);
326 static void nvme_async_event(nvme_t *);
327 static int nvme_format_nvm(nvme_t *, uint32_t, uint8_t, boolean_t, uint8_t,
328 boolean_t, uint8_t);
329 static int nvme_get_logpage(nvme_t *, void **, size_t *, uint8_t, ...);
330 static int nvme_identify(nvme_t *, uint32_t, void **);
331 static int nvme_set_features(nvme_t *, uint32_t, uint8_t, uint32_t,
332 uint32_t *);
333 static int nvme_get_features(nvme_t *, uint32_t, uint8_t, uint32_t *,
334 void **, size_t *);
335 static int nvme_write_cache_set(nvme_t *, boolean_t);
336 static int nvme_set_nqueues(nvme_t *, uint16_t *);
337
338 static void nvme_free_dma(nvme_dma_t *);
339 static int nvme_zalloc_dma(nvme_t *, size_t, uint_t, ddi_dma_attr_t *,
340 nvme_dma_t **);
341 static int nvme_zalloc_queue_dma(nvme_t *, uint32_t, uint16_t, uint_t,
342 nvme_dma_t **);
343 static void nvme_free_qpair(nvme_qpair_t *);
344 static int nvme_alloc_qpair(nvme_t *, uint32_t, nvme_qpair_t **, int);
345 static int nvme_create_io_qpair(nvme_t *, nvme_qpair_t *, uint16_t);
346
347 static inline void nvme_put64(nvme_t *, uintptr_t, uint64_t);
348 static inline void nvme_put32(nvme_t *, uintptr_t, uint32_t);
349 static inline uint64_t nvme_get64(nvme_t *, uintptr_t);
350 static inline uint32_t nvme_get32(nvme_t *, uintptr_t);
351
352 static boolean_t nvme_check_regs_hdl(nvme_t *);
353 static boolean_t nvme_check_dma_hdl(nvme_dma_t *);
354
355 static int nvme_fill_prp(nvme_cmd_t *, bd_xfer_t *);
356
357 static void nvme_bd_xfer_done(void *);
358 static void nvme_bd_driveinfo(void *, bd_drive_t *);
359 static int nvme_bd_mediainfo(void *, bd_media_t *);
360 static int nvme_bd_cmd(nvme_namespace_t *, bd_xfer_t *, uint8_t);
361 static int nvme_bd_read(void *, bd_xfer_t *);
362 static int nvme_bd_write(void *, bd_xfer_t *);
363 static int nvme_bd_sync(void *, bd_xfer_t *);
364 static int nvme_bd_devid(void *, dev_info_t *, ddi_devid_t *);
365
366 static int nvme_prp_dma_constructor(void *, void *, int);
367 static void nvme_prp_dma_destructor(void *, void *);
368
369 static void nvme_prepare_devid(nvme_t *, uint32_t);
370
371 static int nvme_open(dev_t *, int, int, cred_t *);
372 static int nvme_close(dev_t, int, int, cred_t *);
373 static int nvme_ioctl(dev_t, int, intptr_t, int, cred_t *, int *);
374
375 #define NVME_MINOR_INST_SHIFT 9
376 #define NVME_MINOR(inst, nsid) (((inst) << NVME_MINOR_INST_SHIFT) | (nsid))
377 #define NVME_MINOR_INST(minor) ((minor) >> NVME_MINOR_INST_SHIFT)
378 #define NVME_MINOR_NSID(minor) ((minor) & ((1 << NVME_MINOR_INST_SHIFT) - 1))
379 #define NVME_MINOR_MAX (NVME_MINOR(1, 0) - 2)
380
381 static void *nvme_state;
382 static kmem_cache_t *nvme_cmd_cache;
383
384 /*
385 * DMA attributes for queue DMA memory
386 *
387 * Queue DMA memory must be page aligned. The maximum length of a queue is
388 * 65536 entries, and an entry can be 64 bytes long.
389 */
390 static ddi_dma_attr_t nvme_queue_dma_attr = {
391 .dma_attr_version = DMA_ATTR_V0,
392 .dma_attr_addr_lo = 0,
393 .dma_attr_addr_hi = 0xffffffffffffffffULL,
394 .dma_attr_count_max = (UINT16_MAX + 1) * sizeof (nvme_sqe_t) - 1,
395 .dma_attr_align = 0x1000,
396 .dma_attr_burstsizes = 0x7ff,
397 .dma_attr_minxfer = 0x1000,
398 .dma_attr_maxxfer = (UINT16_MAX + 1) * sizeof (nvme_sqe_t),
399 .dma_attr_seg = 0xffffffffffffffffULL,
400 .dma_attr_sgllen = 1,
401 .dma_attr_granular = 1,
402 .dma_attr_flags = 0,
403 };
404
405 /*
406 * DMA attributes for transfers using Physical Region Page (PRP) entries
407 *
408 * A PRP entry describes one page of DMA memory using the page size specified
409 * in the controller configuration's memory page size register (CC.MPS). It uses
410 * a 64bit base address aligned to this page size. There is no limitation on
411 * chaining PRPs together for arbitrarily large DMA transfers.
412 */
413 static ddi_dma_attr_t nvme_prp_dma_attr = {
414 .dma_attr_version = DMA_ATTR_V0,
415 .dma_attr_addr_lo = 0,
416 .dma_attr_addr_hi = 0xffffffffffffffffULL,
417 .dma_attr_count_max = 0xfff,
418 .dma_attr_align = 0x1000,
419 .dma_attr_burstsizes = 0x7ff,
420 .dma_attr_minxfer = 0x1000,
421 .dma_attr_maxxfer = 0x1000,
422 .dma_attr_seg = 0xfff,
423 .dma_attr_sgllen = -1,
424 .dma_attr_granular = 1,
425 .dma_attr_flags = 0,
426 };
427
428 /*
429 * DMA attributes for transfers using scatter/gather lists
430 *
431 * A SGL entry describes a chunk of DMA memory using a 64bit base address and a
432 * 32bit length field. SGL Segment and SGL Last Segment entries require the
433 * length to be a multiple of 16 bytes.
434 */
435 static ddi_dma_attr_t nvme_sgl_dma_attr = {
436 .dma_attr_version = DMA_ATTR_V0,
437 .dma_attr_addr_lo = 0,
438 .dma_attr_addr_hi = 0xffffffffffffffffULL,
439 .dma_attr_count_max = 0xffffffffUL,
440 .dma_attr_align = 1,
441 .dma_attr_burstsizes = 0x7ff,
442 .dma_attr_minxfer = 0x10,
443 .dma_attr_maxxfer = 0xfffffffffULL,
444 .dma_attr_seg = 0xffffffffffffffffULL,
445 .dma_attr_sgllen = -1,
446 .dma_attr_granular = 0x10,
447 .dma_attr_flags = 0
448 };
449
450 static ddi_device_acc_attr_t nvme_reg_acc_attr = {
451 .devacc_attr_version = DDI_DEVICE_ATTR_V0,
452 .devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC,
453 .devacc_attr_dataorder = DDI_STRICTORDER_ACC
454 };
455
456 static struct cb_ops nvme_cb_ops = {
457 .cb_open = nvme_open,
458 .cb_close = nvme_close,
459 .cb_strategy = nodev,
460 .cb_print = nodev,
461 .cb_dump = nodev,
462 .cb_read = nodev,
463 .cb_write = nodev,
464 .cb_ioctl = nvme_ioctl,
465 .cb_devmap = nodev,
466 .cb_mmap = nodev,
467 .cb_segmap = nodev,
468 .cb_chpoll = nochpoll,
469 .cb_prop_op = ddi_prop_op,
470 .cb_str = 0,
471 .cb_flag = D_NEW | D_MP,
472 .cb_rev = CB_REV,
473 .cb_aread = nodev,
474 .cb_awrite = nodev
475 };
476
477 static struct dev_ops nvme_dev_ops = {
478 .devo_rev = DEVO_REV,
479 .devo_refcnt = 0,
480 .devo_getinfo = ddi_no_info,
481 .devo_identify = nulldev,
482 .devo_probe = nulldev,
483 .devo_attach = nvme_attach,
484 .devo_detach = nvme_detach,
485 .devo_reset = nodev,
486 .devo_cb_ops = &nvme_cb_ops,
487 .devo_bus_ops = NULL,
488 .devo_power = NULL,
489 .devo_quiesce = nvme_quiesce,
490 };
491
492 static struct modldrv nvme_modldrv = {
493 .drv_modops = &mod_driverops,
494 .drv_linkinfo = "NVMe v1.1b",
495 .drv_dev_ops = &nvme_dev_ops
496 };
497
498 static struct modlinkage nvme_modlinkage = {
499 .ml_rev = MODREV_1,
500 .ml_linkage = { &nvme_modldrv, NULL }
501 };
502
503 static bd_ops_t nvme_bd_ops = {
504 .o_version = BD_OPS_VERSION_0,
505 .o_drive_info = nvme_bd_driveinfo,
506 .o_media_info = nvme_bd_mediainfo,
507 .o_devid_init = nvme_bd_devid,
508 .o_sync_cache = nvme_bd_sync,
509 .o_read = nvme_bd_read,
510 .o_write = nvme_bd_write,
511 };
512
513 /*
514 * This list will hold commands that have timed out and couldn't be aborted.
515 * As we don't know what the hardware may still do with the DMA memory we can't
516 * free them, so we'll keep them forever on this list where we can easily look
517 * at them with mdb.
518 */
519 static struct list nvme_lost_cmds;
520 static kmutex_t nvme_lc_mutex;
521
522 int
523 _init(void)
524 {
525 int error;
526
527 error = ddi_soft_state_init(&nvme_state, sizeof (nvme_t), 1);
528 if (error != DDI_SUCCESS)
529 return (error);
530
531 nvme_cmd_cache = kmem_cache_create("nvme_cmd_cache",
532 sizeof (nvme_cmd_t), 64, NULL, NULL, NULL, NULL, NULL, 0);
533
534 mutex_init(&nvme_lc_mutex, NULL, MUTEX_DRIVER, NULL);
535 list_create(&nvme_lost_cmds, sizeof (nvme_cmd_t),
536 offsetof(nvme_cmd_t, nc_list));
537
538 bd_mod_init(&nvme_dev_ops);
539
540 error = mod_install(&nvme_modlinkage);
541 if (error != DDI_SUCCESS) {
542 ddi_soft_state_fini(&nvme_state);
543 mutex_destroy(&nvme_lc_mutex);
544 list_destroy(&nvme_lost_cmds);
545 bd_mod_fini(&nvme_dev_ops);
546 }
547
548 return (error);
549 }
550
551 int
552 _fini(void)
553 {
554 int error;
555
556 if (!list_is_empty(&nvme_lost_cmds))
557 return (DDI_FAILURE);
558
559 error = mod_remove(&nvme_modlinkage);
560 if (error == DDI_SUCCESS) {
561 ddi_soft_state_fini(&nvme_state);
562 kmem_cache_destroy(nvme_cmd_cache);
563 mutex_destroy(&nvme_lc_mutex);
564 list_destroy(&nvme_lost_cmds);
565 bd_mod_fini(&nvme_dev_ops);
566 }
567
568 return (error);
569 }
570
571 int
572 _info(struct modinfo *modinfop)
573 {
574 return (mod_info(&nvme_modlinkage, modinfop));
575 }
576
577 static inline void
578 nvme_put64(nvme_t *nvme, uintptr_t reg, uint64_t val)
579 {
580 ASSERT(((uintptr_t)(nvme->n_regs + reg) & 0x7) == 0);
581
582 /*LINTED: E_BAD_PTR_CAST_ALIGN*/
583 ddi_put64(nvme->n_regh, (uint64_t *)(nvme->n_regs + reg), val);
584 }
585
586 static inline void
587 nvme_put32(nvme_t *nvme, uintptr_t reg, uint32_t val)
588 {
589 ASSERT(((uintptr_t)(nvme->n_regs + reg) & 0x3) == 0);
590
591 /*LINTED: E_BAD_PTR_CAST_ALIGN*/
592 ddi_put32(nvme->n_regh, (uint32_t *)(nvme->n_regs + reg), val);
593 }
594
595 static inline uint64_t
596 nvme_get64(nvme_t *nvme, uintptr_t reg)
597 {
598 uint64_t val;
599
600 ASSERT(((uintptr_t)(nvme->n_regs + reg) & 0x7) == 0);
601
602 /*LINTED: E_BAD_PTR_CAST_ALIGN*/
603 val = ddi_get64(nvme->n_regh, (uint64_t *)(nvme->n_regs + reg));
604
605 return (val);
606 }
607
608 static inline uint32_t
609 nvme_get32(nvme_t *nvme, uintptr_t reg)
610 {
611 uint32_t val;
612
613 ASSERT(((uintptr_t)(nvme->n_regs + reg) & 0x3) == 0);
614
615 /*LINTED: E_BAD_PTR_CAST_ALIGN*/
616 val = ddi_get32(nvme->n_regh, (uint32_t *)(nvme->n_regs + reg));
617
618 return (val);
619 }
620
621 static boolean_t
622 nvme_check_regs_hdl(nvme_t *nvme)
623 {
624 ddi_fm_error_t error;
625
626 ddi_fm_acc_err_get(nvme->n_regh, &error, DDI_FME_VERSION);
627
628 if (error.fme_status != DDI_FM_OK)
629 return (B_TRUE);
630
631 return (B_FALSE);
632 }
633
634 static boolean_t
635 nvme_check_dma_hdl(nvme_dma_t *dma)
636 {
637 ddi_fm_error_t error;
638
639 if (dma == NULL)
640 return (B_FALSE);
641
642 ddi_fm_dma_err_get(dma->nd_dmah, &error, DDI_FME_VERSION);
643
644 if (error.fme_status != DDI_FM_OK)
645 return (B_TRUE);
646
647 return (B_FALSE);
648 }
649
650 static void
651 nvme_free_dma_common(nvme_dma_t *dma)
652 {
653 if (dma->nd_dmah != NULL)
654 (void) ddi_dma_unbind_handle(dma->nd_dmah);
655 if (dma->nd_acch != NULL)
656 ddi_dma_mem_free(&dma->nd_acch);
657 if (dma->nd_dmah != NULL)
658 ddi_dma_free_handle(&dma->nd_dmah);
659 }
660
661 static void
662 nvme_free_dma(nvme_dma_t *dma)
663 {
664 nvme_free_dma_common(dma);
665 kmem_free(dma, sizeof (*dma));
666 }
667
668 /* ARGSUSED */
669 static void
670 nvme_prp_dma_destructor(void *buf, void *private)
671 {
672 nvme_dma_t *dma = (nvme_dma_t *)buf;
673
674 nvme_free_dma_common(dma);
675 }
676
677 static int
678 nvme_alloc_dma_common(nvme_t *nvme, nvme_dma_t *dma,
679 size_t len, uint_t flags, ddi_dma_attr_t *dma_attr)
680 {
681 if (ddi_dma_alloc_handle(nvme->n_dip, dma_attr, DDI_DMA_SLEEP, NULL,
682 &dma->nd_dmah) != DDI_SUCCESS) {
683 /*
684 * Due to DDI_DMA_SLEEP this can't be DDI_DMA_NORESOURCES, and
685 * the only other possible error is DDI_DMA_BADATTR which
686 * indicates a driver bug which should cause a panic.
687 */
688 dev_err(nvme->n_dip, CE_PANIC,
689 "!failed to get DMA handle, check DMA attributes");
690 return (DDI_FAILURE);
691 }
692
693 /*
694 * ddi_dma_mem_alloc() can only fail when DDI_DMA_NOSLEEP is specified
695 * or the flags are conflicting, which isn't the case here.
696 */
697 (void) ddi_dma_mem_alloc(dma->nd_dmah, len, &nvme->n_reg_acc_attr,
698 DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, NULL, &dma->nd_memp,
699 &dma->nd_len, &dma->nd_acch);
700
701 if (ddi_dma_addr_bind_handle(dma->nd_dmah, NULL, dma->nd_memp,
702 dma->nd_len, flags | DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, NULL,
703 &dma->nd_cookie, &dma->nd_ncookie) != DDI_DMA_MAPPED) {
704 dev_err(nvme->n_dip, CE_WARN,
705 "!failed to bind DMA memory");
706 atomic_inc_32(&nvme->n_dma_bind_err);
707 nvme_free_dma_common(dma);
708 return (DDI_FAILURE);
709 }
710
711 return (DDI_SUCCESS);
712 }
713
714 static int
715 nvme_zalloc_dma(nvme_t *nvme, size_t len, uint_t flags,
716 ddi_dma_attr_t *dma_attr, nvme_dma_t **ret)
717 {
718 nvme_dma_t *dma = kmem_zalloc(sizeof (nvme_dma_t), KM_SLEEP);
719
720 if (nvme_alloc_dma_common(nvme, dma, len, flags, dma_attr) !=
721 DDI_SUCCESS) {
722 *ret = NULL;
723 kmem_free(dma, sizeof (nvme_dma_t));
724 return (DDI_FAILURE);
725 }
726
727 bzero(dma->nd_memp, dma->nd_len);
728
729 *ret = dma;
730 return (DDI_SUCCESS);
731 }
732
733 /* ARGSUSED */
734 static int
735 nvme_prp_dma_constructor(void *buf, void *private, int flags)
736 {
737 nvme_dma_t *dma = (nvme_dma_t *)buf;
738 nvme_t *nvme = (nvme_t *)private;
739
740 dma->nd_dmah = NULL;
741 dma->nd_acch = NULL;
742
743 if (nvme_alloc_dma_common(nvme, dma, nvme->n_pagesize,
744 DDI_DMA_READ, &nvme->n_prp_dma_attr) != DDI_SUCCESS) {
745 return (-1);
746 }
747
748 ASSERT(dma->nd_ncookie == 1);
749
750 dma->nd_cached = B_TRUE;
751
752 return (0);
753 }
754
755 static int
756 nvme_zalloc_queue_dma(nvme_t *nvme, uint32_t nentry, uint16_t qe_len,
757 uint_t flags, nvme_dma_t **dma)
758 {
759 uint32_t len = nentry * qe_len;
760 ddi_dma_attr_t q_dma_attr = nvme->n_queue_dma_attr;
761
762 len = roundup(len, nvme->n_pagesize);
763
764 q_dma_attr.dma_attr_minxfer = len;
765
766 if (nvme_zalloc_dma(nvme, len, flags, &q_dma_attr, dma)
767 != DDI_SUCCESS) {
768 dev_err(nvme->n_dip, CE_WARN,
769 "!failed to get DMA memory for queue");
770 goto fail;
771 }
772
773 if ((*dma)->nd_ncookie != 1) {
774 dev_err(nvme->n_dip, CE_WARN,
775 "!got too many cookies for queue DMA");
776 goto fail;
777 }
778
779 return (DDI_SUCCESS);
780
781 fail:
782 if (*dma) {
783 nvme_free_dma(*dma);
784 *dma = NULL;
785 }
786
787 return (DDI_FAILURE);
788 }
789
790 static void
791 nvme_free_qpair(nvme_qpair_t *qp)
792 {
793 int i;
794
795 mutex_destroy(&qp->nq_mutex);
796 sema_destroy(&qp->nq_sema);
797
798 if (qp->nq_sqdma != NULL)
799 nvme_free_dma(qp->nq_sqdma);
800 if (qp->nq_cqdma != NULL)
801 nvme_free_dma(qp->nq_cqdma);
802
803 if (qp->nq_active_cmds > 0)
804 for (i = 0; i != qp->nq_nentry; i++)
805 if (qp->nq_cmd[i] != NULL)
806 nvme_free_cmd(qp->nq_cmd[i]);
807
808 if (qp->nq_cmd != NULL)
809 kmem_free(qp->nq_cmd, sizeof (nvme_cmd_t *) * qp->nq_nentry);
810
811 kmem_free(qp, sizeof (nvme_qpair_t));
812 }
813
814 static int
815 nvme_alloc_qpair(nvme_t *nvme, uint32_t nentry, nvme_qpair_t **nqp,
816 int idx)
817 {
818 nvme_qpair_t *qp = kmem_zalloc(sizeof (*qp), KM_SLEEP);
819
820 mutex_init(&qp->nq_mutex, NULL, MUTEX_DRIVER,
821 DDI_INTR_PRI(nvme->n_intr_pri));
822 sema_init(&qp->nq_sema, nentry, NULL, SEMA_DRIVER, NULL);
823
824 if (nvme_zalloc_queue_dma(nvme, nentry, sizeof (nvme_sqe_t),
825 DDI_DMA_WRITE, &qp->nq_sqdma) != DDI_SUCCESS)
826 goto fail;
827
828 if (nvme_zalloc_queue_dma(nvme, nentry, sizeof (nvme_cqe_t),
829 DDI_DMA_READ, &qp->nq_cqdma) != DDI_SUCCESS)
830 goto fail;
831
832 qp->nq_sq = (nvme_sqe_t *)qp->nq_sqdma->nd_memp;
833 qp->nq_cq = (nvme_cqe_t *)qp->nq_cqdma->nd_memp;
834 qp->nq_nentry = nentry;
835
836 qp->nq_sqtdbl = NVME_REG_SQTDBL(nvme, idx);
837 qp->nq_cqhdbl = NVME_REG_CQHDBL(nvme, idx);
838
839 qp->nq_cmd = kmem_zalloc(sizeof (nvme_cmd_t *) * nentry, KM_SLEEP);
840 qp->nq_next_cmd = 0;
841
842 *nqp = qp;
843 return (DDI_SUCCESS);
844
845 fail:
846 nvme_free_qpair(qp);
847 *nqp = NULL;
848
849 return (DDI_FAILURE);
850 }
851
852 static nvme_cmd_t *
853 nvme_alloc_cmd(nvme_t *nvme, int kmflag)
854 {
855 nvme_cmd_t *cmd = kmem_cache_alloc(nvme_cmd_cache, kmflag);
856
857 if (cmd == NULL)
858 return (cmd);
859
860 bzero(cmd, sizeof (nvme_cmd_t));
861
862 cmd->nc_nvme = nvme;
863
864 mutex_init(&cmd->nc_mutex, NULL, MUTEX_DRIVER,
865 DDI_INTR_PRI(nvme->n_intr_pri));
866 cv_init(&cmd->nc_cv, NULL, CV_DRIVER, NULL);
867
868 return (cmd);
869 }
870
871 static void
872 nvme_free_cmd(nvme_cmd_t *cmd)
873 {
874 /* Don't free commands on the lost commands list. */
875 if (list_link_active(&cmd->nc_list))
876 return;
877
878 if (cmd->nc_dma) {
879 if (cmd->nc_dma->nd_cached)
880 kmem_cache_free(cmd->nc_nvme->n_prp_cache,
881 cmd->nc_dma);
882 else
883 nvme_free_dma(cmd->nc_dma);
884 cmd->nc_dma = NULL;
885 }
886
887 cv_destroy(&cmd->nc_cv);
888 mutex_destroy(&cmd->nc_mutex);
889
890 kmem_cache_free(nvme_cmd_cache, cmd);
891 }
892
893 static void
894 nvme_submit_admin_cmd(nvme_qpair_t *qp, nvme_cmd_t *cmd)
895 {
896 sema_p(&qp->nq_sema);
897 nvme_submit_cmd_common(qp, cmd);
898 }
899
900 static int
901 nvme_submit_io_cmd(nvme_qpair_t *qp, nvme_cmd_t *cmd)
902 {
903 if (sema_tryp(&qp->nq_sema) == 0)
904 return (EAGAIN);
905
906 nvme_submit_cmd_common(qp, cmd);
907 return (0);
908 }
909
910 static void
911 nvme_submit_cmd_common(nvme_qpair_t *qp, nvme_cmd_t *cmd)
912 {
913 nvme_reg_sqtdbl_t tail = { 0 };
914
915 mutex_enter(&qp->nq_mutex);
916 cmd->nc_completed = B_FALSE;
917
918 /*
919 * Try to insert the cmd into the active cmd array at the nq_next_cmd
920 * slot. If the slot is already occupied advance to the next slot and
921 * try again. This can happen for long running commands like async event
922 * requests.
923 */
924 while (qp->nq_cmd[qp->nq_next_cmd] != NULL)
925 qp->nq_next_cmd = (qp->nq_next_cmd + 1) % qp->nq_nentry;
926 qp->nq_cmd[qp->nq_next_cmd] = cmd;
927
928 qp->nq_active_cmds++;
929
930 cmd->nc_sqe.sqe_cid = qp->nq_next_cmd;
931 bcopy(&cmd->nc_sqe, &qp->nq_sq[qp->nq_sqtail], sizeof (nvme_sqe_t));
932 (void) ddi_dma_sync(qp->nq_sqdma->nd_dmah,
933 sizeof (nvme_sqe_t) * qp->nq_sqtail,
934 sizeof (nvme_sqe_t), DDI_DMA_SYNC_FORDEV);
935 qp->nq_next_cmd = (qp->nq_next_cmd + 1) % qp->nq_nentry;
936
937 tail.b.sqtdbl_sqt = qp->nq_sqtail = (qp->nq_sqtail + 1) % qp->nq_nentry;
938 nvme_put32(cmd->nc_nvme, qp->nq_sqtdbl, tail.r);
939
940 mutex_exit(&qp->nq_mutex);
941 }
942
943 static nvme_cmd_t *
944 nvme_unqueue_cmd(nvme_t *nvme, nvme_qpair_t *qp, int cid)
945 {
946 nvme_cmd_t *cmd;
947
948 ASSERT(mutex_owned(&qp->nq_mutex));
949 ASSERT3S(cid, <, qp->nq_nentry);
950
951 cmd = qp->nq_cmd[cid];
952 qp->nq_cmd[cid] = NULL;
953 ASSERT3U(qp->nq_active_cmds, >, 0);
954 qp->nq_active_cmds--;
955 sema_v(&qp->nq_sema);
956
957 ASSERT3P(cmd, !=, NULL);
958 ASSERT3P(cmd->nc_nvme, ==, nvme);
959 ASSERT3S(cmd->nc_sqe.sqe_cid, ==, cid);
960
961 return (cmd);
962 }
963
964 static nvme_cmd_t *
965 nvme_retrieve_cmd(nvme_t *nvme, nvme_qpair_t *qp)
966 {
967 nvme_reg_cqhdbl_t head = { 0 };
968
969 nvme_cqe_t *cqe;
970 nvme_cmd_t *cmd;
971
972 (void) ddi_dma_sync(qp->nq_cqdma->nd_dmah, 0,
973 sizeof (nvme_cqe_t) * qp->nq_nentry, DDI_DMA_SYNC_FORKERNEL);
974
975 mutex_enter(&qp->nq_mutex);
976 cqe = &qp->nq_cq[qp->nq_cqhead];
977
978 /* Check phase tag of CQE. Hardware inverts it for new entries. */
979 if (cqe->cqe_sf.sf_p == qp->nq_phase) {
980 mutex_exit(&qp->nq_mutex);
981 return (NULL);
982 }
983
984 ASSERT(nvme->n_ioq[cqe->cqe_sqid] == qp);
985
986 cmd = nvme_unqueue_cmd(nvme, qp, cqe->cqe_cid);
987
988 ASSERT(cmd->nc_sqid == cqe->cqe_sqid);
989 bcopy(cqe, &cmd->nc_cqe, sizeof (nvme_cqe_t));
990
991 qp->nq_sqhead = cqe->cqe_sqhd;
992
993 head.b.cqhdbl_cqh = qp->nq_cqhead = (qp->nq_cqhead + 1) % qp->nq_nentry;
994
995 /* Toggle phase on wrap-around. */
996 if (qp->nq_cqhead == 0)
997 qp->nq_phase = qp->nq_phase ? 0 : 1;
998
999 nvme_put32(cmd->nc_nvme, qp->nq_cqhdbl, head.r);
1000 mutex_exit(&qp->nq_mutex);
1001
1002 return (cmd);
1003 }
1004
1005 static int
1006 nvme_check_unknown_cmd_status(nvme_cmd_t *cmd)
1007 {
1008 nvme_cqe_t *cqe = &cmd->nc_cqe;
1009
1010 dev_err(cmd->nc_nvme->n_dip, CE_WARN,
1011 "!unknown command status received: opc = %x, sqid = %d, cid = %d, "
1012 "sc = %x, sct = %x, dnr = %d, m = %d", cmd->nc_sqe.sqe_opc,
1013 cqe->cqe_sqid, cqe->cqe_cid, cqe->cqe_sf.sf_sc, cqe->cqe_sf.sf_sct,
1014 cqe->cqe_sf.sf_dnr, cqe->cqe_sf.sf_m);
1015
1016 if (cmd->nc_xfer != NULL)
1017 bd_error(cmd->nc_xfer, BD_ERR_ILLRQ);
1018
1019 if (cmd->nc_nvme->n_strict_version) {
1020 cmd->nc_nvme->n_dead = B_TRUE;
1021 ddi_fm_service_impact(cmd->nc_nvme->n_dip, DDI_SERVICE_LOST);
1022 }
1023
1024 return (EIO);
1025 }
1026
1027 static int
1028 nvme_check_vendor_cmd_status(nvme_cmd_t *cmd)
1029 {
1030 nvme_cqe_t *cqe = &cmd->nc_cqe;
1031
1032 dev_err(cmd->nc_nvme->n_dip, CE_WARN,
1033 "!unknown command status received: opc = %x, sqid = %d, cid = %d, "
1034 "sc = %x, sct = %x, dnr = %d, m = %d", cmd->nc_sqe.sqe_opc,
1035 cqe->cqe_sqid, cqe->cqe_cid, cqe->cqe_sf.sf_sc, cqe->cqe_sf.sf_sct,
1036 cqe->cqe_sf.sf_dnr, cqe->cqe_sf.sf_m);
1037 if (!cmd->nc_nvme->n_ignore_unknown_vendor_status) {
1038 cmd->nc_nvme->n_dead = B_TRUE;
1039 ddi_fm_service_impact(cmd->nc_nvme->n_dip, DDI_SERVICE_LOST);
1040 }
1041
1042 return (EIO);
1043 }
1044
1045 static int
1046 nvme_check_integrity_cmd_status(nvme_cmd_t *cmd)
1047 {
1048 nvme_cqe_t *cqe = &cmd->nc_cqe;
1049
1050 switch (cqe->cqe_sf.sf_sc) {
1051 case NVME_CQE_SC_INT_NVM_WRITE:
1052 /* write fail */
1053 /* TODO: post ereport */
1054 if (cmd->nc_xfer != NULL)
1055 bd_error(cmd->nc_xfer, BD_ERR_MEDIA);
1056 return (EIO);
1057
1058 case NVME_CQE_SC_INT_NVM_READ:
1059 /* read fail */
1060 /* TODO: post ereport */
1061 if (cmd->nc_xfer != NULL)
1062 bd_error(cmd->nc_xfer, BD_ERR_MEDIA);
1063 return (EIO);
1064
1065 default:
1066 return (nvme_check_unknown_cmd_status(cmd));
1067 }
1068 }
1069
1070 static int
1071 nvme_check_generic_cmd_status(nvme_cmd_t *cmd)
1072 {
1073 nvme_cqe_t *cqe = &cmd->nc_cqe;
1074
1075 switch (cqe->cqe_sf.sf_sc) {
1076 case NVME_CQE_SC_GEN_SUCCESS:
1077 return (0);
1078
1079 /*
1080 * Errors indicating a bug in the driver should cause a panic.
1081 */
1082 case NVME_CQE_SC_GEN_INV_OPC:
1083 /* Invalid Command Opcode */
1084 if (!cmd->nc_dontpanic)
1085 dev_err(cmd->nc_nvme->n_dip, CE_PANIC,
1086 "programming error: invalid opcode in cmd %p",
1087 (void *)cmd);
1088 return (EINVAL);
1089
1090 case NVME_CQE_SC_GEN_INV_FLD:
1091 /* Invalid Field in Command */
1092 if (!cmd->nc_dontpanic)
1093 dev_err(cmd->nc_nvme->n_dip, CE_PANIC,
1094 "programming error: invalid field in cmd %p",
1095 (void *)cmd);
1096 return (EIO);
1097
1098 case NVME_CQE_SC_GEN_ID_CNFL:
1099 /* Command ID Conflict */
1100 dev_err(cmd->nc_nvme->n_dip, CE_PANIC, "programming error: "
1101 "cmd ID conflict in cmd %p", (void *)cmd);
1102 return (0);
1103
1104 case NVME_CQE_SC_GEN_INV_NS:
1105 /* Invalid Namespace or Format */
1106 if (!cmd->nc_dontpanic)
1107 dev_err(cmd->nc_nvme->n_dip, CE_PANIC,
1108 "programming error: invalid NS/format in cmd %p",
1109 (void *)cmd);
1110 return (EINVAL);
1111
1112 case NVME_CQE_SC_GEN_NVM_LBA_RANGE:
1113 /* LBA Out Of Range */
1114 dev_err(cmd->nc_nvme->n_dip, CE_PANIC, "programming error: "
1115 "LBA out of range in cmd %p", (void *)cmd);
1116 return (0);
1117
1118 /*
1119 * Non-fatal errors, handle gracefully.
1120 */
1121 case NVME_CQE_SC_GEN_DATA_XFR_ERR:
1122 /* Data Transfer Error (DMA) */
1123 /* TODO: post ereport */
1124 atomic_inc_32(&cmd->nc_nvme->n_data_xfr_err);
1125 if (cmd->nc_xfer != NULL)
1126 bd_error(cmd->nc_xfer, BD_ERR_NTRDY);
1127 return (EIO);
1128
1129 case NVME_CQE_SC_GEN_INTERNAL_ERR:
1130 /*
1131 * Internal Error. The spec (v1.0, section 4.5.1.2) says
1132 * detailed error information is returned as async event,
1133 * so we pretty much ignore the error here and handle it
1134 * in the async event handler.
1135 */
1136 atomic_inc_32(&cmd->nc_nvme->n_internal_err);
1137 if (cmd->nc_xfer != NULL)
1138 bd_error(cmd->nc_xfer, BD_ERR_NTRDY);
1139 return (EIO);
1140
1141 case NVME_CQE_SC_GEN_ABORT_REQUEST:
1142 /*
1143 * Command Abort Requested. This normally happens only when a
1144 * command times out.
1145 */
1146 /* TODO: post ereport or change blkdev to handle this? */
1147 atomic_inc_32(&cmd->nc_nvme->n_abort_rq_err);
1148 return (ECANCELED);
1149
1150 case NVME_CQE_SC_GEN_ABORT_PWRLOSS:
1151 /* Command Aborted due to Power Loss Notification */
1152 ddi_fm_service_impact(cmd->nc_nvme->n_dip, DDI_SERVICE_LOST);
1153 cmd->nc_nvme->n_dead = B_TRUE;
1154 return (EIO);
1155
1156 case NVME_CQE_SC_GEN_ABORT_SQ_DEL:
1157 /* Command Aborted due to SQ Deletion */
1158 atomic_inc_32(&cmd->nc_nvme->n_abort_sq_del);
1159 return (EIO);
1160
1161 case NVME_CQE_SC_GEN_NVM_CAP_EXC:
1162 /* Capacity Exceeded */
1163 atomic_inc_32(&cmd->nc_nvme->n_nvm_cap_exc);
1164 if (cmd->nc_xfer != NULL)
1165 bd_error(cmd->nc_xfer, BD_ERR_MEDIA);
1166 return (EIO);
1167
1168 case NVME_CQE_SC_GEN_NVM_NS_NOTRDY:
1169 /* Namespace Not Ready */
1170 atomic_inc_32(&cmd->nc_nvme->n_nvm_ns_notrdy);
1171 if (cmd->nc_xfer != NULL)
1172 bd_error(cmd->nc_xfer, BD_ERR_NTRDY);
1173 return (EIO);
1174
1175 default:
1176 return (nvme_check_unknown_cmd_status(cmd));
1177 }
1178 }
1179
1180 static int
1181 nvme_check_specific_cmd_status(nvme_cmd_t *cmd)
1182 {
1183 nvme_cqe_t *cqe = &cmd->nc_cqe;
1184
1185 switch (cqe->cqe_sf.sf_sc) {
1186 case NVME_CQE_SC_SPC_INV_CQ:
1187 /* Completion Queue Invalid */
1188 ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_CREATE_SQUEUE);
1189 atomic_inc_32(&cmd->nc_nvme->n_inv_cq_err);
1190 return (EINVAL);
1191
1192 case NVME_CQE_SC_SPC_INV_QID:
1193 /* Invalid Queue Identifier */
1194 ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_CREATE_SQUEUE ||
1195 cmd->nc_sqe.sqe_opc == NVME_OPC_DELETE_SQUEUE ||
1196 cmd->nc_sqe.sqe_opc == NVME_OPC_CREATE_CQUEUE ||
1197 cmd->nc_sqe.sqe_opc == NVME_OPC_DELETE_CQUEUE);
1198 atomic_inc_32(&cmd->nc_nvme->n_inv_qid_err);
1199 return (EINVAL);
1200
1201 case NVME_CQE_SC_SPC_MAX_QSZ_EXC:
1202 /* Max Queue Size Exceeded */
1203 ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_CREATE_SQUEUE ||
1204 cmd->nc_sqe.sqe_opc == NVME_OPC_CREATE_CQUEUE);
1205 atomic_inc_32(&cmd->nc_nvme->n_max_qsz_exc);
1206 return (EINVAL);
1207
1208 case NVME_CQE_SC_SPC_ABRT_CMD_EXC:
1209 /* Abort Command Limit Exceeded */
1210 ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_ABORT);
1211 dev_err(cmd->nc_nvme->n_dip, CE_PANIC, "programming error: "
1212 "abort command limit exceeded in cmd %p", (void *)cmd);
1213 return (0);
1214
1215 case NVME_CQE_SC_SPC_ASYNC_EVREQ_EXC:
1216 /* Async Event Request Limit Exceeded */
1217 ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_ASYNC_EVENT);
1218 dev_err(cmd->nc_nvme->n_dip, CE_PANIC, "programming error: "
1219 "async event request limit exceeded in cmd %p",
1220 (void *)cmd);
1221 return (0);
1222
1223 case NVME_CQE_SC_SPC_INV_INT_VECT:
1224 /* Invalid Interrupt Vector */
1225 ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_CREATE_CQUEUE);
1226 atomic_inc_32(&cmd->nc_nvme->n_inv_int_vect);
1227 return (EINVAL);
1228
1229 case NVME_CQE_SC_SPC_INV_LOG_PAGE:
1230 /* Invalid Log Page */
1231 ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_GET_LOG_PAGE);
1232 atomic_inc_32(&cmd->nc_nvme->n_inv_log_page);
1233 return (EINVAL);
1234
1235 case NVME_CQE_SC_SPC_INV_FORMAT:
1236 /* Invalid Format */
1237 ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_NVM_FORMAT);
1238 atomic_inc_32(&cmd->nc_nvme->n_inv_format);
1239 if (cmd->nc_xfer != NULL)
1240 bd_error(cmd->nc_xfer, BD_ERR_ILLRQ);
1241 return (EINVAL);
1242
1243 case NVME_CQE_SC_SPC_INV_Q_DEL:
1244 /* Invalid Queue Deletion */
1245 ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_DELETE_CQUEUE);
1246 atomic_inc_32(&cmd->nc_nvme->n_inv_q_del);
1247 return (EINVAL);
1248
1249 case NVME_CQE_SC_SPC_NVM_CNFL_ATTR:
1250 /* Conflicting Attributes */
1251 ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_NVM_DSET_MGMT ||
1252 cmd->nc_sqe.sqe_opc == NVME_OPC_NVM_READ ||
1253 cmd->nc_sqe.sqe_opc == NVME_OPC_NVM_WRITE);
1254 atomic_inc_32(&cmd->nc_nvme->n_cnfl_attr);
1255 if (cmd->nc_xfer != NULL)
1256 bd_error(cmd->nc_xfer, BD_ERR_ILLRQ);
1257 return (EINVAL);
1258
1259 case NVME_CQE_SC_SPC_NVM_INV_PROT:
1260 /* Invalid Protection Information */
1261 ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_NVM_COMPARE ||
1262 cmd->nc_sqe.sqe_opc == NVME_OPC_NVM_READ ||
1263 cmd->nc_sqe.sqe_opc == NVME_OPC_NVM_WRITE);
1264 atomic_inc_32(&cmd->nc_nvme->n_inv_prot);
1265 if (cmd->nc_xfer != NULL)
1266 bd_error(cmd->nc_xfer, BD_ERR_ILLRQ);
1267 return (EINVAL);
1268
1269 case NVME_CQE_SC_SPC_NVM_READONLY:
1270 /* Write to Read Only Range */
1271 ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_NVM_WRITE);
1272 atomic_inc_32(&cmd->nc_nvme->n_readonly);
1273 if (cmd->nc_xfer != NULL)
1274 bd_error(cmd->nc_xfer, BD_ERR_ILLRQ);
1275 return (EROFS);
1276
1277 default:
1278 return (nvme_check_unknown_cmd_status(cmd));
1279 }
1280 }
1281
1282 static inline int
1283 nvme_check_cmd_status(nvme_cmd_t *cmd)
1284 {
1285 nvme_cqe_t *cqe = &cmd->nc_cqe;
1286
1287 /*
1288 * Take a shortcut if the controller is dead, or if
1289 * command status indicates no error.
1290 */
1291 if (cmd->nc_nvme->n_dead)
1292 return (EIO);
1293
1294 if (cqe->cqe_sf.sf_sct == NVME_CQE_SCT_GENERIC &&
1295 cqe->cqe_sf.sf_sc == NVME_CQE_SC_GEN_SUCCESS)
1296 return (0);
1297
1298 if (cqe->cqe_sf.sf_sct == NVME_CQE_SCT_GENERIC)
1299 return (nvme_check_generic_cmd_status(cmd));
1300 else if (cqe->cqe_sf.sf_sct == NVME_CQE_SCT_SPECIFIC)
1301 return (nvme_check_specific_cmd_status(cmd));
1302 else if (cqe->cqe_sf.sf_sct == NVME_CQE_SCT_INTEGRITY)
1303 return (nvme_check_integrity_cmd_status(cmd));
1304 else if (cqe->cqe_sf.sf_sct == NVME_CQE_SCT_VENDOR)
1305 return (nvme_check_vendor_cmd_status(cmd));
1306
1307 return (nvme_check_unknown_cmd_status(cmd));
1308 }
1309
1310 static int
1311 nvme_abort_cmd(nvme_cmd_t *abort_cmd, uint_t sec)
1312 {
1313 nvme_t *nvme = abort_cmd->nc_nvme;
1314 nvme_cmd_t *cmd = nvme_alloc_cmd(nvme, KM_SLEEP);
1315 nvme_abort_cmd_t ac = { 0 };
1316 int ret = 0;
1317
1318 sema_p(&nvme->n_abort_sema);
1319
1320 ac.b.ac_cid = abort_cmd->nc_sqe.sqe_cid;
1321 ac.b.ac_sqid = abort_cmd->nc_sqid;
1322
1323 cmd->nc_sqid = 0;
1324 cmd->nc_sqe.sqe_opc = NVME_OPC_ABORT;
1325 cmd->nc_callback = nvme_wakeup_cmd;
1326 cmd->nc_sqe.sqe_cdw10 = ac.r;
1327
1328 /*
1329 * Send the ABORT to the hardware. The ABORT command will return _after_
1330 * the aborted command has completed (aborted or otherwise), but since
1331 * we still hold the aborted command's mutex its callback hasn't been
1332 * processed yet.
1333 */
1334 nvme_admin_cmd(cmd, sec);
1335 sema_v(&nvme->n_abort_sema);
1336
1337 if ((ret = nvme_check_cmd_status(cmd)) != 0) {
1338 dev_err(nvme->n_dip, CE_WARN,
1339 "!ABORT failed with sct = %x, sc = %x",
1340 cmd->nc_cqe.cqe_sf.sf_sct, cmd->nc_cqe.cqe_sf.sf_sc);
1341 atomic_inc_32(&nvme->n_abort_failed);
1342 } else {
1343 dev_err(nvme->n_dip, CE_WARN,
1344 "!ABORT of command %d/%d %ssuccessful",
1345 abort_cmd->nc_sqe.sqe_cid, abort_cmd->nc_sqid,
1346 cmd->nc_cqe.cqe_dw0 & 1 ? "un" : "");
1347 if ((cmd->nc_cqe.cqe_dw0 & 1) == 0)
1348 atomic_inc_32(&nvme->n_cmd_aborted);
1349 }
1350
1351 nvme_free_cmd(cmd);
1352 return (ret);
1353 }
1354
1355 /*
1356 * nvme_wait_cmd -- wait for command completion or timeout
1357 *
1358 * In case of a serious error or a timeout of the abort command the hardware
1359 * will be declared dead and FMA will be notified.
1360 */
1361 static void
1362 nvme_wait_cmd(nvme_cmd_t *cmd, uint_t sec)
1363 {
1364 clock_t timeout = ddi_get_lbolt() + drv_usectohz(sec * MICROSEC);
1365 nvme_t *nvme = cmd->nc_nvme;
1366 nvme_reg_csts_t csts;
1367 nvme_qpair_t *qp;
1368
1369 ASSERT(mutex_owned(&cmd->nc_mutex));
1370
1371 while (!cmd->nc_completed) {
1372 if (cv_timedwait(&cmd->nc_cv, &cmd->nc_mutex, timeout) == -1)
1373 break;
1374 }
1375
1376 if (cmd->nc_completed)
1377 return;
1378
1379 /*
1380 * The command timed out.
1381 *
1382 * Check controller for fatal status, any errors associated with the
1383 * register or DMA handle, or for a double timeout (abort command timed
1384 * out). If necessary log a warning and call FMA.
1385 */
1386 csts.r = nvme_get32(nvme, NVME_REG_CSTS);
1387 dev_err(nvme->n_dip, CE_WARN, "!command %d/%d timeout, "
1388 "OPC = %x, CFS = %d", cmd->nc_sqe.sqe_cid, cmd->nc_sqid,
1389 cmd->nc_sqe.sqe_opc, csts.b.csts_cfs);
1390 atomic_inc_32(&nvme->n_cmd_timeout);
1391
1392 if (csts.b.csts_cfs ||
1393 nvme_check_regs_hdl(nvme) ||
1394 nvme_check_dma_hdl(cmd->nc_dma) ||
1395 cmd->nc_sqe.sqe_opc == NVME_OPC_ABORT) {
1396 ddi_fm_service_impact(nvme->n_dip, DDI_SERVICE_LOST);
1397 nvme->n_dead = B_TRUE;
1398 } else if (nvme_abort_cmd(cmd, sec) == 0) {
1399 /*
1400 * If the abort succeeded the command should complete
1401 * immediately with an appropriate status.
1402 */
1403 while (!cmd->nc_completed)
1404 cv_wait(&cmd->nc_cv, &cmd->nc_mutex);
1405
1406 return;
1407 }
1408
1409 qp = nvme->n_ioq[cmd->nc_sqid];
1410
1411 mutex_enter(&qp->nq_mutex);
1412 (void) nvme_unqueue_cmd(nvme, qp, cmd->nc_sqe.sqe_cid);
1413 mutex_exit(&qp->nq_mutex);
1414
1415 /*
1416 * As we don't know what the presumed dead hardware might still do with
1417 * the DMA memory, we'll put the command on the lost commands list if it
1418 * has any DMA memory.
1419 */
1420 if (cmd->nc_dma != NULL) {
1421 mutex_enter(&nvme_lc_mutex);
1422 list_insert_head(&nvme_lost_cmds, cmd);
1423 mutex_exit(&nvme_lc_mutex);
1424 }
1425 }
1426
1427 static void
1428 nvme_wakeup_cmd(void *arg)
1429 {
1430 nvme_cmd_t *cmd = arg;
1431
1432 mutex_enter(&cmd->nc_mutex);
1433 cmd->nc_completed = B_TRUE;
1434 cv_signal(&cmd->nc_cv);
1435 mutex_exit(&cmd->nc_mutex);
1436 }
1437
1438 static void
1439 nvme_async_event_task(void *arg)
1440 {
1441 nvme_cmd_t *cmd = arg;
1442 nvme_t *nvme = cmd->nc_nvme;
1443 nvme_error_log_entry_t *error_log = NULL;
1444 nvme_health_log_t *health_log = NULL;
1445 size_t logsize = 0;
1446 nvme_async_event_t event;
1447
1448 /*
1449 * Check for errors associated with the async request itself. The only
1450 * command-specific error is "async event limit exceeded", which
1451 * indicates a programming error in the driver and causes a panic in
1452 * nvme_check_cmd_status().
1453 *
1454 * Other possible errors are various scenarios where the async request
1455 * was aborted, or internal errors in the device. Internal errors are
1456 * reported to FMA, the command aborts need no special handling here.
1457 *
1458 * And finally, at least qemu nvme does not support async events,
1459 * and will return NVME_CQE_SC_GEN_INV_OPC | DNR. If so, we
1460 * will avoid posting async events.
1461 */
1462
1463 if (nvme_check_cmd_status(cmd) != 0) {
1464 dev_err(cmd->nc_nvme->n_dip, CE_WARN,
1465 "!async event request returned failure, sct = %x, "
1466 "sc = %x, dnr = %d, m = %d", cmd->nc_cqe.cqe_sf.sf_sct,
1467 cmd->nc_cqe.cqe_sf.sf_sc, cmd->nc_cqe.cqe_sf.sf_dnr,
1468 cmd->nc_cqe.cqe_sf.sf_m);
1469
1470 if (cmd->nc_cqe.cqe_sf.sf_sct == NVME_CQE_SCT_GENERIC &&
1471 cmd->nc_cqe.cqe_sf.sf_sc == NVME_CQE_SC_GEN_INTERNAL_ERR) {
1472 cmd->nc_nvme->n_dead = B_TRUE;
1473 ddi_fm_service_impact(cmd->nc_nvme->n_dip,
1474 DDI_SERVICE_LOST);
1475 }
1476
1477 if (cmd->nc_cqe.cqe_sf.sf_sct == NVME_CQE_SCT_GENERIC &&
1478 cmd->nc_cqe.cqe_sf.sf_sc == NVME_CQE_SC_GEN_INV_OPC &&
1479 cmd->nc_cqe.cqe_sf.sf_dnr == 1) {
1480 nvme->n_async_event_supported = B_FALSE;
1481 }
1482
1483 nvme_free_cmd(cmd);
1484 return;
1485 }
1486
1487
1488 event.r = cmd->nc_cqe.cqe_dw0;
1489
1490 /* Clear CQE and re-submit the async request. */
1491 bzero(&cmd->nc_cqe, sizeof (nvme_cqe_t));
1492 nvme_submit_admin_cmd(nvme->n_adminq, cmd);
1493
1494 switch (event.b.ae_type) {
1495 case NVME_ASYNC_TYPE_ERROR:
1496 if (event.b.ae_logpage == NVME_LOGPAGE_ERROR) {
1497 (void) nvme_get_logpage(nvme, (void **)&error_log,
1498 &logsize, event.b.ae_logpage);
1499 } else {
1500 dev_err(nvme->n_dip, CE_WARN, "!wrong logpage in "
1501 "async event reply: %d", event.b.ae_logpage);
1502 atomic_inc_32(&nvme->n_wrong_logpage);
1503 }
1504
1505 switch (event.b.ae_info) {
1506 case NVME_ASYNC_ERROR_INV_SQ:
1507 dev_err(nvme->n_dip, CE_PANIC, "programming error: "
1508 "invalid submission queue");
1509 return;
1510
1511 case NVME_ASYNC_ERROR_INV_DBL:
1512 dev_err(nvme->n_dip, CE_PANIC, "programming error: "
1513 "invalid doorbell write value");
1514 return;
1515
1516 case NVME_ASYNC_ERROR_DIAGFAIL:
1517 dev_err(nvme->n_dip, CE_WARN, "!diagnostic failure");
1518 ddi_fm_service_impact(nvme->n_dip, DDI_SERVICE_LOST);
1519 nvme->n_dead = B_TRUE;
1520 atomic_inc_32(&nvme->n_diagfail_event);
1521 break;
1522
1523 case NVME_ASYNC_ERROR_PERSISTENT:
1524 dev_err(nvme->n_dip, CE_WARN, "!persistent internal "
1525 "device error");
1526 ddi_fm_service_impact(nvme->n_dip, DDI_SERVICE_LOST);
1527 nvme->n_dead = B_TRUE;
1528 atomic_inc_32(&nvme->n_persistent_event);
1529 break;
1530
1531 case NVME_ASYNC_ERROR_TRANSIENT:
1532 dev_err(nvme->n_dip, CE_WARN, "!transient internal "
1533 "device error");
1534 /* TODO: send ereport */
1535 atomic_inc_32(&nvme->n_transient_event);
1536 break;
1537
1538 case NVME_ASYNC_ERROR_FW_LOAD:
1539 dev_err(nvme->n_dip, CE_WARN,
1540 "!firmware image load error");
1541 atomic_inc_32(&nvme->n_fw_load_event);
1542 break;
1543 }
1544 break;
1545
1546 case NVME_ASYNC_TYPE_HEALTH:
1547 if (event.b.ae_logpage == NVME_LOGPAGE_HEALTH) {
1548 (void) nvme_get_logpage(nvme, (void **)&health_log,
1549 &logsize, event.b.ae_logpage, -1);
1550 } else {
1551 dev_err(nvme->n_dip, CE_WARN, "!wrong logpage in "
1552 "async event reply: %d", event.b.ae_logpage);
1553 atomic_inc_32(&nvme->n_wrong_logpage);
1554 }
1555
1556 switch (event.b.ae_info) {
1557 case NVME_ASYNC_HEALTH_RELIABILITY:
1558 dev_err(nvme->n_dip, CE_WARN,
1559 "!device reliability compromised");
1560 /* TODO: send ereport */
1561 atomic_inc_32(&nvme->n_reliability_event);
1562 break;
1563
1564 case NVME_ASYNC_HEALTH_TEMPERATURE:
1565 dev_err(nvme->n_dip, CE_WARN,
1566 "!temperature above threshold");
1567 /* TODO: send ereport */
1568 atomic_inc_32(&nvme->n_temperature_event);
1569 break;
1570
1571 case NVME_ASYNC_HEALTH_SPARE:
1572 dev_err(nvme->n_dip, CE_WARN,
1573 "!spare space below threshold");
1574 /* TODO: send ereport */
1575 atomic_inc_32(&nvme->n_spare_event);
1576 break;
1577 }
1578 break;
1579
1580 case NVME_ASYNC_TYPE_VENDOR:
1581 dev_err(nvme->n_dip, CE_WARN, "!vendor specific async event "
1582 "received, info = %x, logpage = %x", event.b.ae_info,
1583 event.b.ae_logpage);
1584 atomic_inc_32(&nvme->n_vendor_event);
1585 break;
1586
1587 default:
1588 dev_err(nvme->n_dip, CE_WARN, "!unknown async event received, "
1589 "type = %x, info = %x, logpage = %x", event.b.ae_type,
1590 event.b.ae_info, event.b.ae_logpage);
1591 atomic_inc_32(&nvme->n_unknown_event);
1592 break;
1593 }
1594
1595 if (error_log)
1596 kmem_free(error_log, logsize);
1597
1598 if (health_log)
1599 kmem_free(health_log, logsize);
1600 }
1601
1602 static void
1603 nvme_admin_cmd(nvme_cmd_t *cmd, int sec)
1604 {
1605 mutex_enter(&cmd->nc_mutex);
1606 nvme_submit_admin_cmd(cmd->nc_nvme->n_adminq, cmd);
1607 nvme_wait_cmd(cmd, sec);
1608 mutex_exit(&cmd->nc_mutex);
1609 }
1610
1611 static void
1612 nvme_async_event(nvme_t *nvme)
1613 {
1614 nvme_cmd_t *cmd;
1615
1616 cmd = nvme_alloc_cmd(nvme, KM_SLEEP);
1617 cmd->nc_sqid = 0;
1618 cmd->nc_sqe.sqe_opc = NVME_OPC_ASYNC_EVENT;
1619 cmd->nc_callback = nvme_async_event_task;
1620 cmd->nc_dontpanic = B_TRUE;
1621
1622 nvme_submit_admin_cmd(nvme->n_adminq, cmd);
1623 }
1624
1625 static int
1626 nvme_format_nvm(nvme_t *nvme, uint32_t nsid, uint8_t lbaf, boolean_t ms,
1627 uint8_t pi, boolean_t pil, uint8_t ses)
1628 {
1629 nvme_cmd_t *cmd = nvme_alloc_cmd(nvme, KM_SLEEP);
1630 nvme_format_nvm_t format_nvm = { 0 };
1631 int ret;
1632
1633 format_nvm.b.fm_lbaf = lbaf & 0xf;
1634 format_nvm.b.fm_ms = ms ? 1 : 0;
1635 format_nvm.b.fm_pi = pi & 0x7;
1636 format_nvm.b.fm_pil = pil ? 1 : 0;
1637 format_nvm.b.fm_ses = ses & 0x7;
1638
1639 cmd->nc_sqid = 0;
1640 cmd->nc_callback = nvme_wakeup_cmd;
1641 cmd->nc_sqe.sqe_nsid = nsid;
1642 cmd->nc_sqe.sqe_opc = NVME_OPC_NVM_FORMAT;
1643 cmd->nc_sqe.sqe_cdw10 = format_nvm.r;
1644
1645 /*
1646 * Some devices like Samsung SM951 don't allow formatting of all
1647 * namespaces in one command. Handle that gracefully.
1648 */
1649 if (nsid == (uint32_t)-1)
1650 cmd->nc_dontpanic = B_TRUE;
1651
1652 nvme_admin_cmd(cmd, nvme_format_cmd_timeout);
1653
1654 if ((ret = nvme_check_cmd_status(cmd)) != 0) {
1655 dev_err(nvme->n_dip, CE_WARN,
1656 "!FORMAT failed with sct = %x, sc = %x",
1657 cmd->nc_cqe.cqe_sf.sf_sct, cmd->nc_cqe.cqe_sf.sf_sc);
1658 }
1659
1660 nvme_free_cmd(cmd);
1661 return (ret);
1662 }
1663
1664 static int
1665 nvme_get_logpage(nvme_t *nvme, void **buf, size_t *bufsize, uint8_t logpage,
1666 ...)
1667 {
1668 nvme_cmd_t *cmd = nvme_alloc_cmd(nvme, KM_SLEEP);
1669 nvme_getlogpage_t getlogpage = { 0 };
1670 va_list ap;
1671 int ret;
1672
1673 va_start(ap, logpage);
1674
1675 cmd->nc_sqid = 0;
1676 cmd->nc_callback = nvme_wakeup_cmd;
1677 cmd->nc_sqe.sqe_opc = NVME_OPC_GET_LOG_PAGE;
1678
1679 getlogpage.b.lp_lid = logpage;
1680
1681 switch (logpage) {
1682 case NVME_LOGPAGE_ERROR:
1683 cmd->nc_sqe.sqe_nsid = (uint32_t)-1;
1684 /*
1685 * The GET LOG PAGE command can use at most 2 pages to return
1686 * data, PRP lists are not supported.
1687 */
1688 *bufsize = MIN(2 * nvme->n_pagesize,
1689 nvme->n_error_log_len * sizeof (nvme_error_log_entry_t));
1690 break;
1691
1692 case NVME_LOGPAGE_HEALTH:
1693 cmd->nc_sqe.sqe_nsid = va_arg(ap, uint32_t);
1694 *bufsize = sizeof (nvme_health_log_t);
1695 break;
1696
1697 case NVME_LOGPAGE_FWSLOT:
1698 cmd->nc_sqe.sqe_nsid = (uint32_t)-1;
1699 *bufsize = sizeof (nvme_fwslot_log_t);
1700 break;
1701
1702 default:
1703 dev_err(nvme->n_dip, CE_WARN, "!unknown log page requested: %d",
1704 logpage);
1705 atomic_inc_32(&nvme->n_unknown_logpage);
1706 ret = EINVAL;
1707 goto fail;
1708 }
1709
1710 va_end(ap);
1711
1712 getlogpage.b.lp_numd = *bufsize / sizeof (uint32_t) - 1;
1713
1714 cmd->nc_sqe.sqe_cdw10 = getlogpage.r;
1715
1716 if (nvme_zalloc_dma(nvme, getlogpage.b.lp_numd * sizeof (uint32_t),
1717 DDI_DMA_READ, &nvme->n_prp_dma_attr, &cmd->nc_dma) != DDI_SUCCESS) {
1718 dev_err(nvme->n_dip, CE_WARN,
1719 "!nvme_zalloc_dma failed for GET LOG PAGE");
1720 ret = ENOMEM;
1721 goto fail;
1722 }
1723
1724 if (cmd->nc_dma->nd_ncookie > 2) {
1725 dev_err(nvme->n_dip, CE_WARN,
1726 "!too many DMA cookies for GET LOG PAGE");
1727 atomic_inc_32(&nvme->n_too_many_cookies);
1728 ret = ENOMEM;
1729 goto fail;
1730 }
1731
1732 cmd->nc_sqe.sqe_dptr.d_prp[0] = cmd->nc_dma->nd_cookie.dmac_laddress;
1733 if (cmd->nc_dma->nd_ncookie > 1) {
1734 ddi_dma_nextcookie(cmd->nc_dma->nd_dmah,
1735 &cmd->nc_dma->nd_cookie);
1736 cmd->nc_sqe.sqe_dptr.d_prp[1] =
1737 cmd->nc_dma->nd_cookie.dmac_laddress;
1738 }
1739
1740 nvme_admin_cmd(cmd, nvme_admin_cmd_timeout);
1741
1742 if ((ret = nvme_check_cmd_status(cmd)) != 0) {
1743 dev_err(nvme->n_dip, CE_WARN,
1744 "!GET LOG PAGE failed with sct = %x, sc = %x",
1745 cmd->nc_cqe.cqe_sf.sf_sct, cmd->nc_cqe.cqe_sf.sf_sc);
1746 goto fail;
1747 }
1748
1749 *buf = kmem_alloc(*bufsize, KM_SLEEP);
1750 bcopy(cmd->nc_dma->nd_memp, *buf, *bufsize);
1751
1752 fail:
1753 nvme_free_cmd(cmd);
1754
1755 return (ret);
1756 }
1757
1758 static int
1759 nvme_identify(nvme_t *nvme, uint32_t nsid, void **buf)
1760 {
1761 nvme_cmd_t *cmd = nvme_alloc_cmd(nvme, KM_SLEEP);
1762 int ret;
1763
1764 if (buf == NULL)
1765 return (EINVAL);
1766
1767 cmd->nc_sqid = 0;
1768 cmd->nc_callback = nvme_wakeup_cmd;
1769 cmd->nc_sqe.sqe_opc = NVME_OPC_IDENTIFY;
1770 cmd->nc_sqe.sqe_nsid = nsid;
1771 cmd->nc_sqe.sqe_cdw10 = nsid ? NVME_IDENTIFY_NSID : NVME_IDENTIFY_CTRL;
1772
1773 if (nvme_zalloc_dma(nvme, NVME_IDENTIFY_BUFSIZE, DDI_DMA_READ,
1774 &nvme->n_prp_dma_attr, &cmd->nc_dma) != DDI_SUCCESS) {
1775 dev_err(nvme->n_dip, CE_WARN,
1776 "!nvme_zalloc_dma failed for IDENTIFY");
1777 ret = ENOMEM;
1778 goto fail;
1779 }
1780
1781 if (cmd->nc_dma->nd_ncookie > 2) {
1782 dev_err(nvme->n_dip, CE_WARN,
1783 "!too many DMA cookies for IDENTIFY");
1784 atomic_inc_32(&nvme->n_too_many_cookies);
1785 ret = ENOMEM;
1786 goto fail;
1787 }
1788
1789 cmd->nc_sqe.sqe_dptr.d_prp[0] = cmd->nc_dma->nd_cookie.dmac_laddress;
1790 if (cmd->nc_dma->nd_ncookie > 1) {
1791 ddi_dma_nextcookie(cmd->nc_dma->nd_dmah,
1792 &cmd->nc_dma->nd_cookie);
1793 cmd->nc_sqe.sqe_dptr.d_prp[1] =
1794 cmd->nc_dma->nd_cookie.dmac_laddress;
1795 }
1796
1797 nvme_admin_cmd(cmd, nvme_admin_cmd_timeout);
1798
1799 if ((ret = nvme_check_cmd_status(cmd)) != 0) {
1800 dev_err(nvme->n_dip, CE_WARN,
1801 "!IDENTIFY failed with sct = %x, sc = %x",
1802 cmd->nc_cqe.cqe_sf.sf_sct, cmd->nc_cqe.cqe_sf.sf_sc);
1803 goto fail;
1804 }
1805
1806 *buf = kmem_alloc(NVME_IDENTIFY_BUFSIZE, KM_SLEEP);
1807 bcopy(cmd->nc_dma->nd_memp, *buf, NVME_IDENTIFY_BUFSIZE);
1808
1809 fail:
1810 nvme_free_cmd(cmd);
1811
1812 return (ret);
1813 }
1814
1815 static int
1816 nvme_set_features(nvme_t *nvme, uint32_t nsid, uint8_t feature, uint32_t val,
1817 uint32_t *res)
1818 {
1819 _NOTE(ARGUNUSED(nsid));
1820 nvme_cmd_t *cmd = nvme_alloc_cmd(nvme, KM_SLEEP);
1821 int ret = EINVAL;
1822
1823 ASSERT(res != NULL);
1824
1825 cmd->nc_sqid = 0;
1826 cmd->nc_callback = nvme_wakeup_cmd;
1827 cmd->nc_sqe.sqe_opc = NVME_OPC_SET_FEATURES;
1828 cmd->nc_sqe.sqe_cdw10 = feature;
1829 cmd->nc_sqe.sqe_cdw11 = val;
1830
1831 switch (feature) {
1832 case NVME_FEAT_WRITE_CACHE:
1833 if (!nvme->n_write_cache_present)
1834 goto fail;
1835 break;
1836
1837 case NVME_FEAT_NQUEUES:
1838 break;
1839
1840 default:
1841 goto fail;
1842 }
1843
1844 nvme_admin_cmd(cmd, nvme_admin_cmd_timeout);
1845
1846 if ((ret = nvme_check_cmd_status(cmd)) != 0) {
1847 dev_err(nvme->n_dip, CE_WARN,
1848 "!SET FEATURES %d failed with sct = %x, sc = %x",
1849 feature, cmd->nc_cqe.cqe_sf.sf_sct,
1850 cmd->nc_cqe.cqe_sf.sf_sc);
1851 goto fail;
1852 }
1853
1854 *res = cmd->nc_cqe.cqe_dw0;
1855
1856 fail:
1857 nvme_free_cmd(cmd);
1858 return (ret);
1859 }
1860
1861 static int
1862 nvme_get_features(nvme_t *nvme, uint32_t nsid, uint8_t feature, uint32_t *res,
1863 void **buf, size_t *bufsize)
1864 {
1865 nvme_cmd_t *cmd = nvme_alloc_cmd(nvme, KM_SLEEP);
1866 int ret = EINVAL;
1867
1868 ASSERT(res != NULL);
1869
1870 if (bufsize != NULL)
1871 *bufsize = 0;
1872
1873 cmd->nc_sqid = 0;
1874 cmd->nc_callback = nvme_wakeup_cmd;
1875 cmd->nc_sqe.sqe_opc = NVME_OPC_GET_FEATURES;
1876 cmd->nc_sqe.sqe_cdw10 = feature;
1877 cmd->nc_sqe.sqe_cdw11 = *res;
1878
1879 /*
1880 * For some of the optional features there doesn't seem to be a method
1881 * of detecting whether it is supported other than using it. This will
1882 * cause "Invalid Field in Command" error, which is normally considered
1883 * a programming error. Set the nc_dontpanic flag to override the panic
1884 * in nvme_check_generic_cmd_status().
1885 */
1886 switch (feature) {
1887 case NVME_FEAT_ARBITRATION:
1888 case NVME_FEAT_POWER_MGMT:
1889 case NVME_FEAT_TEMPERATURE:
1890 case NVME_FEAT_NQUEUES:
1891 case NVME_FEAT_INTR_COAL:
1892 case NVME_FEAT_INTR_VECT:
1893 case NVME_FEAT_WRITE_ATOM:
1894 case NVME_FEAT_ASYNC_EVENT:
1895 break;
1896
1897 case NVME_FEAT_ERROR:
1898 /*
1899 * Per-namespace Deallocated or Unwritten Logical Block
1900 * Error Enable (DULBE) feature was added after initial NVMe
1901 * specification, but we currently only check this feature with
1902 * NS ID of 0 (the controller itself), and some controllers get
1903 * upset, reporting the error. For the moment, override the
1904 * panic by setting the nc_dontpanic flag.
1905 */
1906 cmd->nc_dontpanic = B_TRUE;
1907 break;
1908
1909 case NVME_FEAT_WRITE_CACHE:
1910 if (!nvme->n_write_cache_present)
1911 goto fail;
1912 break;
1913
1914 case NVME_FEAT_LBA_RANGE:
1915 if (!nvme->n_lba_range_supported)
1916 goto fail;
1917
1918 cmd->nc_dontpanic = B_TRUE;
1919 cmd->nc_sqe.sqe_nsid = nsid;
1920 ASSERT(bufsize != NULL);
1921 *bufsize = NVME_LBA_RANGE_BUFSIZE;
1922 break;
1923
1924 case NVME_FEAT_AUTO_PST:
1925 if (!nvme->n_auto_pst_supported)
1926 goto fail;
1927
1928 ASSERT(bufsize != NULL);
1929 *bufsize = NVME_AUTO_PST_BUFSIZE;
1930 break;
1931
1932 case NVME_FEAT_PROGRESS:
1933 if (!nvme->n_progress_supported)
1934 goto fail;
1935
1936 cmd->nc_dontpanic = B_TRUE;
1937 break;
1938
1939 default:
1940 goto fail;
1941 }
1942
1943 if (bufsize != NULL && *bufsize != 0) {
1944 if (nvme_zalloc_dma(nvme, *bufsize, DDI_DMA_READ,
1945 &nvme->n_prp_dma_attr, &cmd->nc_dma) != DDI_SUCCESS) {
1946 dev_err(nvme->n_dip, CE_WARN,
1947 "!nvme_zalloc_dma failed for GET FEATURES");
1948 ret = ENOMEM;
1949 goto fail;
1950 }
1951
1952 if (cmd->nc_dma->nd_ncookie > 2) {
1953 dev_err(nvme->n_dip, CE_WARN,
1954 "!too many DMA cookies for GET FEATURES");
1955 atomic_inc_32(&nvme->n_too_many_cookies);
1956 ret = ENOMEM;
1957 goto fail;
1958 }
1959
1960 cmd->nc_sqe.sqe_dptr.d_prp[0] =
1961 cmd->nc_dma->nd_cookie.dmac_laddress;
1962 if (cmd->nc_dma->nd_ncookie > 1) {
1963 ddi_dma_nextcookie(cmd->nc_dma->nd_dmah,
1964 &cmd->nc_dma->nd_cookie);
1965 cmd->nc_sqe.sqe_dptr.d_prp[1] =
1966 cmd->nc_dma->nd_cookie.dmac_laddress;
1967 }
1968 }
1969
1970 nvme_admin_cmd(cmd, nvme_admin_cmd_timeout);
1971
1972 if ((ret = nvme_check_cmd_status(cmd)) != 0) {
1973 boolean_t known = B_TRUE;
1974
1975 /* Check if this is unsupported optional feature */
1976 if (cmd->nc_cqe.cqe_sf.sf_sct == NVME_CQE_SCT_GENERIC &&
1977 cmd->nc_cqe.cqe_sf.sf_sc == NVME_CQE_SC_GEN_INV_FLD) {
1978 switch (feature) {
1979 case NVME_FEAT_LBA_RANGE:
1980 nvme->n_lba_range_supported = B_FALSE;
1981 break;
1982 case NVME_FEAT_PROGRESS:
1983 nvme->n_progress_supported = B_FALSE;
1984 break;
1985 default:
1986 known = B_FALSE;
1987 break;
1988 }
1989 } else {
1990 known = B_FALSE;
1991 }
1992
1993 /* Report the error otherwise */
1994 if (!known) {
1995 dev_err(nvme->n_dip, CE_WARN,
1996 "!GET FEATURES %d failed with sct = %x, sc = %x",
1997 feature, cmd->nc_cqe.cqe_sf.sf_sct,
1998 cmd->nc_cqe.cqe_sf.sf_sc);
1999 }
2000
2001 goto fail;
2002 }
2003
2004 if (bufsize != NULL && *bufsize != 0) {
2005 ASSERT(buf != NULL);
2006 *buf = kmem_alloc(*bufsize, KM_SLEEP);
2007 bcopy(cmd->nc_dma->nd_memp, *buf, *bufsize);
2008 }
2009
2010 *res = cmd->nc_cqe.cqe_dw0;
2011
2012 fail:
2013 nvme_free_cmd(cmd);
2014 return (ret);
2015 }
2016
2017 static int
2018 nvme_write_cache_set(nvme_t *nvme, boolean_t enable)
2019 {
2020 nvme_write_cache_t nwc = { 0 };
2021
2022 if (enable)
2023 nwc.b.wc_wce = 1;
2024
2025 return (nvme_set_features(nvme, 0, NVME_FEAT_WRITE_CACHE, nwc.r,
2026 &nwc.r));
2027 }
2028
2029 static int
2030 nvme_set_nqueues(nvme_t *nvme, uint16_t *nqueues)
2031 {
2032 nvme_nqueues_t nq = { 0 };
2033 int ret;
2034
2035 nq.b.nq_nsq = nq.b.nq_ncq = *nqueues - 1;
2036
2037 ret = nvme_set_features(nvme, 0, NVME_FEAT_NQUEUES, nq.r, &nq.r);
2038
2039 if (ret == 0) {
2040 /*
2041 * Always use the same number of submission and completion
2042 * queues, and never use more than the requested number of
2043 * queues.
2044 */
2045 *nqueues = MIN(*nqueues, MIN(nq.b.nq_nsq, nq.b.nq_ncq) + 1);
2046 }
2047
2048 return (ret);
2049 }
2050
2051 static int
2052 nvme_create_io_qpair(nvme_t *nvme, nvme_qpair_t *qp, uint16_t idx)
2053 {
2054 nvme_cmd_t *cmd = nvme_alloc_cmd(nvme, KM_SLEEP);
2055 nvme_create_queue_dw10_t dw10 = { 0 };
2056 nvme_create_cq_dw11_t c_dw11 = { 0 };
2057 nvme_create_sq_dw11_t s_dw11 = { 0 };
2058 int ret;
2059
2060 dw10.b.q_qid = idx;
2061 dw10.b.q_qsize = qp->nq_nentry - 1;
2062
2063 c_dw11.b.cq_pc = 1;
2064 c_dw11.b.cq_ien = 1;
2065 c_dw11.b.cq_iv = idx % nvme->n_intr_cnt;
2066
2067 cmd->nc_sqid = 0;
2068 cmd->nc_callback = nvme_wakeup_cmd;
2069 cmd->nc_sqe.sqe_opc = NVME_OPC_CREATE_CQUEUE;
2070 cmd->nc_sqe.sqe_cdw10 = dw10.r;
2071 cmd->nc_sqe.sqe_cdw11 = c_dw11.r;
2072 cmd->nc_sqe.sqe_dptr.d_prp[0] = qp->nq_cqdma->nd_cookie.dmac_laddress;
2073
2074 nvme_admin_cmd(cmd, nvme_admin_cmd_timeout);
2075
2076 if ((ret = nvme_check_cmd_status(cmd)) != 0) {
2077 dev_err(nvme->n_dip, CE_WARN,
2078 "!CREATE CQUEUE failed with sct = %x, sc = %x",
2079 cmd->nc_cqe.cqe_sf.sf_sct, cmd->nc_cqe.cqe_sf.sf_sc);
2080 goto fail;
2081 }
2082
2083 nvme_free_cmd(cmd);
2084
2085 s_dw11.b.sq_pc = 1;
2086 s_dw11.b.sq_cqid = idx;
2087
2088 cmd = nvme_alloc_cmd(nvme, KM_SLEEP);
2089 cmd->nc_sqid = 0;
2090 cmd->nc_callback = nvme_wakeup_cmd;
2091 cmd->nc_sqe.sqe_opc = NVME_OPC_CREATE_SQUEUE;
2092 cmd->nc_sqe.sqe_cdw10 = dw10.r;
2093 cmd->nc_sqe.sqe_cdw11 = s_dw11.r;
2094 cmd->nc_sqe.sqe_dptr.d_prp[0] = qp->nq_sqdma->nd_cookie.dmac_laddress;
2095
2096 nvme_admin_cmd(cmd, nvme_admin_cmd_timeout);
2097
2098 if ((ret = nvme_check_cmd_status(cmd)) != 0) {
2099 dev_err(nvme->n_dip, CE_WARN,
2100 "!CREATE SQUEUE failed with sct = %x, sc = %x",
2101 cmd->nc_cqe.cqe_sf.sf_sct, cmd->nc_cqe.cqe_sf.sf_sc);
2102 goto fail;
2103 }
2104
2105 fail:
2106 nvme_free_cmd(cmd);
2107
2108 return (ret);
2109 }
2110
2111 static boolean_t
2112 nvme_reset(nvme_t *nvme, boolean_t quiesce)
2113 {
2114 nvme_reg_csts_t csts;
2115 int i;
2116
2117 nvme_put32(nvme, NVME_REG_CC, 0);
2118
2119 csts.r = nvme_get32(nvme, NVME_REG_CSTS);
2120 if (csts.b.csts_rdy == 1) {
2121 nvme_put32(nvme, NVME_REG_CC, 0);
2122 for (i = 0; i != nvme->n_timeout * 10; i++) {
2123 csts.r = nvme_get32(nvme, NVME_REG_CSTS);
2124 if (csts.b.csts_rdy == 0)
2125 break;
2126
2127 if (quiesce)
2128 drv_usecwait(50000);
2129 else
2130 delay(drv_usectohz(50000));
2131 }
2132 }
2133
2134 nvme_put32(nvme, NVME_REG_AQA, 0);
2135 nvme_put32(nvme, NVME_REG_ASQ, 0);
2136 nvme_put32(nvme, NVME_REG_ACQ, 0);
2137
2138 csts.r = nvme_get32(nvme, NVME_REG_CSTS);
2139 return (csts.b.csts_rdy == 0 ? B_TRUE : B_FALSE);
2140 }
2141
2142 static void
2143 nvme_shutdown(nvme_t *nvme, int mode, boolean_t quiesce)
2144 {
2145 nvme_reg_cc_t cc;
2146 nvme_reg_csts_t csts;
2147 int i;
2148
2149 ASSERT(mode == NVME_CC_SHN_NORMAL || mode == NVME_CC_SHN_ABRUPT);
2150
2151 cc.r = nvme_get32(nvme, NVME_REG_CC);
2152 cc.b.cc_shn = mode & 0x3;
2153 nvme_put32(nvme, NVME_REG_CC, cc.r);
2154
2155 for (i = 0; i != 10; i++) {
2156 csts.r = nvme_get32(nvme, NVME_REG_CSTS);
2157 if (csts.b.csts_shst == NVME_CSTS_SHN_COMPLETE)
2158 break;
2159
2160 if (quiesce)
2161 drv_usecwait(100000);
2162 else
2163 delay(drv_usectohz(100000));
2164 }
2165 }
2166
2167
2168 static void
2169 nvme_prepare_devid(nvme_t *nvme, uint32_t nsid)
2170 {
2171 /*
2172 * Section 7.7 of the spec describes how to get a unique ID for
2173 * the controller: the vendor ID, the model name and the serial
2174 * number shall be unique when combined.
2175 *
2176 * If a namespace has no EUI64 we use the above and add the hex
2177 * namespace ID to get a unique ID for the namespace.
2178 */
2179 char model[sizeof (nvme->n_idctl->id_model) + 1];
2180 char serial[sizeof (nvme->n_idctl->id_serial) + 1];
2181
2182 bcopy(nvme->n_idctl->id_model, model, sizeof (nvme->n_idctl->id_model));
2183 bcopy(nvme->n_idctl->id_serial, serial,
2184 sizeof (nvme->n_idctl->id_serial));
2185
2186 model[sizeof (nvme->n_idctl->id_model)] = '\0';
2187 serial[sizeof (nvme->n_idctl->id_serial)] = '\0';
2188
2189 nvme->n_ns[nsid - 1].ns_devid = kmem_asprintf("%4X-%s-%s-%X",
2190 nvme->n_idctl->id_vid, model, serial, nsid);
2191 }
2192
2193 static int
2194 nvme_init_ns(nvme_t *nvme, int nsid)
2195 {
2196 nvme_namespace_t *ns = &nvme->n_ns[nsid - 1];
2197 nvme_identify_nsid_t *idns;
2198 int last_rp;
2199
2200 ns->ns_nvme = nvme;
2201
2202 if (nvme_identify(nvme, nsid, (void **)&idns) != 0) {
2203 dev_err(nvme->n_dip, CE_WARN,
2204 "!failed to identify namespace %d", nsid);
2205 return (DDI_FAILURE);
2206 }
2207
2208 ns->ns_idns = idns;
2209 ns->ns_id = nsid;
2210 ns->ns_block_count = idns->id_nsize;
2211 ns->ns_block_size =
2212 1 << idns->id_lbaf[idns->id_flbas.lba_format].lbaf_lbads;
2213 ns->ns_best_block_size = ns->ns_block_size;
2214
2215 /*
2216 * Get the EUI64 if present. Use it for devid and device node names.
2217 */
2218 if (NVME_VERSION_ATLEAST(&nvme->n_version, 1, 1))
2219 bcopy(idns->id_eui64, ns->ns_eui64, sizeof (ns->ns_eui64));
2220
2221 /*LINTED: E_BAD_PTR_CAST_ALIGN*/
2222 if (*(uint64_t *)ns->ns_eui64 != 0) {
2223 uint8_t *eui64 = ns->ns_eui64;
2224
2225 (void) snprintf(ns->ns_name, sizeof (ns->ns_name),
2226 "%02x%02x%02x%02x%02x%02x%02x%02x",
2227 eui64[0], eui64[1], eui64[2], eui64[3],
2228 eui64[4], eui64[5], eui64[6], eui64[7]);
2229 } else {
2230 (void) snprintf(ns->ns_name, sizeof (ns->ns_name), "%d",
2231 ns->ns_id);
2232
2233 nvme_prepare_devid(nvme, ns->ns_id);
2234 }
2235
2236 /*
2237 * Find the LBA format with no metadata and the best relative
2238 * performance. A value of 3 means "degraded", 0 is best.
2239 */
2240 last_rp = 3;
2241 for (int j = 0; j <= idns->id_nlbaf; j++) {
2242 if (idns->id_lbaf[j].lbaf_lbads == 0)
2243 break;
2244 if (idns->id_lbaf[j].lbaf_ms != 0)
2245 continue;
2246 if (idns->id_lbaf[j].lbaf_rp >= last_rp)
2247 continue;
2248 last_rp = idns->id_lbaf[j].lbaf_rp;
2249 ns->ns_best_block_size =
2250 1 << idns->id_lbaf[j].lbaf_lbads;
2251 }
2252
2253 if (ns->ns_best_block_size < nvme->n_min_block_size)
2254 ns->ns_best_block_size = nvme->n_min_block_size;
2255
2256 /*
2257 * We currently don't support namespaces that use either:
2258 * - protection information
2259 * - illegal block size (< 512)
2260 */
2261 if (idns->id_dps.dp_pinfo) {
2262 dev_err(nvme->n_dip, CE_WARN,
2263 "!ignoring namespace %d, unsupported feature: "
2264 "pinfo = %d", nsid, idns->id_dps.dp_pinfo);
2265 ns->ns_ignore = B_TRUE;
2266 } else if (ns->ns_block_size < 512) {
2267 dev_err(nvme->n_dip, CE_WARN,
2268 "!ignoring namespace %d, unsupported block size %"PRIu64,
2269 nsid, (uint64_t)ns->ns_block_size);
2270 ns->ns_ignore = B_TRUE;
2271 } else {
2272 ns->ns_ignore = B_FALSE;
2273 }
2274
2275 return (DDI_SUCCESS);
2276 }
2277
2278 static int
2279 nvme_init(nvme_t *nvme)
2280 {
2281 nvme_reg_cc_t cc = { 0 };
2282 nvme_reg_aqa_t aqa = { 0 };
2283 nvme_reg_asq_t asq = { 0 };
2284 nvme_reg_acq_t acq = { 0 };
2285 nvme_reg_cap_t cap;
2286 nvme_reg_vs_t vs;
2287 nvme_reg_csts_t csts;
2288 int i = 0;
2289 uint16_t nqueues;
2290 char model[sizeof (nvme->n_idctl->id_model) + 1];
2291 char *vendor, *product;
2292
2293 /* Check controller version */
2294 vs.r = nvme_get32(nvme, NVME_REG_VS);
2295 nvme->n_version.v_major = vs.b.vs_mjr;
2296 nvme->n_version.v_minor = vs.b.vs_mnr;
2297 dev_err(nvme->n_dip, CE_CONT, "?NVMe spec version %d.%d",
2298 nvme->n_version.v_major, nvme->n_version.v_minor);
2299
2300 if (nvme->n_version.v_major > nvme_version_major) {
2301 dev_err(nvme->n_dip, CE_WARN, "!no support for version > %d.x",
2302 nvme_version_major);
2303 if (nvme->n_strict_version)
2304 goto fail;
2305 }
2306
2307 /* retrieve controller configuration */
2308 cap.r = nvme_get64(nvme, NVME_REG_CAP);
2309
2310 if ((cap.b.cap_css & NVME_CAP_CSS_NVM) == 0) {
2311 dev_err(nvme->n_dip, CE_WARN,
2312 "!NVM command set not supported by hardware");
2313 goto fail;
2314 }
2315
2316 nvme->n_nssr_supported = cap.b.cap_nssrs;
2317 nvme->n_doorbell_stride = 4 << cap.b.cap_dstrd;
2318 nvme->n_timeout = cap.b.cap_to;
2319 nvme->n_arbitration_mechanisms = cap.b.cap_ams;
2320 nvme->n_cont_queues_reqd = cap.b.cap_cqr;
2321 nvme->n_max_queue_entries = cap.b.cap_mqes + 1;
2322
2323 /*
2324 * The MPSMIN and MPSMAX fields in the CAP register use 0 to specify
2325 * the base page size of 4k (1<<12), so add 12 here to get the real
2326 * page size value.
2327 */
2328 nvme->n_pageshift = MIN(MAX(cap.b.cap_mpsmin + 12, PAGESHIFT),
2329 cap.b.cap_mpsmax + 12);
2330 nvme->n_pagesize = 1UL << (nvme->n_pageshift);
2331
2332 /*
2333 * Set up Queue DMA to transfer at least 1 page-aligned page at a time.
2334 */
2335 nvme->n_queue_dma_attr.dma_attr_align = nvme->n_pagesize;
2336 nvme->n_queue_dma_attr.dma_attr_minxfer = nvme->n_pagesize;
2337
2338 /*
2339 * Set up PRP DMA to transfer 1 page-aligned page at a time.
2340 * Maxxfer may be increased after we identified the controller limits.
2341 */
2342 nvme->n_prp_dma_attr.dma_attr_maxxfer = nvme->n_pagesize;
2343 nvme->n_prp_dma_attr.dma_attr_minxfer = nvme->n_pagesize;
2344 nvme->n_prp_dma_attr.dma_attr_align = nvme->n_pagesize;
2345 nvme->n_prp_dma_attr.dma_attr_seg = nvme->n_pagesize - 1;
2346
2347 /*
2348 * Reset controller if it's still in ready state.
2349 */
2350 if (nvme_reset(nvme, B_FALSE) == B_FALSE) {
2351 dev_err(nvme->n_dip, CE_WARN, "!unable to reset controller");
2352 ddi_fm_service_impact(nvme->n_dip, DDI_SERVICE_LOST);
2353 nvme->n_dead = B_TRUE;
2354 goto fail;
2355 }
2356
2357 /*
2358 * Create the admin queue pair.
2359 */
2360 if (nvme_alloc_qpair(nvme, nvme->n_admin_queue_len, &nvme->n_adminq, 0)
2361 != DDI_SUCCESS) {
2362 dev_err(nvme->n_dip, CE_WARN,
2363 "!unable to allocate admin qpair");
2364 goto fail;
2365 }
2366 nvme->n_ioq = kmem_alloc(sizeof (nvme_qpair_t *), KM_SLEEP);
2367 nvme->n_ioq[0] = nvme->n_adminq;
2368
2369 nvme->n_progress |= NVME_ADMIN_QUEUE;
2370
2371 (void) ddi_prop_update_int(DDI_DEV_T_NONE, nvme->n_dip,
2372 "admin-queue-len", nvme->n_admin_queue_len);
2373
2374 aqa.b.aqa_asqs = aqa.b.aqa_acqs = nvme->n_admin_queue_len - 1;
2375 asq = nvme->n_adminq->nq_sqdma->nd_cookie.dmac_laddress;
2376 acq = nvme->n_adminq->nq_cqdma->nd_cookie.dmac_laddress;
2377
2378 ASSERT((asq & (nvme->n_pagesize - 1)) == 0);
2379 ASSERT((acq & (nvme->n_pagesize - 1)) == 0);
2380
2381 nvme_put32(nvme, NVME_REG_AQA, aqa.r);
2382 nvme_put64(nvme, NVME_REG_ASQ, asq);
2383 nvme_put64(nvme, NVME_REG_ACQ, acq);
2384
2385 cc.b.cc_ams = 0; /* use Round-Robin arbitration */
2386 cc.b.cc_css = 0; /* use NVM command set */
2387 cc.b.cc_mps = nvme->n_pageshift - 12;
2388 cc.b.cc_shn = 0; /* no shutdown in progress */
2389 cc.b.cc_en = 1; /* enable controller */
2390 cc.b.cc_iosqes = 6; /* submission queue entry is 2^6 bytes long */
2391 cc.b.cc_iocqes = 4; /* completion queue entry is 2^4 bytes long */
2392
2393 nvme_put32(nvme, NVME_REG_CC, cc.r);
2394
2395 /*
2396 * Wait for the controller to become ready.
2397 */
2398 csts.r = nvme_get32(nvme, NVME_REG_CSTS);
2399 if (csts.b.csts_rdy == 0) {
2400 for (i = 0; i != nvme->n_timeout * 10; i++) {
2401 delay(drv_usectohz(50000));
2402 csts.r = nvme_get32(nvme, NVME_REG_CSTS);
2403
2404 if (csts.b.csts_cfs == 1) {
2405 dev_err(nvme->n_dip, CE_WARN,
2406 "!controller fatal status at init");
2407 ddi_fm_service_impact(nvme->n_dip,
2408 DDI_SERVICE_LOST);
2409 nvme->n_dead = B_TRUE;
2410 goto fail;
2411 }
2412
2413 if (csts.b.csts_rdy == 1)
2414 break;
2415 }
2416 }
2417
2418 if (csts.b.csts_rdy == 0) {
2419 dev_err(nvme->n_dip, CE_WARN, "!controller not ready");
2420 ddi_fm_service_impact(nvme->n_dip, DDI_SERVICE_LOST);
2421 nvme->n_dead = B_TRUE;
2422 goto fail;
2423 }
2424
2425 /*
2426 * Assume an abort command limit of 1. We'll destroy and re-init
2427 * that later when we know the true abort command limit.
2428 */
2429 sema_init(&nvme->n_abort_sema, 1, NULL, SEMA_DRIVER, NULL);
2430
2431 /*
2432 * Setup initial interrupt for admin queue.
2433 */
2434 if ((nvme_setup_interrupts(nvme, DDI_INTR_TYPE_MSIX, 1)
2435 != DDI_SUCCESS) &&
2436 (nvme_setup_interrupts(nvme, DDI_INTR_TYPE_MSI, 1)
2437 != DDI_SUCCESS) &&
2438 (nvme_setup_interrupts(nvme, DDI_INTR_TYPE_FIXED, 1)
2439 != DDI_SUCCESS)) {
2440 dev_err(nvme->n_dip, CE_WARN,
2441 "!failed to setup initial interrupt");
2442 goto fail;
2443 }
2444
2445 /*
2446 * Post an asynchronous event command to catch errors.
2447 * We assume the asynchronous events are supported as required by
2448 * specification (Figure 40 in section 5 of NVMe 1.2).
2449 * However, since at least qemu does not follow the specification,
2450 * we need a mechanism to protect ourselves.
2451 */
2452 nvme->n_async_event_supported = B_TRUE;
2453 nvme_async_event(nvme);
2454
2455 /*
2456 * Identify Controller
2457 */
2458 if (nvme_identify(nvme, 0, (void **)&nvme->n_idctl) != 0) {
2459 dev_err(nvme->n_dip, CE_WARN,
2460 "!failed to identify controller");
2461 goto fail;
2462 }
2463
2464 /*
2465 * Get Vendor & Product ID
2466 */
2467 bcopy(nvme->n_idctl->id_model, model, sizeof (nvme->n_idctl->id_model));
2468 model[sizeof (nvme->n_idctl->id_model)] = '\0';
2469 sata_split_model(model, &vendor, &product);
2470
2471 if (vendor == NULL)
2472 nvme->n_vendor = strdup("NVMe");
2473 else
2474 nvme->n_vendor = strdup(vendor);
2475
2476 nvme->n_product = strdup(product);
2477
2478 /*
2479 * Get controller limits.
2480 */
2481 nvme->n_async_event_limit = MAX(NVME_MIN_ASYNC_EVENT_LIMIT,
2482 MIN(nvme->n_admin_queue_len / 10,
2483 MIN(nvme->n_idctl->id_aerl + 1, nvme->n_async_event_limit)));
2484
2485 (void) ddi_prop_update_int(DDI_DEV_T_NONE, nvme->n_dip,
2486 "async-event-limit", nvme->n_async_event_limit);
2487
2488 nvme->n_abort_command_limit = nvme->n_idctl->id_acl + 1;
2489
2490 /*
2491 * Reinitialize the semaphore with the true abort command limit
2492 * supported by the hardware. It's not necessary to disable interrupts
2493 * as only command aborts use the semaphore, and no commands are
2494 * executed or aborted while we're here.
2495 */
2496 sema_destroy(&nvme->n_abort_sema);
2497 sema_init(&nvme->n_abort_sema, nvme->n_abort_command_limit - 1, NULL,
2498 SEMA_DRIVER, NULL);
2499
2500 nvme->n_progress |= NVME_CTRL_LIMITS;
2501
2502 if (nvme->n_idctl->id_mdts == 0)
2503 nvme->n_max_data_transfer_size = nvme->n_pagesize * 65536;
2504 else
2505 nvme->n_max_data_transfer_size =
2506 1ull << (nvme->n_pageshift + nvme->n_idctl->id_mdts);
2507
2508 nvme->n_error_log_len = nvme->n_idctl->id_elpe + 1;
2509
2510 /*
2511 * Limit n_max_data_transfer_size to what we can handle in one PRP.
2512 * Chained PRPs are currently unsupported.
2513 *
2514 * This is a no-op on hardware which doesn't support a transfer size
2515 * big enough to require chained PRPs.
2516 */
2517 nvme->n_max_data_transfer_size = MIN(nvme->n_max_data_transfer_size,
2518 (nvme->n_pagesize / sizeof (uint64_t) * nvme->n_pagesize));
2519
2520 nvme->n_prp_dma_attr.dma_attr_maxxfer = nvme->n_max_data_transfer_size;
2521
2522 /*
2523 * Make sure the minimum/maximum queue entry sizes are not
2524 * larger/smaller than the default.
2525 */
2526
2527 if (((1 << nvme->n_idctl->id_sqes.qes_min) > sizeof (nvme_sqe_t)) ||
2528 ((1 << nvme->n_idctl->id_sqes.qes_max) < sizeof (nvme_sqe_t)) ||
2529 ((1 << nvme->n_idctl->id_cqes.qes_min) > sizeof (nvme_cqe_t)) ||
2530 ((1 << nvme->n_idctl->id_cqes.qes_max) < sizeof (nvme_cqe_t)))
2531 goto fail;
2532
2533 /*
2534 * Check for the presence of a Volatile Write Cache. If present,
2535 * enable or disable based on the value of the property
2536 * volatile-write-cache-enable (default is enabled).
2537 */
2538 nvme->n_write_cache_present =
2539 nvme->n_idctl->id_vwc.vwc_present == 0 ? B_FALSE : B_TRUE;
2540
2541 (void) ddi_prop_update_int(DDI_DEV_T_NONE, nvme->n_dip,
2542 "volatile-write-cache-present",
2543 nvme->n_write_cache_present ? 1 : 0);
2544
2545 if (!nvme->n_write_cache_present) {
2546 nvme->n_write_cache_enabled = B_FALSE;
2547 } else if (nvme_write_cache_set(nvme, nvme->n_write_cache_enabled)
2548 != 0) {
2549 dev_err(nvme->n_dip, CE_WARN,
2550 "!failed to %sable volatile write cache",
2551 nvme->n_write_cache_enabled ? "en" : "dis");
2552 /*
2553 * Assume the cache is (still) enabled.
2554 */
2555 nvme->n_write_cache_enabled = B_TRUE;
2556 }
2557
2558 (void) ddi_prop_update_int(DDI_DEV_T_NONE, nvme->n_dip,
2559 "volatile-write-cache-enable",
2560 nvme->n_write_cache_enabled ? 1 : 0);
2561
2562 /*
2563 * Assume LBA Range Type feature is supported. If it isn't this
2564 * will be set to B_FALSE by nvme_get_features().
2565 */
2566 nvme->n_lba_range_supported = B_TRUE;
2567
2568 /*
2569 * Check support for Autonomous Power State Transition.
2570 */
2571 if (NVME_VERSION_ATLEAST(&nvme->n_version, 1, 1))
2572 nvme->n_auto_pst_supported =
2573 nvme->n_idctl->id_apsta.ap_sup == 0 ? B_FALSE : B_TRUE;
2574
2575 /*
2576 * Assume Software Progress Marker feature is supported. If it isn't
2577 * this will be set to B_FALSE by nvme_get_features().
2578 */
2579 nvme->n_progress_supported = B_TRUE;
2580
2581 /*
2582 * Identify Namespaces
2583 */
2584 nvme->n_namespace_count = nvme->n_idctl->id_nn;
2585
2586 if (nvme->n_namespace_count == 0) {
2587 dev_err(nvme->n_dip, CE_WARN,
2588 "!controllers without namespaces are not supported");
2589 goto fail;
2590 }
2591
2592 if (nvme->n_namespace_count > NVME_MINOR_MAX) {
2593 dev_err(nvme->n_dip, CE_WARN,
2594 "!too many namespaces: %d, limiting to %d\n",
2595 nvme->n_namespace_count, NVME_MINOR_MAX);
2596 nvme->n_namespace_count = NVME_MINOR_MAX;
2597 }
2598
2599 nvme->n_ns = kmem_zalloc(sizeof (nvme_namespace_t) *
2600 nvme->n_namespace_count, KM_SLEEP);
2601
2602 for (i = 0; i != nvme->n_namespace_count; i++) {
2603 mutex_init(&nvme->n_ns[i].ns_minor.nm_mutex, NULL, MUTEX_DRIVER,
2604 NULL);
2605 if (nvme_init_ns(nvme, i + 1) != DDI_SUCCESS)
2606 goto fail;
2607 }
2608
2609 /*
2610 * Try to set up MSI/MSI-X interrupts.
2611 */
2612 if ((nvme->n_intr_types & (DDI_INTR_TYPE_MSI | DDI_INTR_TYPE_MSIX))
2613 != 0) {
2614 nvme_release_interrupts(nvme);
2615
2616 nqueues = MIN(UINT16_MAX, ncpus);
2617
2618 if ((nvme_setup_interrupts(nvme, DDI_INTR_TYPE_MSIX,
2619 nqueues) != DDI_SUCCESS) &&
2620 (nvme_setup_interrupts(nvme, DDI_INTR_TYPE_MSI,
2621 nqueues) != DDI_SUCCESS)) {
2622 dev_err(nvme->n_dip, CE_WARN,
2623 "!failed to setup MSI/MSI-X interrupts");
2624 goto fail;
2625 }
2626 }
2627
2628 nqueues = nvme->n_intr_cnt;
2629
2630 /*
2631 * Create I/O queue pairs.
2632 */
2633
2634 if (nvme_set_nqueues(nvme, &nqueues) != 0) {
2635 dev_err(nvme->n_dip, CE_WARN,
2636 "!failed to set number of I/O queues to %d",
2637 nvme->n_intr_cnt);
2638 goto fail;
2639 }
2640
2641 /*
2642 * Reallocate I/O queue array
2643 */
2644 kmem_free(nvme->n_ioq, sizeof (nvme_qpair_t *));
2645 nvme->n_ioq = kmem_zalloc(sizeof (nvme_qpair_t *) *
2646 (nqueues + 1), KM_SLEEP);
2647 nvme->n_ioq[0] = nvme->n_adminq;
2648
2649 nvme->n_ioq_count = nqueues;
2650
2651 /*
2652 * If we got less queues than we asked for we might as well give
2653 * some of the interrupt vectors back to the system.
2654 */
2655 if (nvme->n_ioq_count < nvme->n_intr_cnt) {
2656 nvme_release_interrupts(nvme);
2657
2658 if (nvme_setup_interrupts(nvme, nvme->n_intr_type,
2659 nvme->n_ioq_count) != DDI_SUCCESS) {
2660 dev_err(nvme->n_dip, CE_WARN,
2661 "!failed to reduce number of interrupts");
2662 goto fail;
2663 }
2664 }
2665
2666 /*
2667 * Alloc & register I/O queue pairs
2668 */
2669 nvme->n_io_queue_len =
2670 MIN(nvme->n_io_queue_len, nvme->n_max_queue_entries);
2671 (void) ddi_prop_update_int(DDI_DEV_T_NONE, nvme->n_dip, "io-queue-len",
2672 nvme->n_io_queue_len);
2673
2674 for (i = 1; i != nvme->n_ioq_count + 1; i++) {
2675 if (nvme_alloc_qpair(nvme, nvme->n_io_queue_len,
2676 &nvme->n_ioq[i], i) != DDI_SUCCESS) {
2677 dev_err(nvme->n_dip, CE_WARN,
2678 "!unable to allocate I/O qpair %d", i);
2679 goto fail;
2680 }
2681
2682 if (nvme_create_io_qpair(nvme, nvme->n_ioq[i], i) != 0) {
2683 dev_err(nvme->n_dip, CE_WARN,
2684 "!unable to create I/O qpair %d", i);
2685 goto fail;
2686 }
2687 }
2688
2689 /*
2690 * Post more asynchronous events commands to reduce event reporting
2691 * latency as suggested by the spec.
2692 */
2693 if (nvme->n_async_event_supported) {
2694 for (i = 1; i != nvme->n_async_event_limit; i++)
2695 nvme_async_event(nvme);
2696 }
2697
2698 return (DDI_SUCCESS);
2699
2700 fail:
2701 (void) nvme_reset(nvme, B_FALSE);
2702 return (DDI_FAILURE);
2703 }
2704
2705 static uint_t
2706 nvme_intr(caddr_t arg1, caddr_t arg2)
2707 {
2708 /*LINTED: E_PTR_BAD_CAST_ALIGN*/
2709 nvme_t *nvme = (nvme_t *)arg1;
2710 int inum = (int)(uintptr_t)arg2;
2711 int ccnt = 0;
2712 int qnum;
2713 nvme_cmd_t *cmd;
2714
2715 if (inum >= nvme->n_intr_cnt)
2716 return (DDI_INTR_UNCLAIMED);
2717
2718 if (nvme->n_dead)
2719 return (nvme->n_intr_type == DDI_INTR_TYPE_FIXED ?
2720 DDI_INTR_UNCLAIMED : DDI_INTR_CLAIMED);
2721
2722 /*
2723 * The interrupt vector a queue uses is calculated as queue_idx %
2724 * intr_cnt in nvme_create_io_qpair(). Iterate through the queue array
2725 * in steps of n_intr_cnt to process all queues using this vector.
2726 */
2727 for (qnum = inum;
2728 qnum < nvme->n_ioq_count + 1 && nvme->n_ioq[qnum] != NULL;
2729 qnum += nvme->n_intr_cnt) {
2730 while ((cmd = nvme_retrieve_cmd(nvme, nvme->n_ioq[qnum]))) {
2731 taskq_dispatch_ent((taskq_t *)cmd->nc_nvme->n_cmd_taskq,
2732 cmd->nc_callback, cmd, TQ_NOSLEEP, &cmd->nc_tqent);
2733 ccnt++;
2734 }
2735 }
2736
2737 return (ccnt > 0 ? DDI_INTR_CLAIMED : DDI_INTR_UNCLAIMED);
2738 }
2739
2740 static void
2741 nvme_release_interrupts(nvme_t *nvme)
2742 {
2743 int i;
2744
2745 for (i = 0; i < nvme->n_intr_cnt; i++) {
2746 if (nvme->n_inth[i] == NULL)
2747 break;
2748
2749 if (nvme->n_intr_cap & DDI_INTR_FLAG_BLOCK)
2750 (void) ddi_intr_block_disable(&nvme->n_inth[i], 1);
2751 else
2752 (void) ddi_intr_disable(nvme->n_inth[i]);
2753
2754 (void) ddi_intr_remove_handler(nvme->n_inth[i]);
2755 (void) ddi_intr_free(nvme->n_inth[i]);
2756 }
2757
2758 kmem_free(nvme->n_inth, nvme->n_inth_sz);
2759 nvme->n_inth = NULL;
2760 nvme->n_inth_sz = 0;
2761
2762 nvme->n_progress &= ~NVME_INTERRUPTS;
2763 }
2764
2765 static int
2766 nvme_setup_interrupts(nvme_t *nvme, int intr_type, int nqpairs)
2767 {
2768 int nintrs, navail, count;
2769 int ret;
2770 int i;
2771
2772 if (nvme->n_intr_types == 0) {
2773 ret = ddi_intr_get_supported_types(nvme->n_dip,
2774 &nvme->n_intr_types);
2775 if (ret != DDI_SUCCESS) {
2776 dev_err(nvme->n_dip, CE_WARN,
2777 "!%s: ddi_intr_get_supported types failed",
2778 __func__);
2779 return (ret);
2780 }
2781 #ifdef __x86
2782 if (get_hwenv() == HW_VMWARE)
2783 nvme->n_intr_types &= ~DDI_INTR_TYPE_MSIX;
2784 #endif
2785 }
2786
2787 if ((nvme->n_intr_types & intr_type) == 0)
2788 return (DDI_FAILURE);
2789
2790 ret = ddi_intr_get_nintrs(nvme->n_dip, intr_type, &nintrs);
2791 if (ret != DDI_SUCCESS) {
2792 dev_err(nvme->n_dip, CE_WARN, "!%s: ddi_intr_get_nintrs failed",
2793 __func__);
2794 return (ret);
2795 }
2796
2797 ret = ddi_intr_get_navail(nvme->n_dip, intr_type, &navail);
2798 if (ret != DDI_SUCCESS) {
2799 dev_err(nvme->n_dip, CE_WARN, "!%s: ddi_intr_get_navail failed",
2800 __func__);
2801 return (ret);
2802 }
2803
2804 /* We want at most one interrupt per queue pair. */
2805 if (navail > nqpairs)
2806 navail = nqpairs;
2807
2808 nvme->n_inth_sz = sizeof (ddi_intr_handle_t) * navail;
2809 nvme->n_inth = kmem_zalloc(nvme->n_inth_sz, KM_SLEEP);
2810
2811 ret = ddi_intr_alloc(nvme->n_dip, nvme->n_inth, intr_type, 0, navail,
2812 &count, 0);
2813 if (ret != DDI_SUCCESS) {
2814 dev_err(nvme->n_dip, CE_WARN, "!%s: ddi_intr_alloc failed",
2815 __func__);
2816 goto fail;
2817 }
2818
2819 nvme->n_intr_cnt = count;
2820
2821 ret = ddi_intr_get_pri(nvme->n_inth[0], &nvme->n_intr_pri);
2822 if (ret != DDI_SUCCESS) {
2823 dev_err(nvme->n_dip, CE_WARN, "!%s: ddi_intr_get_pri failed",
2824 __func__);
2825 goto fail;
2826 }
2827
2828 for (i = 0; i < count; i++) {
2829 ret = ddi_intr_add_handler(nvme->n_inth[i], nvme_intr,
2830 (void *)nvme, (void *)(uintptr_t)i);
2831 if (ret != DDI_SUCCESS) {
2832 dev_err(nvme->n_dip, CE_WARN,
2833 "!%s: ddi_intr_add_handler failed", __func__);
2834 goto fail;
2835 }
2836 }
2837
2838 (void) ddi_intr_get_cap(nvme->n_inth[0], &nvme->n_intr_cap);
2839
2840 for (i = 0; i < count; i++) {
2841 if (nvme->n_intr_cap & DDI_INTR_FLAG_BLOCK)
2842 ret = ddi_intr_block_enable(&nvme->n_inth[i], 1);
2843 else
2844 ret = ddi_intr_enable(nvme->n_inth[i]);
2845
2846 if (ret != DDI_SUCCESS) {
2847 dev_err(nvme->n_dip, CE_WARN,
2848 "!%s: enabling interrupt %d failed", __func__, i);
2849 goto fail;
2850 }
2851 }
2852
2853 nvme->n_intr_type = intr_type;
2854
2855 nvme->n_progress |= NVME_INTERRUPTS;
2856
2857 return (DDI_SUCCESS);
2858
2859 fail:
2860 nvme_release_interrupts(nvme);
2861
2862 return (ret);
2863 }
2864
2865 static int
2866 nvme_fm_errcb(dev_info_t *dip, ddi_fm_error_t *fm_error, const void *arg)
2867 {
2868 _NOTE(ARGUNUSED(arg));
2869
2870 pci_ereport_post(dip, fm_error, NULL);
2871 return (fm_error->fme_status);
2872 }
2873
2874 static int
2875 nvme_attach(dev_info_t *dip, ddi_attach_cmd_t cmd)
2876 {
2877 nvme_t *nvme;
2878 int instance;
2879 int nregs;
2880 off_t regsize;
2881 int i;
2882 char name[32];
2883
2884 if (cmd != DDI_ATTACH)
2885 return (DDI_FAILURE);
2886
2887 instance = ddi_get_instance(dip);
2888
2889 if (ddi_soft_state_zalloc(nvme_state, instance) != DDI_SUCCESS)
2890 return (DDI_FAILURE);
2891
2892 nvme = ddi_get_soft_state(nvme_state, instance);
2893 ddi_set_driver_private(dip, nvme);
2894 nvme->n_dip = dip;
2895
2896 mutex_init(&nvme->n_minor.nm_mutex, NULL, MUTEX_DRIVER, NULL);
2897
2898 nvme->n_strict_version = ddi_prop_get_int(DDI_DEV_T_ANY, dip,
2899 DDI_PROP_DONTPASS, "strict-version", 1) == 1 ? B_TRUE : B_FALSE;
2900 nvme->n_ignore_unknown_vendor_status = ddi_prop_get_int(DDI_DEV_T_ANY,
2901 dip, DDI_PROP_DONTPASS, "ignore-unknown-vendor-status", 0) == 1 ?
2902 B_TRUE : B_FALSE;
2903 nvme->n_admin_queue_len = ddi_prop_get_int(DDI_DEV_T_ANY, dip,
2904 DDI_PROP_DONTPASS, "admin-queue-len", NVME_DEFAULT_ADMIN_QUEUE_LEN);
2905 nvme->n_io_queue_len = ddi_prop_get_int(DDI_DEV_T_ANY, dip,
2906 DDI_PROP_DONTPASS, "io-queue-len", NVME_DEFAULT_IO_QUEUE_LEN);
2907 nvme->n_async_event_limit = ddi_prop_get_int(DDI_DEV_T_ANY, dip,
2908 DDI_PROP_DONTPASS, "async-event-limit",
2909 NVME_DEFAULT_ASYNC_EVENT_LIMIT);
2910 nvme->n_write_cache_enabled = ddi_prop_get_int(DDI_DEV_T_ANY, dip,
2911 DDI_PROP_DONTPASS, "volatile-write-cache-enable", 1) != 0 ?
2912 B_TRUE : B_FALSE;
2913 nvme->n_min_block_size = ddi_prop_get_int(DDI_DEV_T_ANY, dip,
2914 DDI_PROP_DONTPASS, "min-phys-block-size",
2915 NVME_DEFAULT_MIN_BLOCK_SIZE);
2916
2917 if (!ISP2(nvme->n_min_block_size) ||
2918 (nvme->n_min_block_size < NVME_DEFAULT_MIN_BLOCK_SIZE)) {
2919 dev_err(dip, CE_WARN, "!min-phys-block-size %s, "
2920 "using default %d", ISP2(nvme->n_min_block_size) ?
2921 "too low" : "not a power of 2",
2922 NVME_DEFAULT_MIN_BLOCK_SIZE);
2923 nvme->n_min_block_size = NVME_DEFAULT_MIN_BLOCK_SIZE;
2924 }
2925
2926 if (nvme->n_admin_queue_len < NVME_MIN_ADMIN_QUEUE_LEN)
2927 nvme->n_admin_queue_len = NVME_MIN_ADMIN_QUEUE_LEN;
2928 else if (nvme->n_admin_queue_len > NVME_MAX_ADMIN_QUEUE_LEN)
2929 nvme->n_admin_queue_len = NVME_MAX_ADMIN_QUEUE_LEN;
2930
2931 if (nvme->n_io_queue_len < NVME_MIN_IO_QUEUE_LEN)
2932 nvme->n_io_queue_len = NVME_MIN_IO_QUEUE_LEN;
2933
2934 if (nvme->n_async_event_limit < 1)
2935 nvme->n_async_event_limit = NVME_DEFAULT_ASYNC_EVENT_LIMIT;
2936
2937 nvme->n_reg_acc_attr = nvme_reg_acc_attr;
2938 nvme->n_queue_dma_attr = nvme_queue_dma_attr;
2939 nvme->n_prp_dma_attr = nvme_prp_dma_attr;
2940 nvme->n_sgl_dma_attr = nvme_sgl_dma_attr;
2941
2942 /*
2943 * Setup FMA support.
2944 */
2945 nvme->n_fm_cap = ddi_getprop(DDI_DEV_T_ANY, dip,
2946 DDI_PROP_CANSLEEP | DDI_PROP_DONTPASS, "fm-capable",
2947 DDI_FM_EREPORT_CAPABLE | DDI_FM_ACCCHK_CAPABLE |
2948 DDI_FM_DMACHK_CAPABLE | DDI_FM_ERRCB_CAPABLE);
2949
2950 ddi_fm_init(dip, &nvme->n_fm_cap, &nvme->n_fm_ibc);
2951
2952 if (nvme->n_fm_cap) {
2953 if (nvme->n_fm_cap & DDI_FM_ACCCHK_CAPABLE)
2954 nvme->n_reg_acc_attr.devacc_attr_access =
2955 DDI_FLAGERR_ACC;
2956
2957 if (nvme->n_fm_cap & DDI_FM_DMACHK_CAPABLE) {
2958 nvme->n_prp_dma_attr.dma_attr_flags |= DDI_DMA_FLAGERR;
2959 nvme->n_sgl_dma_attr.dma_attr_flags |= DDI_DMA_FLAGERR;
2960 }
2961
2962 if (DDI_FM_EREPORT_CAP(nvme->n_fm_cap) ||
2963 DDI_FM_ERRCB_CAP(nvme->n_fm_cap))
2964 pci_ereport_setup(dip);
2965
2966 if (DDI_FM_ERRCB_CAP(nvme->n_fm_cap))
2967 ddi_fm_handler_register(dip, nvme_fm_errcb,
2968 (void *)nvme);
2969 }
2970
2971 nvme->n_progress |= NVME_FMA_INIT;
2972
2973 /*
2974 * The spec defines several register sets. Only the controller
2975 * registers (set 1) are currently used.
2976 */
2977 if (ddi_dev_nregs(dip, &nregs) == DDI_FAILURE ||
2978 nregs < 2 ||
2979 ddi_dev_regsize(dip, 1, ®size) == DDI_FAILURE)
2980 goto fail;
2981
2982 if (ddi_regs_map_setup(dip, 1, &nvme->n_regs, 0, regsize,
2983 &nvme->n_reg_acc_attr, &nvme->n_regh) != DDI_SUCCESS) {
2984 dev_err(dip, CE_WARN, "!failed to map regset 1");
2985 goto fail;
2986 }
2987
2988 nvme->n_progress |= NVME_REGS_MAPPED;
2989
2990 /*
2991 * Create taskq for command completion.
2992 */
2993 (void) snprintf(name, sizeof (name), "%s%d_cmd_taskq",
2994 ddi_driver_name(dip), ddi_get_instance(dip));
2995 nvme->n_cmd_taskq = ddi_taskq_create(dip, name, MIN(UINT16_MAX, ncpus),
2996 TASKQ_DEFAULTPRI, 0);
2997 if (nvme->n_cmd_taskq == NULL) {
2998 dev_err(dip, CE_WARN, "!failed to create cmd taskq");
2999 goto fail;
3000 }
3001
3002 /*
3003 * Create PRP DMA cache
3004 */
3005 (void) snprintf(name, sizeof (name), "%s%d_prp_cache",
3006 ddi_driver_name(dip), ddi_get_instance(dip));
3007 nvme->n_prp_cache = kmem_cache_create(name, sizeof (nvme_dma_t),
3008 0, nvme_prp_dma_constructor, nvme_prp_dma_destructor,
3009 NULL, (void *)nvme, NULL, 0);
3010
3011 if (nvme_init(nvme) != DDI_SUCCESS)
3012 goto fail;
3013
3014 /*
3015 * Attach the blkdev driver for each namespace.
3016 */
3017 for (i = 0; i != nvme->n_namespace_count; i++) {
3018 if (ddi_create_minor_node(nvme->n_dip, nvme->n_ns[i].ns_name,
3019 S_IFCHR, NVME_MINOR(ddi_get_instance(nvme->n_dip), i + 1),
3020 DDI_NT_NVME_ATTACHMENT_POINT, 0) != DDI_SUCCESS) {
3021 dev_err(dip, CE_WARN,
3022 "!failed to create minor node for namespace %d", i);
3023 goto fail;
3024 }
3025
3026 if (nvme->n_ns[i].ns_ignore)
3027 continue;
3028
3029 nvme->n_ns[i].ns_bd_hdl = bd_alloc_handle(&nvme->n_ns[i],
3030 &nvme_bd_ops, &nvme->n_prp_dma_attr, KM_SLEEP);
3031
3032 if (nvme->n_ns[i].ns_bd_hdl == NULL) {
3033 dev_err(dip, CE_WARN,
3034 "!failed to get blkdev handle for namespace %d", i);
3035 goto fail;
3036 }
3037
3038 if (bd_attach_handle(dip, nvme->n_ns[i].ns_bd_hdl)
3039 != DDI_SUCCESS) {
3040 dev_err(dip, CE_WARN,
3041 "!failed to attach blkdev handle for namespace %d",
3042 i);
3043 goto fail;
3044 }
3045 }
3046
3047 if (ddi_create_minor_node(dip, "devctl", S_IFCHR,
3048 NVME_MINOR(ddi_get_instance(dip), 0), DDI_NT_NVME_NEXUS, 0)
3049 != DDI_SUCCESS) {
3050 dev_err(dip, CE_WARN, "nvme_attach: "
3051 "cannot create devctl minor node");
3052 goto fail;
3053 }
3054
3055 return (DDI_SUCCESS);
3056
3057 fail:
3058 /* attach successful anyway so that FMA can retire the device */
3059 if (nvme->n_dead)
3060 return (DDI_SUCCESS);
3061
3062 (void) nvme_detach(dip, DDI_DETACH);
3063
3064 return (DDI_FAILURE);
3065 }
3066
3067 static int
3068 nvme_detach(dev_info_t *dip, ddi_detach_cmd_t cmd)
3069 {
3070 int instance, i;
3071 nvme_t *nvme;
3072
3073 if (cmd != DDI_DETACH)
3074 return (DDI_FAILURE);
3075
3076 instance = ddi_get_instance(dip);
3077
3078 nvme = ddi_get_soft_state(nvme_state, instance);
3079
3080 if (nvme == NULL)
3081 return (DDI_FAILURE);
3082
3083 ddi_remove_minor_node(dip, "devctl");
3084 mutex_destroy(&nvme->n_minor.nm_mutex);
3085
3086 if (nvme->n_ns) {
3087 for (i = 0; i != nvme->n_namespace_count; i++) {
3088 ddi_remove_minor_node(dip, nvme->n_ns[i].ns_name);
3089 mutex_destroy(&nvme->n_ns[i].ns_minor.nm_mutex);
3090
3091 if (nvme->n_ns[i].ns_bd_hdl) {
3092 (void) bd_detach_handle(
3093 nvme->n_ns[i].ns_bd_hdl);
3094 bd_free_handle(nvme->n_ns[i].ns_bd_hdl);
3095 }
3096
3097 if (nvme->n_ns[i].ns_idns)
3098 kmem_free(nvme->n_ns[i].ns_idns,
3099 sizeof (nvme_identify_nsid_t));
3100 if (nvme->n_ns[i].ns_devid)
3101 strfree(nvme->n_ns[i].ns_devid);
3102 }
3103
3104 kmem_free(nvme->n_ns, sizeof (nvme_namespace_t) *
3105 nvme->n_namespace_count);
3106 }
3107
3108 if (nvme->n_progress & NVME_INTERRUPTS)
3109 nvme_release_interrupts(nvme);
3110
3111 if (nvme->n_cmd_taskq)
3112 ddi_taskq_wait(nvme->n_cmd_taskq);
3113
3114 if (nvme->n_ioq_count > 0) {
3115 for (i = 1; i != nvme->n_ioq_count + 1; i++) {
3116 if (nvme->n_ioq[i] != NULL) {
3117 /* TODO: send destroy queue commands */
3118 nvme_free_qpair(nvme->n_ioq[i]);
3119 }
3120 }
3121
3122 kmem_free(nvme->n_ioq, sizeof (nvme_qpair_t *) *
3123 (nvme->n_ioq_count + 1));
3124 }
3125
3126 if (nvme->n_prp_cache != NULL) {
3127 kmem_cache_destroy(nvme->n_prp_cache);
3128 }
3129
3130 if (nvme->n_progress & NVME_REGS_MAPPED) {
3131 nvme_shutdown(nvme, NVME_CC_SHN_NORMAL, B_FALSE);
3132 (void) nvme_reset(nvme, B_FALSE);
3133 }
3134
3135 if (nvme->n_cmd_taskq)
3136 ddi_taskq_destroy(nvme->n_cmd_taskq);
3137
3138 if (nvme->n_progress & NVME_CTRL_LIMITS)
3139 sema_destroy(&nvme->n_abort_sema);
3140
3141 if (nvme->n_progress & NVME_ADMIN_QUEUE)
3142 nvme_free_qpair(nvme->n_adminq);
3143
3144 if (nvme->n_idctl)
3145 kmem_free(nvme->n_idctl, NVME_IDENTIFY_BUFSIZE);
3146
3147 if (nvme->n_progress & NVME_REGS_MAPPED)
3148 ddi_regs_map_free(&nvme->n_regh);
3149
3150 if (nvme->n_progress & NVME_FMA_INIT) {
3151 if (DDI_FM_ERRCB_CAP(nvme->n_fm_cap))
3152 ddi_fm_handler_unregister(nvme->n_dip);
3153
3154 if (DDI_FM_EREPORT_CAP(nvme->n_fm_cap) ||
3155 DDI_FM_ERRCB_CAP(nvme->n_fm_cap))
3156 pci_ereport_teardown(nvme->n_dip);
3157
3158 ddi_fm_fini(nvme->n_dip);
3159 }
3160
3161 if (nvme->n_vendor != NULL)
3162 strfree(nvme->n_vendor);
3163
3164 if (nvme->n_product != NULL)
3165 strfree(nvme->n_product);
3166
3167 ddi_soft_state_free(nvme_state, instance);
3168
3169 return (DDI_SUCCESS);
3170 }
3171
3172 static int
3173 nvme_quiesce(dev_info_t *dip)
3174 {
3175 int instance;
3176 nvme_t *nvme;
3177
3178 instance = ddi_get_instance(dip);
3179
3180 nvme = ddi_get_soft_state(nvme_state, instance);
3181
3182 if (nvme == NULL)
3183 return (DDI_FAILURE);
3184
3185 nvme_shutdown(nvme, NVME_CC_SHN_ABRUPT, B_TRUE);
3186
3187 (void) nvme_reset(nvme, B_TRUE);
3188
3189 return (DDI_FAILURE);
3190 }
3191
3192 static int
3193 nvme_fill_prp(nvme_cmd_t *cmd, bd_xfer_t *xfer)
3194 {
3195 nvme_t *nvme = cmd->nc_nvme;
3196 int nprp_page, nprp;
3197 uint64_t *prp;
3198
3199 if (xfer->x_ndmac == 0)
3200 return (DDI_FAILURE);
3201
3202 cmd->nc_sqe.sqe_dptr.d_prp[0] = xfer->x_dmac.dmac_laddress;
3203 ddi_dma_nextcookie(xfer->x_dmah, &xfer->x_dmac);
3204
3205 if (xfer->x_ndmac == 1) {
3206 cmd->nc_sqe.sqe_dptr.d_prp[1] = 0;
3207 return (DDI_SUCCESS);
3208 } else if (xfer->x_ndmac == 2) {
3209 cmd->nc_sqe.sqe_dptr.d_prp[1] = xfer->x_dmac.dmac_laddress;
3210 return (DDI_SUCCESS);
3211 }
3212
3213 xfer->x_ndmac--;
3214
3215 nprp_page = nvme->n_pagesize / sizeof (uint64_t) - 1;
3216 ASSERT(nprp_page > 0);
3217 nprp = (xfer->x_ndmac + nprp_page - 1) / nprp_page;
3218
3219 /*
3220 * We currently don't support chained PRPs and set up our DMA
3221 * attributes to reflect that. If we still get an I/O request
3222 * that needs a chained PRP something is very wrong.
3223 */
3224 VERIFY(nprp == 1);
3225
3226 cmd->nc_dma = kmem_cache_alloc(nvme->n_prp_cache, KM_SLEEP);
3227 bzero(cmd->nc_dma->nd_memp, cmd->nc_dma->nd_len);
3228
3229 cmd->nc_sqe.sqe_dptr.d_prp[1] = cmd->nc_dma->nd_cookie.dmac_laddress;
3230
3231 /*LINTED: E_PTR_BAD_CAST_ALIGN*/
3232 for (prp = (uint64_t *)cmd->nc_dma->nd_memp;
3233 xfer->x_ndmac > 0;
3234 prp++, xfer->x_ndmac--) {
3235 *prp = xfer->x_dmac.dmac_laddress;
3236 ddi_dma_nextcookie(xfer->x_dmah, &xfer->x_dmac);
3237 }
3238
3239 (void) ddi_dma_sync(cmd->nc_dma->nd_dmah, 0, cmd->nc_dma->nd_len,
3240 DDI_DMA_SYNC_FORDEV);
3241 return (DDI_SUCCESS);
3242 }
3243
3244 static nvme_cmd_t *
3245 nvme_create_nvm_cmd(nvme_namespace_t *ns, uint8_t opc, bd_xfer_t *xfer)
3246 {
3247 nvme_t *nvme = ns->ns_nvme;
3248 nvme_cmd_t *cmd;
3249
3250 /*
3251 * Blkdev only sets BD_XFER_POLL when dumping, so don't sleep.
3252 */
3253 cmd = nvme_alloc_cmd(nvme, (xfer->x_flags & BD_XFER_POLL) ?
3254 KM_NOSLEEP : KM_SLEEP);
3255
3256 if (cmd == NULL)
3257 return (NULL);
3258
3259 cmd->nc_sqe.sqe_opc = opc;
3260 cmd->nc_callback = nvme_bd_xfer_done;
3261 cmd->nc_xfer = xfer;
3262
3263 switch (opc) {
3264 case NVME_OPC_NVM_WRITE:
3265 case NVME_OPC_NVM_READ:
3266 VERIFY(xfer->x_nblks <= 0x10000);
3267
3268 cmd->nc_sqe.sqe_nsid = ns->ns_id;
3269
3270 cmd->nc_sqe.sqe_cdw10 = xfer->x_blkno & 0xffffffffu;
3271 cmd->nc_sqe.sqe_cdw11 = (xfer->x_blkno >> 32);
3272 cmd->nc_sqe.sqe_cdw12 = (uint16_t)(xfer->x_nblks - 1);
3273
3274 if (nvme_fill_prp(cmd, xfer) != DDI_SUCCESS)
3275 goto fail;
3276 break;
3277
3278 case NVME_OPC_NVM_FLUSH:
3279 cmd->nc_sqe.sqe_nsid = ns->ns_id;
3280 break;
3281
3282 default:
3283 goto fail;
3284 }
3285
3286 return (cmd);
3287
3288 fail:
3289 nvme_free_cmd(cmd);
3290 return (NULL);
3291 }
3292
3293 static void
3294 nvme_bd_xfer_done(void *arg)
3295 {
3296 nvme_cmd_t *cmd = arg;
3297 bd_xfer_t *xfer = cmd->nc_xfer;
3298 int error = 0;
3299
3300 error = nvme_check_cmd_status(cmd);
3301 nvme_free_cmd(cmd);
3302
3303 bd_xfer_done(xfer, error);
3304 }
3305
3306 static void
3307 nvme_bd_driveinfo(void *arg, bd_drive_t *drive)
3308 {
3309 nvme_namespace_t *ns = arg;
3310 nvme_t *nvme = ns->ns_nvme;
3311
3312 /*
3313 * blkdev maintains one queue size per instance (namespace),
3314 * but all namespace share the I/O queues.
3315 * TODO: need to figure out a sane default, or use per-NS I/O queues,
3316 * or change blkdev to handle EAGAIN
3317 */
3318 drive->d_qsize = nvme->n_ioq_count * nvme->n_io_queue_len
3319 / nvme->n_namespace_count;
3320
3321 /*
3322 * d_maxxfer is not set, which means the value is taken from the DMA
3323 * attributes specified to bd_alloc_handle.
3324 */
3325
3326 drive->d_removable = B_FALSE;
3327 drive->d_hotpluggable = B_FALSE;
3328
3329 bcopy(ns->ns_eui64, drive->d_eui64, sizeof (drive->d_eui64));
3330 drive->d_target = ns->ns_id;
3331 drive->d_lun = 0;
3332
3333 drive->d_model = nvme->n_idctl->id_model;
3334 drive->d_model_len = sizeof (nvme->n_idctl->id_model);
3335 drive->d_vendor = nvme->n_vendor;
3336 drive->d_vendor_len = strlen(nvme->n_vendor);
3337 drive->d_product = nvme->n_product;
3338 drive->d_product_len = strlen(nvme->n_product);
3339 drive->d_serial = nvme->n_idctl->id_serial;
3340 drive->d_serial_len = sizeof (nvme->n_idctl->id_serial);
3341 drive->d_revision = nvme->n_idctl->id_fwrev;
3342 drive->d_revision_len = sizeof (nvme->n_idctl->id_fwrev);
3343 }
3344
3345 static int
3346 nvme_bd_mediainfo(void *arg, bd_media_t *media)
3347 {
3348 nvme_namespace_t *ns = arg;
3349
3350 media->m_nblks = ns->ns_block_count;
3351 media->m_blksize = ns->ns_block_size;
3352 media->m_readonly = B_FALSE;
3353 media->m_solidstate = B_TRUE;
3354
3355 media->m_pblksize = ns->ns_best_block_size;
3356
3357 return (0);
3358 }
3359
3360 static int
3361 nvme_bd_cmd(nvme_namespace_t *ns, bd_xfer_t *xfer, uint8_t opc)
3362 {
3363 nvme_t *nvme = ns->ns_nvme;
3364 nvme_cmd_t *cmd;
3365 nvme_qpair_t *ioq;
3366 boolean_t poll;
3367 int ret;
3368
3369 if (nvme->n_dead)
3370 return (EIO);
3371
3372 cmd = nvme_create_nvm_cmd(ns, opc, xfer);
3373 if (cmd == NULL)
3374 return (ENOMEM);
3375
3376 cmd->nc_sqid = (CPU->cpu_id % nvme->n_ioq_count) + 1;
3377 ASSERT(cmd->nc_sqid <= nvme->n_ioq_count);
3378 ioq = nvme->n_ioq[cmd->nc_sqid];
3379
3380 /*
3381 * Get the polling flag before submitting the command. The command may
3382 * complete immediately after it was submitted, which means we must
3383 * treat both cmd and xfer as if they have been freed already.
3384 */
3385 poll = (xfer->x_flags & BD_XFER_POLL) != 0;
3386
3387 ret = nvme_submit_io_cmd(ioq, cmd);
3388
3389 if (ret != 0)
3390 return (ret);
3391
3392 if (!poll)
3393 return (0);
3394
3395 do {
3396 cmd = nvme_retrieve_cmd(nvme, ioq);
3397 if (cmd != NULL)
3398 nvme_bd_xfer_done(cmd);
3399 else
3400 drv_usecwait(10);
3401 } while (ioq->nq_active_cmds != 0);
3402
3403 return (0);
3404 }
3405
3406 static int
3407 nvme_bd_read(void *arg, bd_xfer_t *xfer)
3408 {
3409 nvme_namespace_t *ns = arg;
3410
3411 return (nvme_bd_cmd(ns, xfer, NVME_OPC_NVM_READ));
3412 }
3413
3414 static int
3415 nvme_bd_write(void *arg, bd_xfer_t *xfer)
3416 {
3417 nvme_namespace_t *ns = arg;
3418
3419 return (nvme_bd_cmd(ns, xfer, NVME_OPC_NVM_WRITE));
3420 }
3421
3422 static int
3423 nvme_bd_sync(void *arg, bd_xfer_t *xfer)
3424 {
3425 nvme_namespace_t *ns = arg;
3426
3427 if (ns->ns_nvme->n_dead)
3428 return (EIO);
3429
3430 /*
3431 * If the volatile write cache is not present or not enabled the FLUSH
3432 * command is a no-op, so we can take a shortcut here.
3433 */
3434 if (!ns->ns_nvme->n_write_cache_present) {
3435 bd_xfer_done(xfer, ENOTSUP);
3436 return (0);
3437 }
3438
3439 if (!ns->ns_nvme->n_write_cache_enabled) {
3440 bd_xfer_done(xfer, 0);
3441 return (0);
3442 }
3443
3444 return (nvme_bd_cmd(ns, xfer, NVME_OPC_NVM_FLUSH));
3445 }
3446
3447 static int
3448 nvme_bd_devid(void *arg, dev_info_t *devinfo, ddi_devid_t *devid)
3449 {
3450 nvme_namespace_t *ns = arg;
3451
3452 /*LINTED: E_BAD_PTR_CAST_ALIGN*/
3453 if (*(uint64_t *)ns->ns_eui64 != 0) {
3454 return (ddi_devid_init(devinfo, DEVID_SCSI3_WWN,
3455 sizeof (ns->ns_eui64), ns->ns_eui64, devid));
3456 } else {
3457 return (ddi_devid_init(devinfo, DEVID_ENCAP,
3458 strlen(ns->ns_devid), ns->ns_devid, devid));
3459 }
3460 }
3461
3462 static int
3463 nvme_open(dev_t *devp, int flag, int otyp, cred_t *cred_p)
3464 {
3465 #ifndef __lock_lint
3466 _NOTE(ARGUNUSED(cred_p));
3467 #endif
3468 minor_t minor = getminor(*devp);
3469 nvme_t *nvme = ddi_get_soft_state(nvme_state, NVME_MINOR_INST(minor));
3470 int nsid = NVME_MINOR_NSID(minor);
3471 nvme_minor_state_t *nm;
3472 int rv = 0;
3473
3474 if (otyp != OTYP_CHR)
3475 return (EINVAL);
3476
3477 if (nvme == NULL)
3478 return (ENXIO);
3479
3480 if (nsid > nvme->n_namespace_count)
3481 return (ENXIO);
3482
3483 if (nvme->n_dead)
3484 return (EIO);
3485
3486 nm = nsid == 0 ? &nvme->n_minor : &nvme->n_ns[nsid - 1].ns_minor;
3487
3488 mutex_enter(&nm->nm_mutex);
3489 if (nm->nm_oexcl) {
3490 rv = EBUSY;
3491 goto out;
3492 }
3493
3494 if (flag & FEXCL) {
3495 if (nm->nm_ocnt != 0) {
3496 rv = EBUSY;
3497 goto out;
3498 }
3499 nm->nm_oexcl = B_TRUE;
3500 }
3501
3502 nm->nm_ocnt++;
3503
3504 out:
3505 mutex_exit(&nm->nm_mutex);
3506 return (rv);
3507
3508 }
3509
3510 static int
3511 nvme_close(dev_t dev, int flag, int otyp, cred_t *cred_p)
3512 {
3513 #ifndef __lock_lint
3514 _NOTE(ARGUNUSED(cred_p));
3515 _NOTE(ARGUNUSED(flag));
3516 #endif
3517 minor_t minor = getminor(dev);
3518 nvme_t *nvme = ddi_get_soft_state(nvme_state, NVME_MINOR_INST(minor));
3519 int nsid = NVME_MINOR_NSID(minor);
3520 nvme_minor_state_t *nm;
3521
3522 if (otyp != OTYP_CHR)
3523 return (ENXIO);
3524
3525 if (nvme == NULL)
3526 return (ENXIO);
3527
3528 if (nsid > nvme->n_namespace_count)
3529 return (ENXIO);
3530
3531 nm = nsid == 0 ? &nvme->n_minor : &nvme->n_ns[nsid - 1].ns_minor;
3532
3533 mutex_enter(&nm->nm_mutex);
3534 if (nm->nm_oexcl)
3535 nm->nm_oexcl = B_FALSE;
3536
3537 ASSERT(nm->nm_ocnt > 0);
3538 nm->nm_ocnt--;
3539 mutex_exit(&nm->nm_mutex);
3540
3541 return (0);
3542 }
3543
3544 static int
3545 nvme_ioctl_identify(nvme_t *nvme, int nsid, nvme_ioctl_t *nioc, int mode,
3546 cred_t *cred_p)
3547 {
3548 _NOTE(ARGUNUSED(cred_p));
3549 int rv = 0;
3550 void *idctl;
3551
3552 if ((mode & FREAD) == 0)
3553 return (EPERM);
3554
3555 if (nioc->n_len < NVME_IDENTIFY_BUFSIZE)
3556 return (EINVAL);
3557
3558 if ((rv = nvme_identify(nvme, nsid, (void **)&idctl)) != 0)
3559 return (rv);
3560
3561 if (ddi_copyout(idctl, (void *)nioc->n_buf, NVME_IDENTIFY_BUFSIZE, mode)
3562 != 0)
3563 rv = EFAULT;
3564
3565 kmem_free(idctl, NVME_IDENTIFY_BUFSIZE);
3566
3567 return (rv);
3568 }
3569
3570 static int
3571 nvme_ioctl_capabilities(nvme_t *nvme, int nsid, nvme_ioctl_t *nioc,
3572 int mode, cred_t *cred_p)
3573 {
3574 _NOTE(ARGUNUSED(nsid, cred_p));
3575 int rv = 0;
3576 nvme_reg_cap_t cap = { 0 };
3577 nvme_capabilities_t nc;
3578
3579 if ((mode & FREAD) == 0)
3580 return (EPERM);
3581
3582 if (nioc->n_len < sizeof (nc))
3583 return (EINVAL);
3584
3585 cap.r = nvme_get64(nvme, NVME_REG_CAP);
3586
3587 /*
3588 * The MPSMIN and MPSMAX fields in the CAP register use 0 to
3589 * specify the base page size of 4k (1<<12), so add 12 here to
3590 * get the real page size value.
3591 */
3592 nc.mpsmax = 1 << (12 + cap.b.cap_mpsmax);
3593 nc.mpsmin = 1 << (12 + cap.b.cap_mpsmin);
3594
3595 if (ddi_copyout(&nc, (void *)nioc->n_buf, sizeof (nc), mode) != 0)
3596 rv = EFAULT;
3597
3598 return (rv);
3599 }
3600
3601 static int
3602 nvme_ioctl_get_logpage(nvme_t *nvme, int nsid, nvme_ioctl_t *nioc,
3603 int mode, cred_t *cred_p)
3604 {
3605 _NOTE(ARGUNUSED(cred_p));
3606 void *log = NULL;
3607 size_t bufsize = 0;
3608 int rv = 0;
3609
3610 if ((mode & FREAD) == 0)
3611 return (EPERM);
3612
3613 switch (nioc->n_arg) {
3614 case NVME_LOGPAGE_ERROR:
3615 if (nsid != 0)
3616 return (EINVAL);
3617 break;
3618 case NVME_LOGPAGE_HEALTH:
3619 if (nsid != 0 && nvme->n_idctl->id_lpa.lp_smart == 0)
3620 return (EINVAL);
3621
3622 if (nsid == 0)
3623 nsid = (uint32_t)-1;
3624
3625 break;
3626 case NVME_LOGPAGE_FWSLOT:
3627 if (nsid != 0)
3628 return (EINVAL);
3629 break;
3630 default:
3631 return (EINVAL);
3632 }
3633
3634 if (nvme_get_logpage(nvme, &log, &bufsize, nioc->n_arg, nsid)
3635 != DDI_SUCCESS)
3636 return (EIO);
3637
3638 if (nioc->n_len < bufsize) {
3639 kmem_free(log, bufsize);
3640 return (EINVAL);
3641 }
3642
3643 if (ddi_copyout(log, (void *)nioc->n_buf, bufsize, mode) != 0)
3644 rv = EFAULT;
3645
3646 nioc->n_len = bufsize;
3647 kmem_free(log, bufsize);
3648
3649 return (rv);
3650 }
3651
3652 static int
3653 nvme_ioctl_get_features(nvme_t *nvme, int nsid, nvme_ioctl_t *nioc,
3654 int mode, cred_t *cred_p)
3655 {
3656 _NOTE(ARGUNUSED(cred_p));
3657 void *buf = NULL;
3658 size_t bufsize = 0;
3659 uint32_t res = 0;
3660 uint8_t feature;
3661 int rv = 0;
3662
3663 if ((mode & FREAD) == 0)
3664 return (EPERM);
3665
3666 if ((nioc->n_arg >> 32) > 0xff)
3667 return (EINVAL);
3668
3669 feature = (uint8_t)(nioc->n_arg >> 32);
3670
3671 switch (feature) {
3672 case NVME_FEAT_ARBITRATION:
3673 case NVME_FEAT_POWER_MGMT:
3674 case NVME_FEAT_TEMPERATURE:
3675 case NVME_FEAT_ERROR:
3676 case NVME_FEAT_NQUEUES:
3677 case NVME_FEAT_INTR_COAL:
3678 case NVME_FEAT_WRITE_ATOM:
3679 case NVME_FEAT_ASYNC_EVENT:
3680 case NVME_FEAT_PROGRESS:
3681 if (nsid != 0)
3682 return (EINVAL);
3683 break;
3684
3685 case NVME_FEAT_INTR_VECT:
3686 if (nsid != 0)
3687 return (EINVAL);
3688
3689 res = nioc->n_arg & 0xffffffffUL;
3690 if (res >= nvme->n_intr_cnt)
3691 return (EINVAL);
3692 break;
3693
3694 case NVME_FEAT_LBA_RANGE:
3695 if (nvme->n_lba_range_supported == B_FALSE)
3696 return (EINVAL);
3697
3698 if (nsid == 0 ||
3699 nsid > nvme->n_namespace_count)
3700 return (EINVAL);
3701
3702 break;
3703
3704 case NVME_FEAT_WRITE_CACHE:
3705 if (nsid != 0)
3706 return (EINVAL);
3707
3708 if (!nvme->n_write_cache_present)
3709 return (EINVAL);
3710
3711 break;
3712
3713 case NVME_FEAT_AUTO_PST:
3714 if (nsid != 0)
3715 return (EINVAL);
3716
3717 if (!nvme->n_auto_pst_supported)
3718 return (EINVAL);
3719
3720 break;
3721
3722 default:
3723 return (EINVAL);
3724 }
3725
3726 rv = nvme_get_features(nvme, nsid, feature, &res, &buf, &bufsize);
3727 if (rv != 0)
3728 return (rv);
3729
3730 if (nioc->n_len < bufsize) {
3731 kmem_free(buf, bufsize);
3732 return (EINVAL);
3733 }
3734
3735 if (buf && ddi_copyout(buf, (void*)nioc->n_buf, bufsize, mode) != 0)
3736 rv = EFAULT;
3737
3738 kmem_free(buf, bufsize);
3739 nioc->n_arg = res;
3740 nioc->n_len = bufsize;
3741
3742 return (rv);
3743 }
3744
3745 static int
3746 nvme_ioctl_intr_cnt(nvme_t *nvme, int nsid, nvme_ioctl_t *nioc, int mode,
3747 cred_t *cred_p)
3748 {
3749 _NOTE(ARGUNUSED(nsid, mode, cred_p));
3750
3751 if ((mode & FREAD) == 0)
3752 return (EPERM);
3753
3754 nioc->n_arg = nvme->n_intr_cnt;
3755 return (0);
3756 }
3757
3758 static int
3759 nvme_ioctl_version(nvme_t *nvme, int nsid, nvme_ioctl_t *nioc, int mode,
3760 cred_t *cred_p)
3761 {
3762 _NOTE(ARGUNUSED(nsid, cred_p));
3763 int rv = 0;
3764
3765 if ((mode & FREAD) == 0)
3766 return (EPERM);
3767
3768 if (nioc->n_len < sizeof (nvme->n_version))
3769 return (ENOMEM);
3770
3771 if (ddi_copyout(&nvme->n_version, (void *)nioc->n_buf,
3772 sizeof (nvme->n_version), mode) != 0)
3773 rv = EFAULT;
3774
3775 return (rv);
3776 }
3777
3778 static int
3779 nvme_ioctl_format(nvme_t *nvme, int nsid, nvme_ioctl_t *nioc, int mode,
3780 cred_t *cred_p)
3781 {
3782 _NOTE(ARGUNUSED(mode));
3783 nvme_format_nvm_t frmt = { 0 };
3784 int c_nsid = nsid != 0 ? nsid - 1 : 0;
3785
3786 if ((mode & FWRITE) == 0 || secpolicy_sys_config(cred_p, B_FALSE) != 0)
3787 return (EPERM);
3788
3789 frmt.r = nioc->n_arg & 0xffffffff;
3790
3791 /*
3792 * Check whether the FORMAT NVM command is supported.
3793 */
3794 if (nvme->n_idctl->id_oacs.oa_format == 0)
3795 return (EINVAL);
3796
3797 /*
3798 * Don't allow format or secure erase of individual namespace if that
3799 * would cause a format or secure erase of all namespaces.
3800 */
3801 if (nsid != 0 && nvme->n_idctl->id_fna.fn_format != 0)
3802 return (EINVAL);
3803
3804 if (nsid != 0 && frmt.b.fm_ses != NVME_FRMT_SES_NONE &&
3805 nvme->n_idctl->id_fna.fn_sec_erase != 0)
3806 return (EINVAL);
3807
3808 /*
3809 * Don't allow formatting with Protection Information.
3810 */
3811 if (frmt.b.fm_pi != 0 || frmt.b.fm_pil != 0 || frmt.b.fm_ms != 0)
3812 return (EINVAL);
3813
3814 /*
3815 * Don't allow formatting using an illegal LBA format, or any LBA format
3816 * that uses metadata.
3817 */
3818 if (frmt.b.fm_lbaf > nvme->n_ns[c_nsid].ns_idns->id_nlbaf ||
3819 nvme->n_ns[c_nsid].ns_idns->id_lbaf[frmt.b.fm_lbaf].lbaf_ms != 0)
3820 return (EINVAL);
3821
3822 /*
3823 * Don't allow formatting using an illegal Secure Erase setting.
3824 */
3825 if (frmt.b.fm_ses > NVME_FRMT_MAX_SES ||
3826 (frmt.b.fm_ses == NVME_FRMT_SES_CRYPTO &&
3827 nvme->n_idctl->id_fna.fn_crypt_erase == 0))
3828 return (EINVAL);
3829
3830 if (nsid == 0)
3831 nsid = (uint32_t)-1;
3832
3833 return (nvme_format_nvm(nvme, nsid, frmt.b.fm_lbaf, B_FALSE, 0, B_FALSE,
3834 frmt.b.fm_ses));
3835 }
3836
3837 static int
3838 nvme_ioctl_detach(nvme_t *nvme, int nsid, nvme_ioctl_t *nioc, int mode,
3839 cred_t *cred_p)
3840 {
3841 _NOTE(ARGUNUSED(nioc, mode));
3842 int rv = 0;
3843
3844 if ((mode & FWRITE) == 0 || secpolicy_sys_config(cred_p, B_FALSE) != 0)
3845 return (EPERM);
3846
3847 if (nsid == 0)
3848 return (EINVAL);
3849
3850 rv = bd_detach_handle(nvme->n_ns[nsid - 1].ns_bd_hdl);
3851 if (rv != DDI_SUCCESS)
3852 rv = EBUSY;
3853
3854 return (rv);
3855 }
3856
3857 static int
3858 nvme_ioctl_attach(nvme_t *nvme, int nsid, nvme_ioctl_t *nioc, int mode,
3859 cred_t *cred_p)
3860 {
3861 _NOTE(ARGUNUSED(nioc, mode));
3862 nvme_identify_nsid_t *idns;
3863 int rv = 0;
3864
3865 if ((mode & FWRITE) == 0 || secpolicy_sys_config(cred_p, B_FALSE) != 0)
3866 return (EPERM);
3867
3868 if (nsid == 0)
3869 return (EINVAL);
3870
3871 /*
3872 * Identify namespace again, free old identify data.
3873 */
3874 idns = nvme->n_ns[nsid - 1].ns_idns;
3875 if (nvme_init_ns(nvme, nsid) != DDI_SUCCESS)
3876 return (EIO);
3877
3878 kmem_free(idns, sizeof (nvme_identify_nsid_t));
3879
3880 rv = bd_attach_handle(nvme->n_dip, nvme->n_ns[nsid - 1].ns_bd_hdl);
3881 if (rv != DDI_SUCCESS)
3882 rv = EBUSY;
3883
3884 return (rv);
3885 }
3886
3887 static int
3888 nvme_ioctl(dev_t dev, int cmd, intptr_t arg, int mode, cred_t *cred_p,
3889 int *rval_p)
3890 {
3891 #ifndef __lock_lint
3892 _NOTE(ARGUNUSED(rval_p));
3893 #endif
3894 minor_t minor = getminor(dev);
3895 nvme_t *nvme = ddi_get_soft_state(nvme_state, NVME_MINOR_INST(minor));
3896 int nsid = NVME_MINOR_NSID(minor);
3897 int rv = 0;
3898 nvme_ioctl_t nioc;
3899
3900 int (*nvme_ioctl[])(nvme_t *, int, nvme_ioctl_t *, int, cred_t *) = {
3901 NULL,
3902 nvme_ioctl_identify,
3903 nvme_ioctl_identify,
3904 nvme_ioctl_capabilities,
3905 nvme_ioctl_get_logpage,
3906 nvme_ioctl_get_features,
3907 nvme_ioctl_intr_cnt,
3908 nvme_ioctl_version,
3909 nvme_ioctl_format,
3910 nvme_ioctl_detach,
3911 nvme_ioctl_attach
3912 };
3913
3914 if (nvme == NULL)
3915 return (ENXIO);
3916
3917 if (nsid > nvme->n_namespace_count)
3918 return (ENXIO);
3919
3920 if (IS_DEVCTL(cmd))
3921 return (ndi_devctl_ioctl(nvme->n_dip, cmd, arg, mode, 0));
3922
3923 #ifdef _MULTI_DATAMODEL
3924 switch (ddi_model_convert_from(mode & FMODELS)) {
3925 case DDI_MODEL_ILP32: {
3926 nvme_ioctl32_t nioc32;
3927 if (ddi_copyin((void*)arg, &nioc32, sizeof (nvme_ioctl32_t),
3928 mode) != 0)
3929 return (EFAULT);
3930 nioc.n_len = nioc32.n_len;
3931 nioc.n_buf = nioc32.n_buf;
3932 nioc.n_arg = nioc32.n_arg;
3933 break;
3934 }
3935 case DDI_MODEL_NONE:
3936 #endif
3937 if (ddi_copyin((void*)arg, &nioc, sizeof (nvme_ioctl_t), mode)
3938 != 0)
3939 return (EFAULT);
3940 #ifdef _MULTI_DATAMODEL
3941 break;
3942 }
3943 #endif
3944
3945 if (nvme->n_dead && cmd != NVME_IOC_DETACH)
3946 return (EIO);
3947
3948
3949 if (cmd == NVME_IOC_IDENTIFY_CTRL) {
3950 /*
3951 * This makes NVME_IOC_IDENTIFY_CTRL work the same on devctl and
3952 * attachment point nodes.
3953 */
3954 nsid = 0;
3955 } else if (cmd == NVME_IOC_IDENTIFY_NSID && nsid == 0) {
3956 /*
3957 * This makes NVME_IOC_IDENTIFY_NSID work on a devctl node, it
3958 * will always return identify data for namespace 1.
3959 */
3960 nsid = 1;
3961 }
3962
3963 if (IS_NVME_IOC(cmd) && nvme_ioctl[NVME_IOC_CMD(cmd)] != NULL)
3964 rv = nvme_ioctl[NVME_IOC_CMD(cmd)](nvme, nsid, &nioc, mode,
3965 cred_p);
3966 else
3967 rv = EINVAL;
3968
3969 #ifdef _MULTI_DATAMODEL
3970 switch (ddi_model_convert_from(mode & FMODELS)) {
3971 case DDI_MODEL_ILP32: {
3972 nvme_ioctl32_t nioc32;
3973
3974 nioc32.n_len = (size32_t)nioc.n_len;
3975 nioc32.n_buf = (uintptr32_t)nioc.n_buf;
3976 nioc32.n_arg = nioc.n_arg;
3977
3978 if (ddi_copyout(&nioc32, (void *)arg, sizeof (nvme_ioctl32_t),
3979 mode) != 0)
3980 return (EFAULT);
3981 break;
3982 }
3983 case DDI_MODEL_NONE:
3984 #endif
3985 if (ddi_copyout(&nioc, (void *)arg, sizeof (nvme_ioctl_t), mode)
3986 != 0)
3987 return (EFAULT);
3988 #ifdef _MULTI_DATAMODEL
3989 break;
3990 }
3991 #endif
3992
3993 return (rv);
3994 }