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9095 ixgbe MAC_CAPAB_LED support
Reviewed by: Jerry Jelinek <jerry.jelinek@joyent.com>
Reviewed by: Sebastian Wiedenroth <sebastian.wiedenroth@skylime.net>
Reviewed by: Toomas Soome <tsoome@me.com>
Approved by: Dan McDonald <danmcd@joyent.com>
SUP-479 10 Gigabit CX4 Dual Port Server Adapter EXPX9502CX4 unresponsive to external pings after upgrade from 3.1.2 to 3.1.3.5
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--- old/usr/src/uts/common/io/ixgbe/ixgbe_gld.c
+++ new/usr/src/uts/common/io/ixgbe/ixgbe_gld.c
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
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18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21
22 22 /*
23 23 * Copyright(c) 2007-2010 Intel Corporation. All rights reserved.
24 24 */
25 25
26 26 /*
27 27 * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved.
28 - * Copyright 2012 Nexenta Systems, Inc. All rights reserved.
28 + * Copyright 2013 Nexenta Systems, Inc. All rights reserved.
29 29 * Copyright 2016 OmniTI Computer Consulting, Inc. All rights reserved.
30 30 * Copyright (c) 2017, Joyent, Inc.
31 31 */
32 32
33 33 #include "ixgbe_sw.h"
34 34
35 35 /*
36 36 * Bring the device out of the reset/quiesced state that it
37 37 * was in when the interface was registered.
38 38 */
39 39 int
40 40 ixgbe_m_start(void *arg)
41 41 {
42 42 ixgbe_t *ixgbe = (ixgbe_t *)arg;
43 43
44 44 mutex_enter(&ixgbe->gen_lock);
45 45
46 46 if (ixgbe->ixgbe_state & IXGBE_SUSPENDED) {
47 47 mutex_exit(&ixgbe->gen_lock);
48 48 return (ECANCELED);
49 49 }
50 50
51 51 if (ixgbe_start(ixgbe, B_TRUE) != IXGBE_SUCCESS) {
52 52 mutex_exit(&ixgbe->gen_lock);
53 53 return (EIO);
54 54 }
55 55
56 56 atomic_or_32(&ixgbe->ixgbe_state, IXGBE_STARTED);
57 57
58 58 mutex_exit(&ixgbe->gen_lock);
59 59
60 60 /*
61 61 * Enable and start the watchdog timer
62 62 */
63 63 ixgbe_enable_watchdog_timer(ixgbe);
64 64
65 65 return (0);
66 66 }
67 67
68 68 /*
69 69 * Stop the device and put it in a reset/quiesced state such
70 70 * that the interface can be unregistered.
71 71 */
72 72 void
73 73 ixgbe_m_stop(void *arg)
74 74 {
75 75 ixgbe_t *ixgbe = (ixgbe_t *)arg;
76 76
77 77 mutex_enter(&ixgbe->gen_lock);
78 78
79 79 if (ixgbe->ixgbe_state & IXGBE_SUSPENDED) {
80 80 mutex_exit(&ixgbe->gen_lock);
81 81 return;
82 82 }
83 83
84 84 atomic_and_32(&ixgbe->ixgbe_state, ~IXGBE_STARTED);
85 85
86 86 ixgbe_stop(ixgbe, B_TRUE);
87 87
88 88 mutex_exit(&ixgbe->gen_lock);
89 89
90 90 /*
91 91 * Disable and stop the watchdog timer
92 92 */
93 93 ixgbe_disable_watchdog_timer(ixgbe);
94 94 }
95 95
96 96 /*
97 97 * Set the promiscuity of the device.
98 98 */
99 99 int
100 100 ixgbe_m_promisc(void *arg, boolean_t on)
101 101 {
102 102 ixgbe_t *ixgbe = (ixgbe_t *)arg;
103 103 uint32_t reg_val;
104 104 struct ixgbe_hw *hw = &ixgbe->hw;
105 105
106 106 mutex_enter(&ixgbe->gen_lock);
107 107
108 108 if (ixgbe->ixgbe_state & IXGBE_SUSPENDED) {
109 109 mutex_exit(&ixgbe->gen_lock);
110 110 return (ECANCELED);
111 111 }
112 112 reg_val = IXGBE_READ_REG(hw, IXGBE_FCTRL);
113 113
114 114 if (on)
115 115 reg_val |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
116 116 else
117 117 reg_val &= (~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE));
118 118
119 119 IXGBE_WRITE_REG(&ixgbe->hw, IXGBE_FCTRL, reg_val);
120 120
121 121 mutex_exit(&ixgbe->gen_lock);
122 122
123 123 return (0);
124 124 }
125 125
126 126 /*
127 127 * Add/remove the addresses to/from the set of multicast
128 128 * addresses for which the device will receive packets.
129 129 */
130 130 int
131 131 ixgbe_m_multicst(void *arg, boolean_t add, const uint8_t *mcst_addr)
132 132 {
133 133 ixgbe_t *ixgbe = (ixgbe_t *)arg;
134 134 int result;
135 135
136 136 mutex_enter(&ixgbe->gen_lock);
137 137
138 138 if (ixgbe->ixgbe_state & IXGBE_SUSPENDED) {
139 139 mutex_exit(&ixgbe->gen_lock);
140 140 return (ECANCELED);
141 141 }
142 142
143 143 result = (add) ? ixgbe_multicst_add(ixgbe, mcst_addr)
144 144 : ixgbe_multicst_remove(ixgbe, mcst_addr);
145 145
146 146 mutex_exit(&ixgbe->gen_lock);
147 147
148 148 return (result);
149 149 }
150 150
151 151 /*
152 152 * Pass on M_IOCTL messages passed to the DLD, and support
153 153 * private IOCTLs for debugging and ndd.
154 154 */
155 155 void
156 156 ixgbe_m_ioctl(void *arg, queue_t *q, mblk_t *mp)
157 157 {
158 158 ixgbe_t *ixgbe = (ixgbe_t *)arg;
159 159 struct iocblk *iocp;
160 160 enum ioc_reply status;
161 161
162 162 iocp = (struct iocblk *)(uintptr_t)mp->b_rptr;
163 163 iocp->ioc_error = 0;
164 164
165 165 mutex_enter(&ixgbe->gen_lock);
166 166 if (ixgbe->ixgbe_state & IXGBE_SUSPENDED) {
167 167 mutex_exit(&ixgbe->gen_lock);
168 168 miocnak(q, mp, 0, EINVAL);
169 169 return;
170 170 }
171 171 mutex_exit(&ixgbe->gen_lock);
172 172
173 173 switch (iocp->ioc_cmd) {
174 174 case LB_GET_INFO_SIZE:
175 175 case LB_GET_INFO:
176 176 case LB_GET_MODE:
177 177 case LB_SET_MODE:
178 178 status = ixgbe_loopback_ioctl(ixgbe, iocp, mp);
179 179 break;
180 180
181 181 default:
182 182 status = IOC_INVAL;
183 183 break;
184 184 }
185 185
186 186 /*
187 187 * Decide how to reply
188 188 */
189 189 switch (status) {
190 190 default:
191 191 case IOC_INVAL:
192 192 /*
193 193 * Error, reply with a NAK and EINVAL or the specified error
194 194 */
195 195 miocnak(q, mp, 0, iocp->ioc_error == 0 ?
196 196 EINVAL : iocp->ioc_error);
197 197 break;
198 198
199 199 case IOC_DONE:
200 200 /*
201 201 * OK, reply already sent
202 202 */
203 203 break;
204 204
205 205 case IOC_ACK:
206 206 /*
207 207 * OK, reply with an ACK
208 208 */
209 209 miocack(q, mp, 0, 0);
210 210 break;
211 211
212 212 case IOC_REPLY:
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213 213 /*
214 214 * OK, send prepared reply as ACK or NAK
215 215 */
216 216 mp->b_datap->db_type = iocp->ioc_error == 0 ?
217 217 M_IOCACK : M_IOCNAK;
218 218 qreply(q, mp);
219 219 break;
220 220 }
221 221 }
222 222
223 +static int
224 +ixgbe_led_set(void *arg, mac_led_mode_t mode, uint_t flags)
225 +{
226 + ixgbe_t *ixgbe = arg;
227 + struct ixgbe_hw *hw = &ixgbe->hw;
228 + uint32_t lidx = ixgbe->ixgbe_led_index;
229 +
230 + if (flags != 0)
231 + return (EINVAL);
232 +
233 + if (mode != MAC_LED_DEFAULT &&
234 + mode != MAC_LED_IDENT &&
235 + mode != MAC_LED_OFF &&
236 + mode != MAC_LED_ON)
237 + return (ENOTSUP);
238 +
239 + if (ixgbe->ixgbe_led_blink && mode != MAC_LED_IDENT) {
240 + if (ixgbe_blink_led_stop(hw, lidx) != IXGBE_SUCCESS) {
241 + return (EIO);
242 + }
243 + ixgbe->ixgbe_led_blink = B_FALSE;
244 + }
245 +
246 + if (mode != MAC_LED_DEFAULT && !ixgbe->ixgbe_led_active) {
247 + ixgbe->ixgbe_led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
248 + ixgbe->ixgbe_led_active = B_TRUE;
249 + }
250 +
251 + switch (mode) {
252 + case MAC_LED_DEFAULT:
253 + if (ixgbe->ixgbe_led_active) {
254 + IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ixgbe->ixgbe_led_reg);
255 + ixgbe->ixgbe_led_active = B_FALSE;
256 + }
257 + break;
258 + case MAC_LED_IDENT:
259 + if (ixgbe_blink_led_start(hw, lidx) != IXGBE_SUCCESS)
260 + return (EIO);
261 + ixgbe->ixgbe_led_blink = B_TRUE;
262 + break;
263 + case MAC_LED_OFF:
264 + if (ixgbe_led_off(hw, lidx) != IXGBE_SUCCESS)
265 + return (EIO);
266 + break;
267 + case MAC_LED_ON:
268 + if (ixgbe_led_on(hw, lidx) != IXGBE_SUCCESS)
269 + return (EIO);
270 + break;
271 + default:
272 + return (ENOTSUP);
273 + }
274 +
275 + return (0);
276 +}
277 +
223 278 /*
224 279 * Obtain the MAC's capabilities and associated data from
225 280 * the driver.
226 281 */
227 282 boolean_t
228 283 ixgbe_m_getcapab(void *arg, mac_capab_t cap, void *cap_data)
229 284 {
230 285 ixgbe_t *ixgbe = (ixgbe_t *)arg;
231 286
232 287 switch (cap) {
233 288 case MAC_CAPAB_HCKSUM: {
234 289 uint32_t *tx_hcksum_flags = cap_data;
235 290
236 291 /*
237 292 * We advertise our capabilities only if tx hcksum offload is
238 293 * enabled. On receive, the stack will accept checksummed
239 294 * packets anyway, even if we haven't said we can deliver
240 295 * them.
241 296 */
242 297 if (!ixgbe->tx_hcksum_enable)
243 298 return (B_FALSE);
244 299
245 300 *tx_hcksum_flags = HCKSUM_INET_PARTIAL | HCKSUM_IPHDRCKSUM;
246 301 break;
247 302 }
248 303 case MAC_CAPAB_LSO: {
249 304 mac_capab_lso_t *cap_lso = cap_data;
250 305
251 306 if (ixgbe->lso_enable) {
252 307 cap_lso->lso_flags = LSO_TX_BASIC_TCP_IPV4;
253 308 cap_lso->lso_basic_tcp_ipv4.lso_max = IXGBE_LSO_MAXLEN;
254 309 break;
255 310 } else {
256 311 return (B_FALSE);
257 312 }
258 313 }
259 314 case MAC_CAPAB_RINGS: {
260 315 mac_capab_rings_t *cap_rings = cap_data;
261 316
262 317 switch (cap_rings->mr_type) {
263 318 case MAC_RING_TYPE_RX:
264 319 cap_rings->mr_group_type = MAC_GROUP_TYPE_STATIC;
265 320 cap_rings->mr_rnum = ixgbe->num_rx_rings;
266 321 cap_rings->mr_gnum = ixgbe->num_rx_groups;
267 322 cap_rings->mr_rget = ixgbe_fill_ring;
268 323 cap_rings->mr_gget = ixgbe_fill_group;
269 324 cap_rings->mr_gaddring = NULL;
270 325 cap_rings->mr_gremring = NULL;
271 326 break;
272 327 case MAC_RING_TYPE_TX:
273 328 cap_rings->mr_group_type = MAC_GROUP_TYPE_STATIC;
274 329 cap_rings->mr_rnum = ixgbe->num_tx_rings;
275 330 cap_rings->mr_gnum = 0;
276 331 cap_rings->mr_rget = ixgbe_fill_ring;
277 332 cap_rings->mr_gget = NULL;
278 333 break;
279 334 default:
280 335 break;
281 336 }
282 337 break;
283 338 }
284 339 case MAC_CAPAB_TRANSCEIVER: {
285 340 mac_capab_transceiver_t *mct = cap_data;
286 341
287 342 /*
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288 343 * Rather than try and guess based on the media type whether or
289 344 * not we have a transceiver we can read, we instead will let
290 345 * the actual function calls figure that out for us.
291 346 */
292 347 mct->mct_flags = 0;
293 348 mct->mct_ntransceivers = 1;
294 349 mct->mct_info = ixgbe_transceiver_info;
295 350 mct->mct_read = ixgbe_transceiver_read;
296 351 return (B_TRUE);
297 352 }
353 + case MAC_CAPAB_LED: {
354 + mac_capab_led_t *mcl = cap_data;
355 +
356 + mcl->mcl_flags = 0;
357 + mcl->mcl_modes = MAC_LED_DEFAULT | MAC_LED_ON | MAC_LED_OFF |
358 + MAC_LED_IDENT;
359 + mcl->mcl_set = ixgbe_led_set;
360 + break;
361 +
362 + }
298 363 default:
299 364 return (B_FALSE);
300 365 }
301 366 return (B_TRUE);
302 367 }
303 368
304 369 int
305 370 ixgbe_m_setprop(void *arg, const char *pr_name, mac_prop_id_t pr_num,
306 371 uint_t pr_valsize, const void *pr_val)
307 372 {
308 373 ixgbe_t *ixgbe = (ixgbe_t *)arg;
309 374 struct ixgbe_hw *hw = &ixgbe->hw;
310 375 int err = 0;
311 376 uint32_t flow_control;
312 377 uint32_t cur_mtu, new_mtu;
313 378 uint32_t rx_size;
314 379 uint32_t tx_size;
315 380 ixgbe_link_speed speeds = 0;
316 381
317 382 mutex_enter(&ixgbe->gen_lock);
318 383 if (ixgbe->ixgbe_state & IXGBE_SUSPENDED) {
319 384 mutex_exit(&ixgbe->gen_lock);
320 385 return (ECANCELED);
321 386 }
322 387
323 388 /*
324 389 * We cannot always rely on the common code maintaining
325 390 * hw->phy.speeds_supported, therefore we fall back to use the recorded
326 391 * supported speeds which were obtained during instance init in
327 392 * ixgbe_init_params().
328 393 */
329 394 speeds = hw->phy.speeds_supported;
330 395 if (speeds == 0)
331 396 speeds = ixgbe->speeds_supported;
332 397
333 398 if (ixgbe->loopback_mode != IXGBE_LB_NONE &&
334 399 ixgbe_param_locked(pr_num)) {
335 400 /*
336 401 * All en_* parameters are locked (read-only)
337 402 * while the device is in any sort of loopback mode.
338 403 */
339 404 mutex_exit(&ixgbe->gen_lock);
340 405 return (EBUSY);
341 406 }
342 407
343 408 /*
344 409 * We allow speed changes only on baseT PHYs. MAC_PROP_EN_* are marked
345 410 * read-only on non-baseT PHYs.
346 411 */
347 412 switch (pr_num) {
348 413 case MAC_PROP_EN_10GFDX_CAP:
349 414 if (hw->phy.media_type == ixgbe_media_type_copper &&
350 415 speeds & IXGBE_LINK_SPEED_10GB_FULL) {
351 416 ixgbe->param_en_10000fdx_cap = *(uint8_t *)pr_val;
352 417 goto setup_link;
353 418 } else {
354 419 err = ENOTSUP;
355 420 break;
356 421 }
357 422 case MAC_PROP_EN_5000FDX_CAP:
358 423 if (hw->phy.media_type == ixgbe_media_type_copper &&
359 424 speeds & IXGBE_LINK_SPEED_5GB_FULL) {
360 425 ixgbe->param_en_5000fdx_cap = *(uint8_t *)pr_val;
361 426 goto setup_link;
362 427 } else {
363 428 err = ENOTSUP;
364 429 break;
365 430 }
366 431 case MAC_PROP_EN_2500FDX_CAP:
367 432 if (hw->phy.media_type == ixgbe_media_type_copper &&
368 433 speeds & IXGBE_LINK_SPEED_2_5GB_FULL) {
369 434 ixgbe->param_en_2500fdx_cap = *(uint8_t *)pr_val;
370 435 goto setup_link;
371 436 } else {
372 437 err = ENOTSUP;
373 438 break;
374 439 }
375 440 case MAC_PROP_EN_1000FDX_CAP:
376 441 if (hw->phy.media_type == ixgbe_media_type_copper &&
377 442 speeds & IXGBE_LINK_SPEED_1GB_FULL) {
378 443 ixgbe->param_en_1000fdx_cap = *(uint8_t *)pr_val;
379 444 goto setup_link;
380 445 } else {
381 446 err = ENOTSUP;
382 447 break;
383 448 }
384 449 case MAC_PROP_EN_100FDX_CAP:
385 450 if (hw->phy.media_type == ixgbe_media_type_copper &&
386 451 speeds & IXGBE_LINK_SPEED_100_FULL) {
387 452 ixgbe->param_en_100fdx_cap = *(uint8_t *)pr_val;
388 453 goto setup_link;
389 454 } else {
390 455 err = ENOTSUP;
391 456 break;
392 457 }
393 458 case MAC_PROP_AUTONEG:
394 459 if (ixgbe->hw.phy.media_type != ixgbe_media_type_copper) {
395 460 err = ENOTSUP;
396 461 break;
397 462 } else {
398 463 ixgbe->param_adv_autoneg_cap = *(uint8_t *)pr_val;
399 464 goto setup_link;
400 465 }
401 466 case MAC_PROP_FLOWCTRL:
402 467 bcopy(pr_val, &flow_control, sizeof (flow_control));
403 468
404 469 switch (flow_control) {
405 470 default:
406 471 err = EINVAL;
407 472 break;
408 473 case LINK_FLOWCTRL_NONE:
409 474 hw->fc.requested_mode = ixgbe_fc_none;
410 475 break;
411 476 case LINK_FLOWCTRL_RX:
412 477 hw->fc.requested_mode = ixgbe_fc_rx_pause;
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413 478 break;
414 479 case LINK_FLOWCTRL_TX:
415 480 hw->fc.requested_mode = ixgbe_fc_tx_pause;
416 481 break;
417 482 case LINK_FLOWCTRL_BI:
418 483 hw->fc.requested_mode = ixgbe_fc_full;
419 484 break;
420 485 }
421 486 setup_link:
422 487 if (err == 0) {
488 + /* Don't autoneg if forcing a value */
489 + ixgbe->hw.fc.disable_fc_autoneg = TRUE;
490 + (void) ixgbe_fc_enable(hw);
491 +
423 492 if (ixgbe_driver_setup_link(ixgbe, B_TRUE) !=
424 493 IXGBE_SUCCESS)
425 494 err = EINVAL;
426 495 }
427 496 break;
428 497 case MAC_PROP_ADV_10GFDX_CAP:
429 498 case MAC_PROP_ADV_5000FDX_CAP:
430 499 case MAC_PROP_ADV_2500FDX_CAP:
431 500 case MAC_PROP_ADV_1000FDX_CAP:
432 501 case MAC_PROP_ADV_100FDX_CAP:
433 502 case MAC_PROP_STATUS:
434 503 case MAC_PROP_SPEED:
435 504 case MAC_PROP_DUPLEX:
436 505 err = ENOTSUP; /* read-only prop. Can't set this. */
437 506 break;
438 507 case MAC_PROP_MTU:
439 508 cur_mtu = ixgbe->default_mtu;
440 509 bcopy(pr_val, &new_mtu, sizeof (new_mtu));
441 510 if (new_mtu == cur_mtu) {
442 511 err = 0;
443 512 break;
444 513 }
445 514
446 515 if (new_mtu < DEFAULT_MTU || new_mtu > ixgbe->capab->max_mtu) {
447 516 err = EINVAL;
448 517 break;
449 518 }
450 519
451 520 if (ixgbe->ixgbe_state & IXGBE_STARTED) {
452 521 err = EBUSY;
453 522 break;
454 523 }
455 524
456 525 err = mac_maxsdu_update(ixgbe->mac_hdl, new_mtu);
457 526 if (err == 0) {
458 527 ixgbe->default_mtu = new_mtu;
459 528 ixgbe->max_frame_size = ixgbe->default_mtu +
460 529 sizeof (struct ether_vlan_header) + ETHERFCSL;
461 530
462 531 /*
463 532 * Set rx buffer size
464 533 */
465 534 rx_size = ixgbe->max_frame_size + IPHDR_ALIGN_ROOM;
466 535 ixgbe->rx_buf_size = ((rx_size >> 10) + ((rx_size &
467 536 (((uint32_t)1 << 10) - 1)) > 0 ? 1 : 0)) << 10;
468 537
469 538 /*
470 539 * Set tx buffer size
471 540 */
472 541 tx_size = ixgbe->max_frame_size;
473 542 ixgbe->tx_buf_size = ((tx_size >> 10) + ((tx_size &
474 543 (((uint32_t)1 << 10) - 1)) > 0 ? 1 : 0)) << 10;
475 544 }
476 545 break;
477 546 case MAC_PROP_PRIVATE:
478 547 err = ixgbe_set_priv_prop(ixgbe, pr_name, pr_valsize, pr_val);
479 548 break;
480 549 default:
481 550 err = ENOTSUP;
482 551 break;
483 552 }
484 553 mutex_exit(&ixgbe->gen_lock);
485 554 return (err);
486 555 }
487 556
488 557 int
489 558 ixgbe_m_getprop(void *arg, const char *pr_name, mac_prop_id_t pr_num,
490 559 uint_t pr_valsize, void *pr_val)
491 560 {
492 561 ixgbe_t *ixgbe = (ixgbe_t *)arg;
493 562 struct ixgbe_hw *hw = &ixgbe->hw;
494 563 int err = 0;
495 564 uint32_t flow_control;
496 565 uint64_t tmp = 0;
497 566 ixgbe_link_speed speeds = 0;
498 567
499 568 /*
500 569 * We cannot always rely on the common code maintaining
501 570 * hw->phy.speeds_supported, therefore we fall back to use the recorded
502 571 * supported speeds which were obtained during instance init in
503 572 * ixgbe_init_params().
504 573 */
505 574 speeds = hw->phy.speeds_supported;
506 575 if (speeds == 0)
507 576 speeds = ixgbe->speeds_supported;
508 577
509 578 switch (pr_num) {
510 579 case MAC_PROP_DUPLEX:
511 580 ASSERT(pr_valsize >= sizeof (link_duplex_t));
512 581 bcopy(&ixgbe->link_duplex, pr_val,
513 582 sizeof (link_duplex_t));
514 583 break;
515 584 case MAC_PROP_SPEED:
516 585 ASSERT(pr_valsize >= sizeof (uint64_t));
517 586 tmp = ixgbe->link_speed * 1000000ull;
518 587 bcopy(&tmp, pr_val, sizeof (tmp));
519 588 break;
520 589 case MAC_PROP_AUTONEG:
521 590 *(uint8_t *)pr_val = ixgbe->param_adv_autoneg_cap;
522 591 break;
523 592 case MAC_PROP_FLOWCTRL:
524 593 ASSERT(pr_valsize >= sizeof (uint32_t));
525 594
526 595 switch (hw->fc.requested_mode) {
527 596 case ixgbe_fc_none:
528 597 flow_control = LINK_FLOWCTRL_NONE;
529 598 break;
530 599 case ixgbe_fc_rx_pause:
531 600 flow_control = LINK_FLOWCTRL_RX;
532 601 break;
533 602 case ixgbe_fc_tx_pause:
534 603 flow_control = LINK_FLOWCTRL_TX;
535 604 break;
536 605 case ixgbe_fc_full:
537 606 flow_control = LINK_FLOWCTRL_BI;
538 607 break;
539 608 }
540 609 bcopy(&flow_control, pr_val, sizeof (flow_control));
541 610 break;
542 611 case MAC_PROP_ADV_10GFDX_CAP:
543 612 if (speeds & IXGBE_LINK_SPEED_10GB_FULL)
544 613 *(uint8_t *)pr_val = ixgbe->param_adv_10000fdx_cap;
545 614 else
546 615 err = ENOTSUP;
547 616 break;
548 617 case MAC_PROP_EN_10GFDX_CAP:
549 618 if (speeds & IXGBE_LINK_SPEED_10GB_FULL)
550 619 *(uint8_t *)pr_val = ixgbe->param_en_10000fdx_cap;
551 620 else
552 621 err = ENOTSUP;
553 622 break;
554 623 case MAC_PROP_ADV_5000FDX_CAP:
555 624 if (speeds & IXGBE_LINK_SPEED_5GB_FULL)
556 625 *(uint8_t *)pr_val = ixgbe->param_adv_5000fdx_cap;
557 626 else
558 627 err = ENOTSUP;
559 628 break;
560 629 case MAC_PROP_EN_5000FDX_CAP:
561 630 if (speeds & IXGBE_LINK_SPEED_5GB_FULL)
562 631 *(uint8_t *)pr_val = ixgbe->param_en_5000fdx_cap;
563 632 else
564 633 err = ENOTSUP;
565 634 break;
566 635 case MAC_PROP_ADV_2500FDX_CAP:
567 636 if (speeds & IXGBE_LINK_SPEED_2_5GB_FULL)
568 637 *(uint8_t *)pr_val = ixgbe->param_adv_2500fdx_cap;
569 638 else
570 639 err = ENOTSUP;
571 640 break;
572 641 case MAC_PROP_EN_2500FDX_CAP:
573 642 if (speeds & IXGBE_LINK_SPEED_2_5GB_FULL)
574 643 *(uint8_t *)pr_val = ixgbe->param_en_2500fdx_cap;
575 644 else
576 645 err = ENOTSUP;
577 646 break;
578 647 case MAC_PROP_ADV_1000FDX_CAP:
579 648 if (speeds & IXGBE_LINK_SPEED_1GB_FULL)
580 649 *(uint8_t *)pr_val = ixgbe->param_adv_1000fdx_cap;
581 650 else
582 651 err = ENOTSUP;
583 652 break;
584 653 case MAC_PROP_EN_1000FDX_CAP:
585 654 if (speeds & IXGBE_LINK_SPEED_1GB_FULL)
586 655 *(uint8_t *)pr_val = ixgbe->param_en_1000fdx_cap;
587 656 else
588 657 err = ENOTSUP;
589 658 break;
590 659 case MAC_PROP_ADV_100FDX_CAP:
591 660 if (speeds & IXGBE_LINK_SPEED_100_FULL)
592 661 *(uint8_t *)pr_val = ixgbe->param_adv_100fdx_cap;
593 662 else
594 663 err = ENOTSUP;
595 664 break;
596 665 case MAC_PROP_EN_100FDX_CAP:
597 666 if (speeds & IXGBE_LINK_SPEED_100_FULL)
598 667 *(uint8_t *)pr_val = ixgbe->param_en_100fdx_cap;
599 668 else
600 669 err = ENOTSUP;
601 670 break;
602 671 case MAC_PROP_PRIVATE:
603 672 err = ixgbe_get_priv_prop(ixgbe, pr_name,
604 673 pr_valsize, pr_val);
605 674 break;
606 675 default:
607 676 err = ENOTSUP;
608 677 break;
609 678 }
610 679 return (err);
611 680 }
612 681
613 682 void
614 683 ixgbe_m_propinfo(void *arg, const char *pr_name, mac_prop_id_t pr_num,
615 684 mac_prop_info_handle_t prh)
616 685 {
617 686 ixgbe_t *ixgbe = (ixgbe_t *)arg;
618 687 struct ixgbe_hw *hw = &ixgbe->hw;
619 688 uint_t perm;
620 689 uint8_t value;
621 690 ixgbe_link_speed speeds = 0;
622 691
623 692 /*
624 693 * We cannot always rely on the common code maintaining
625 694 * hw->phy.speeds_supported, therefore we fall back to use the
626 695 * recorded supported speeds which were obtained during instance init in
627 696 * ixgbe_init_params().
628 697 */
629 698 speeds = hw->phy.speeds_supported;
630 699 if (speeds == 0)
631 700 speeds = ixgbe->speeds_supported;
632 701
633 702 switch (pr_num) {
634 703 case MAC_PROP_DUPLEX:
635 704 case MAC_PROP_SPEED:
636 705 mac_prop_info_set_perm(prh, MAC_PROP_PERM_READ);
637 706 break;
638 707
639 708 case MAC_PROP_ADV_100FDX_CAP:
640 709 mac_prop_info_set_perm(prh, MAC_PROP_PERM_READ);
641 710 value = (speeds & IXGBE_LINK_SPEED_100_FULL) ? 1 : 0;
642 711 mac_prop_info_set_default_uint8(prh, value);
643 712 break;
644 713
645 714 case MAC_PROP_ADV_1000FDX_CAP:
646 715 mac_prop_info_set_perm(prh, MAC_PROP_PERM_READ);
647 716 value = (speeds & IXGBE_LINK_SPEED_1GB_FULL) ? 1 : 0;
648 717 mac_prop_info_set_default_uint8(prh, value);
649 718 break;
650 719
651 720 case MAC_PROP_ADV_2500FDX_CAP:
652 721 mac_prop_info_set_perm(prh, MAC_PROP_PERM_READ);
653 722 value = (speeds & IXGBE_LINK_SPEED_2_5GB_FULL) ? 1 : 0;
654 723 mac_prop_info_set_default_uint8(prh, value);
655 724 break;
656 725
657 726 case MAC_PROP_ADV_5000FDX_CAP:
658 727 mac_prop_info_set_perm(prh, MAC_PROP_PERM_READ);
659 728 value = (speeds & IXGBE_LINK_SPEED_5GB_FULL) ? 1 : 0;
660 729 mac_prop_info_set_default_uint8(prh, value);
661 730 break;
662 731
663 732 case MAC_PROP_ADV_10GFDX_CAP:
664 733 mac_prop_info_set_perm(prh, MAC_PROP_PERM_READ);
665 734 value = (speeds & IXGBE_LINK_SPEED_10GB_FULL) ? 1 : 0;
666 735 mac_prop_info_set_default_uint8(prh, value);
667 736 break;
668 737
669 738 /*
670 739 * We allow speed changes only on baseT PHYs. MAC_PROP_EN_* are marked
671 740 * read-only on non-baseT (SFP) PHYs.
672 741 */
673 742 case MAC_PROP_AUTONEG:
674 743 perm = (hw->phy.media_type == ixgbe_media_type_copper) ?
675 744 MAC_PROP_PERM_RW : MAC_PROP_PERM_READ;
676 745 mac_prop_info_set_perm(prh, perm);
677 746 mac_prop_info_set_default_uint8(prh, 1);
678 747 break;
679 748
680 749 case MAC_PROP_EN_10GFDX_CAP:
681 750 if (speeds & IXGBE_LINK_SPEED_10GB_FULL) {
682 751 perm = (hw->phy.media_type == ixgbe_media_type_copper) ?
683 752 MAC_PROP_PERM_RW : MAC_PROP_PERM_READ;
684 753 mac_prop_info_set_perm(prh, perm);
685 754 mac_prop_info_set_default_uint8(prh, 1);
686 755 }
687 756 break;
688 757
689 758 case MAC_PROP_EN_5000FDX_CAP:
690 759 if (speeds & IXGBE_LINK_SPEED_5GB_FULL) {
691 760 perm = (hw->phy.media_type == ixgbe_media_type_copper) ?
692 761 MAC_PROP_PERM_RW : MAC_PROP_PERM_READ;
693 762 mac_prop_info_set_perm(prh, perm);
694 763 mac_prop_info_set_default_uint8(prh, 1);
695 764 }
696 765 break;
697 766
698 767 case MAC_PROP_EN_2500FDX_CAP:
699 768 if (speeds & IXGBE_LINK_SPEED_2_5GB_FULL) {
700 769 perm = (hw->phy.media_type == ixgbe_media_type_copper) ?
701 770 MAC_PROP_PERM_RW : MAC_PROP_PERM_READ;
702 771 mac_prop_info_set_perm(prh, perm);
703 772 mac_prop_info_set_default_uint8(prh, 1);
704 773 }
705 774 break;
706 775
707 776 case MAC_PROP_EN_1000FDX_CAP:
708 777 if (speeds & IXGBE_LINK_SPEED_1GB_FULL) {
709 778 perm = (hw->phy.media_type == ixgbe_media_type_copper) ?
710 779 MAC_PROP_PERM_RW : MAC_PROP_PERM_READ;
711 780 mac_prop_info_set_perm(prh, perm);
712 781 mac_prop_info_set_default_uint8(prh, 1);
713 782 }
714 783 break;
715 784
716 785 case MAC_PROP_EN_100FDX_CAP:
717 786 if (speeds & IXGBE_LINK_SPEED_100_FULL) {
718 787 perm = (hw->phy.media_type == ixgbe_media_type_copper) ?
719 788 MAC_PROP_PERM_RW : MAC_PROP_PERM_READ;
720 789 mac_prop_info_set_perm(prh, perm);
721 790 mac_prop_info_set_default_uint8(prh, 1);
722 791 }
723 792 break;
724 793
725 794 case MAC_PROP_FLOWCTRL:
726 795 mac_prop_info_set_default_link_flowctrl(prh,
727 796 LINK_FLOWCTRL_NONE);
728 797 break;
729 798
730 799 case MAC_PROP_MTU:
731 800 mac_prop_info_set_range_uint32(prh,
732 801 DEFAULT_MTU, ixgbe->capab->max_mtu);
733 802 break;
734 803
735 804 case MAC_PROP_PRIVATE: {
736 805 char valstr[64];
737 806 int value;
738 807
739 808 bzero(valstr, sizeof (valstr));
740 809
741 810 if (strcmp(pr_name, "_adv_pause_cap") == 0 ||
742 811 strcmp(pr_name, "_adv_asym_pause_cap") == 0) {
743 812 mac_prop_info_set_perm(prh, MAC_PROP_PERM_READ);
744 813 return;
745 814 }
746 815
747 816 if (strcmp(pr_name, "_tx_copy_thresh") == 0) {
748 817 value = DEFAULT_TX_COPY_THRESHOLD;
749 818 } else if (strcmp(pr_name, "_tx_recycle_thresh") == 0) {
750 819 value = DEFAULT_TX_RECYCLE_THRESHOLD;
751 820 } else if (strcmp(pr_name, "_tx_overload_thresh") == 0) {
752 821 value = DEFAULT_TX_OVERLOAD_THRESHOLD;
753 822 } else if (strcmp(pr_name, "_tx_resched_thresh") == 0) {
754 823 value = DEFAULT_TX_RESCHED_THRESHOLD;
755 824 } else if (strcmp(pr_name, "_rx_copy_thresh") == 0) {
756 825 value = DEFAULT_RX_COPY_THRESHOLD;
757 826 } else if (strcmp(pr_name, "_rx_limit_per_intr") == 0) {
758 827 value = DEFAULT_RX_LIMIT_PER_INTR;
759 828 } if (strcmp(pr_name, "_intr_throttling") == 0) {
760 829 value = ixgbe->capab->def_intr_throttle;
761 830 } else {
762 831 return;
763 832 }
764 833
765 834 (void) snprintf(valstr, sizeof (valstr), "%x", value);
766 835 }
767 836 }
768 837 }
769 838
770 839 boolean_t
771 840 ixgbe_param_locked(mac_prop_id_t pr_num)
772 841 {
773 842 /*
774 843 * All en_* parameters are locked (read-only) while
775 844 * the device is in any sort of loopback mode ...
776 845 */
777 846 switch (pr_num) {
778 847 case MAC_PROP_EN_10GFDX_CAP:
779 848 case MAC_PROP_EN_5000FDX_CAP:
780 849 case MAC_PROP_EN_2500FDX_CAP:
781 850 case MAC_PROP_EN_1000FDX_CAP:
782 851 case MAC_PROP_EN_100FDX_CAP:
783 852 case MAC_PROP_AUTONEG:
784 853 case MAC_PROP_FLOWCTRL:
785 854 return (B_TRUE);
786 855 }
787 856 return (B_FALSE);
788 857 }
789 858
790 859 /* ARGSUSED */
791 860 int
792 861 ixgbe_set_priv_prop(ixgbe_t *ixgbe, const char *pr_name,
793 862 uint_t pr_valsize, const void *pr_val)
794 863 {
795 864 int err = 0;
796 865 long result;
797 866 struct ixgbe_hw *hw = &ixgbe->hw;
798 867 int i;
799 868
800 869 if (strcmp(pr_name, "_tx_copy_thresh") == 0) {
801 870 if (pr_val == NULL) {
802 871 err = EINVAL;
803 872 return (err);
804 873 }
805 874 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result);
806 875 if (result < MIN_TX_COPY_THRESHOLD ||
807 876 result > MAX_TX_COPY_THRESHOLD)
808 877 err = EINVAL;
809 878 else {
810 879 ixgbe->tx_copy_thresh = (uint32_t)result;
811 880 }
812 881 return (err);
813 882 }
814 883 if (strcmp(pr_name, "_tx_recycle_thresh") == 0) {
815 884 if (pr_val == NULL) {
816 885 err = EINVAL;
817 886 return (err);
818 887 }
819 888 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result);
820 889 if (result < MIN_TX_RECYCLE_THRESHOLD ||
821 890 result > MAX_TX_RECYCLE_THRESHOLD)
822 891 err = EINVAL;
823 892 else {
824 893 ixgbe->tx_recycle_thresh = (uint32_t)result;
825 894 }
826 895 return (err);
827 896 }
828 897 if (strcmp(pr_name, "_tx_overload_thresh") == 0) {
829 898 if (pr_val == NULL) {
830 899 err = EINVAL;
831 900 return (err);
832 901 }
833 902 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result);
834 903 if (result < MIN_TX_OVERLOAD_THRESHOLD ||
835 904 result > MAX_TX_OVERLOAD_THRESHOLD)
836 905 err = EINVAL;
837 906 else {
838 907 ixgbe->tx_overload_thresh = (uint32_t)result;
839 908 }
840 909 return (err);
841 910 }
842 911 if (strcmp(pr_name, "_tx_resched_thresh") == 0) {
843 912 if (pr_val == NULL) {
844 913 err = EINVAL;
845 914 return (err);
846 915 }
847 916 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result);
848 917 if (result < MIN_TX_RESCHED_THRESHOLD ||
849 918 result > MAX_TX_RESCHED_THRESHOLD)
850 919 err = EINVAL;
851 920 else {
852 921 ixgbe->tx_resched_thresh = (uint32_t)result;
853 922 }
854 923 return (err);
855 924 }
856 925 if (strcmp(pr_name, "_rx_copy_thresh") == 0) {
857 926 if (pr_val == NULL) {
858 927 err = EINVAL;
859 928 return (err);
860 929 }
861 930 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result);
862 931 if (result < MIN_RX_COPY_THRESHOLD ||
863 932 result > MAX_RX_COPY_THRESHOLD)
864 933 err = EINVAL;
865 934 else {
866 935 ixgbe->rx_copy_thresh = (uint32_t)result;
867 936 }
868 937 return (err);
869 938 }
870 939 if (strcmp(pr_name, "_rx_limit_per_intr") == 0) {
871 940 if (pr_val == NULL) {
872 941 err = EINVAL;
873 942 return (err);
874 943 }
875 944 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result);
876 945 if (result < MIN_RX_LIMIT_PER_INTR ||
877 946 result > MAX_RX_LIMIT_PER_INTR)
878 947 err = EINVAL;
879 948 else {
880 949 ixgbe->rx_limit_per_intr = (uint32_t)result;
881 950 }
882 951 return (err);
883 952 }
884 953 if (strcmp(pr_name, "_intr_throttling") == 0) {
885 954 if (pr_val == NULL) {
886 955 err = EINVAL;
887 956 return (err);
888 957 }
889 958 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result);
890 959
891 960 if (result < ixgbe->capab->min_intr_throttle ||
892 961 result > ixgbe->capab->max_intr_throttle)
893 962 err = EINVAL;
894 963 else {
895 964 ixgbe->intr_throttling[0] = (uint32_t)result;
896 965
897 966 /*
898 967 * 82599, X540 and X550 require the interrupt throttling
899 968 * rate is a multiple of 8. This is enforced by the
900 969 * register definiton.
901 970 */
902 971 if (hw->mac.type == ixgbe_mac_82599EB ||
903 972 hw->mac.type == ixgbe_mac_X540 ||
904 973 hw->mac.type == ixgbe_mac_X550 ||
905 974 hw->mac.type == ixgbe_mac_X550EM_x) {
906 975 ixgbe->intr_throttling[0] =
907 976 ixgbe->intr_throttling[0] & 0xFF8;
908 977 }
909 978
910 979 for (i = 0; i < MAX_INTR_VECTOR; i++)
911 980 ixgbe->intr_throttling[i] =
912 981 ixgbe->intr_throttling[0];
913 982
914 983 /* Set interrupt throttling rate */
915 984 for (i = 0; i < ixgbe->intr_cnt; i++)
916 985 IXGBE_WRITE_REG(hw, IXGBE_EITR(i),
917 986 ixgbe->intr_throttling[i]);
918 987 }
919 988 return (err);
920 989 }
921 990 return (ENOTSUP);
922 991 }
923 992
924 993 int
925 994 ixgbe_get_priv_prop(ixgbe_t *ixgbe, const char *pr_name,
926 995 uint_t pr_valsize, void *pr_val)
927 996 {
928 997 int err = ENOTSUP;
929 998 int value;
930 999
931 1000 if (strcmp(pr_name, "_adv_pause_cap") == 0) {
932 1001 value = ixgbe->param_adv_pause_cap;
933 1002 err = 0;
934 1003 goto done;
935 1004 }
936 1005 if (strcmp(pr_name, "_adv_asym_pause_cap") == 0) {
937 1006 value = ixgbe->param_adv_asym_pause_cap;
938 1007 err = 0;
939 1008 goto done;
940 1009 }
941 1010 if (strcmp(pr_name, "_tx_copy_thresh") == 0) {
942 1011 value = ixgbe->tx_copy_thresh;
943 1012 err = 0;
944 1013 goto done;
945 1014 }
946 1015 if (strcmp(pr_name, "_tx_recycle_thresh") == 0) {
947 1016 value = ixgbe->tx_recycle_thresh;
948 1017 err = 0;
949 1018 goto done;
950 1019 }
951 1020 if (strcmp(pr_name, "_tx_overload_thresh") == 0) {
952 1021 value = ixgbe->tx_overload_thresh;
953 1022 err = 0;
954 1023 goto done;
955 1024 }
956 1025 if (strcmp(pr_name, "_tx_resched_thresh") == 0) {
957 1026 value = ixgbe->tx_resched_thresh;
958 1027 err = 0;
959 1028 goto done;
960 1029 }
961 1030 if (strcmp(pr_name, "_rx_copy_thresh") == 0) {
962 1031 value = ixgbe->rx_copy_thresh;
963 1032 err = 0;
964 1033 goto done;
965 1034 }
966 1035 if (strcmp(pr_name, "_rx_limit_per_intr") == 0) {
967 1036 value = ixgbe->rx_limit_per_intr;
968 1037 err = 0;
969 1038 goto done;
970 1039 }
971 1040 if (strcmp(pr_name, "_intr_throttling") == 0) {
972 1041 value = ixgbe->intr_throttling[0];
973 1042 err = 0;
974 1043 goto done;
975 1044 }
976 1045 done:
977 1046 if (err == 0) {
978 1047 (void) snprintf(pr_val, pr_valsize, "%d", value);
979 1048 }
980 1049 return (err);
981 1050 }
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