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NEX-20178 Heavy read load using 10G i40e causes network disconnect
MFV illumos-joyent@83a8d0d616db36010b59cc850d1926c0f6a30de1
OS-7457 i40e Tx freezes on zero descriptors
Reviewed by: Robert Mustacchi <rm@joyent.com>
Reviewed by: Rob Johnston <rob.johnston@joyent.com>
Approved by: Robert Mustacchi <rm@joyent.com>
MFV illumos-joyent@0d3f2b61dcfb18edace4fd257054f6fdbe07c99c
OS-7492 i40e Tx freeze when b_cont chain exceeds 8 descriptors
Reviewed by: Robert Mustacchi <rm@joyent.com>
Reviewed by: Rob Johnston <rob.johnston@joyent.com>
Approved by: Robert Mustacchi <rm@joyent.com>
MFV illumos-joyent@b4bede175d4c50ac1b36078a677b69388f6fb59f
OS-7577 initialize FC for i40e
Reviewed by: Robert Mustacchi <rm@joyent.com>
Approved by: Rob Johnston <rob.johnston@joyent.com>
MFV illumos-joyent@83a8d0d616db36010b59cc850d1926c0f6a30de1
OS-7457 i40e Tx freezes on zero descriptors
Reviewed by: Robert Mustacchi <rm@joyent.com>
Reviewed by: Rob Johnston <rob.johnston@joyent.com>
Approved by: Robert Mustacchi <rm@joyent.com>
MFV: illumos-joyent@61dc3dec4f82a3e13e94609a0a83d5f66c64e760
OS-6846 want i40e multi-group support
OS-7372 i40e_alloc_ring_mem() unwinds when it shouldn't
Reviewed by: Robert Mustacchi <rm@joyent.com>
Approved by: Robert Mustacchi <rm@joyent.com>
Author: Ryan Zezeski <rpz@joyent.com>
MFV: illumos-joyent@757454db6669c1186f60bc625510c1b67217aae6
OS-7082 i40e: blown assert in i40e_tx_cleanup_ring()
OS-7086 i40e: add mdb dcmd to dump info on tx descriptor rings
OS-7101 i40e: add kstat to track TX DMA bind failures
Reviewed by: Ryan Zezeski <rpz@joyent.com>
Reviewed by: Robert Mustacchi <rm@joyent.com>
Approved by: Patrick Mooney <patrick.mooney@joyent.com>
Author: Rob Johnston <rob.johnston@joyent.com>
MFV: illumos-joyent@9e30beee2f0c127bf41868db46257124206e28d6
OS-5225 Want Fortville TSO support
Reviewed by: Ryan Zezeski <rpz@joyent.com>
Reviewed by: Robert Mustacchi <rm@joyent.com>
Approved by: Patrick Mooney <patrick.mooney@joyent.com>
Author: Rob Johnston <rob.johnston@joyent.com>
NEX-13226 xvv710 25Gb NIC panics system under load
Reviewed by: Yuri Pankov <yuri.pankov@nexenta.com>
Reviewed by: Evan Layton <evan.layton@nexenta.com>
NEX-7822 40Gb Intel XL710 NIC performance data
Reviewed by: Steve Peng <steve.peng@nexenta.com>
Reviewed by: Evan Layton <evan.layton@nexenta.com>
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--- old/usr/src/uts/common/io/i40e/i40e_sw.h
+++ new/usr/src/uts/common/io/i40e/i40e_sw.h
1 1 /*
2 2 * This file and its contents are supplied under the terms of the
3 3 * Common Development and Distribution License ("CDDL"), version 1.0.
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4 4 * You may only use this file in accordance with the terms of version
5 5 * 1.0 of the CDDL.
6 6 *
7 7 * A full copy of the text of the CDDL should have accompanied this
8 8 * source. A copy of the CDDL is also available via the Internet at
9 9 * http://www.illumos.org/license/CDDL.
10 10 */
11 11
12 12 /*
13 13 * Copyright 2015 OmniTI Computer Consulting, Inc. All rights reserved.
14 - * Copyright (c) 2017, Joyent, Inc.
14 + * Copyright 2019 Joyent, Inc.
15 15 * Copyright 2017 Tegile Systems, Inc. All rights reserved.
16 16 */
17 17
18 18 /*
19 19 * Please see i40e_main.c for an introduction to the device driver, its layout,
20 20 * and more.
21 21 */
22 22
23 23 #ifndef _I40E_SW_H
24 24 #define _I40E_SW_H
25 25
26 26 #ifdef __cplusplus
27 27 extern "C" {
28 28 #endif
29 29
30 30 #include <sys/types.h>
31 31 #include <sys/conf.h>
32 32 #include <sys/debug.h>
33 33 #include <sys/stropts.h>
34 34 #include <sys/stream.h>
35 35 #include <sys/strsun.h>
36 36 #include <sys/strlog.h>
37 37 #include <sys/kmem.h>
38 38 #include <sys/stat.h>
39 39 #include <sys/kstat.h>
40 40 #include <sys/modctl.h>
41 41 #include <sys/errno.h>
42 42 #include <sys/dlpi.h>
43 43 #include <sys/mac_provider.h>
44 44 #include <sys/mac_ether.h>
45 45 #include <sys/vlan.h>
46 46 #include <sys/ddi.h>
47 47 #include <sys/sunddi.h>
48 48 #include <sys/pci.h>
49 49 #include <sys/pcie.h>
50 50 #include <sys/sdt.h>
51 51 #include <sys/ethernet.h>
52 52 #include <sys/pattr.h>
53 53 #include <sys/strsubr.h>
54 54 #include <sys/netlb.h>
55 55 #include <sys/random.h>
56 56 #include <inet/common.h>
57 57 #include <inet/tcp.h>
58 58 #include <inet/ip.h>
59 59 #include <inet/mi.h>
60 60 #include <inet/nd.h>
61 61 #include <netinet/udp.h>
62 62 #include <netinet/sctp.h>
63 63 #include <sys/bitmap.h>
64 64 #include <sys/cpuvar.h>
65 65 #include <sys/ddifm.h>
66 66 #include <sys/fm/protocol.h>
67 67 #include <sys/fm/util.h>
68 68 #include <sys/disp.h>
69 69 #include <sys/fm/io/ddi.h>
70 70 #include <sys/list.h>
71 71 #include <sys/debug.h>
72 72 #include <sys/sdt.h>
73 73 #include "i40e_type.h"
74 74 #include "i40e_osdep.h"
75 75 #include "i40e_prototype.h"
76 76 #include "i40e_xregs.h"
77 77
78 78 #define I40E_MODULE_NAME "i40e"
79 79
80 80 #define I40E_ADAPTER_REGSET 1
81 81
82 82 /*
83 83 * Configuration constants. Note that the hardware defines a minimum bound of 32
84 84 * descriptors and requires that the programming of the descriptor lengths be
85 85 * aligned in units of 32 descriptors.
86 86 */
87 87 #define I40E_MIN_TX_RING_SIZE 64
88 88 #define I40E_MAX_TX_RING_SIZE 4096
89 89 #define I40E_DEF_TX_RING_SIZE 1024
90 90
91 91 #define I40E_MIN_RX_RING_SIZE 64
92 92 #define I40E_MAX_RX_RING_SIZE 4096
93 93 #define I40E_DEF_RX_RING_SIZE 1024
94 94
95 95 #define I40E_DESC_ALIGN 32
96 96
97 97 /*
98 98 * Sizes used for asynchronous processing of the adminq. We allocate a fixed
99 99 * size buffer for each instance of the device during attach time, rather than
100 100 * allocating and freeing one during interrupt processing.
101 101 *
102 102 * We also define the descriptor size of the admin queue here.
103 103 */
104 104 #define I40E_ADMINQ_BUFSZ 4096
105 105 #define I40E_MAX_ADMINQ_SIZE 1024
106 106 #define I40E_DEF_ADMINQ_SIZE 256
107 107
108 108 /*
109 109 * Note, while the min and maximum values are based upon the sizing of the ring
110 110 * itself, the default is taken from ixgbe without much thought. It's basically
111 111 * been cargo culted. See i40e_transceiver.c for a bit more information.
112 112 */
113 113 #define I40E_MIN_RX_LIMIT_PER_INTR 16
114 114 #define I40E_MAX_RX_LIMIT_PER_INTR 4096
115 115 #define I40E_DEF_RX_LIMIT_PER_INTR 256
116 116
117 117 /*
118 118 * Valid MTU ranges. Note that the XL710's maximum payload is actually 9728.
119 119 * However, we need to adjust for the ETHERFCSL (4 bytes) and the Ethernet VLAN
120 120 * header size (18 bytes) to get the actual maximum frame we can use. If
121 121 * different adapters end up with different sizes, we should make this value a
122 122 * bit more dynamic.
123 123 */
124 124 #define I40E_MAX_MTU 9706
125 125 #define I40E_MIN_MTU ETHERMIN
126 126 #define I40E_DEF_MTU ETHERMTU
127 127
128 128 /*
129 129 * Interrupt throttling related values. Interrupt throttling values are defined
130 130 * in two microsecond increments. Note that a value of zero basically says do no
131 131 * ITR activity. A helpful way to think about these is that setting the ITR to a
132 132 * value will allow a certain number of interrupts per second.
133 133 *
134 134 * Our default values for RX allow 20k interrupts per second while our default
135 135 * values for TX allow for 5k interrupts per second. For other class interrupts,
136 136 * we limit ourselves to a rate of 2k/s.
137 137 */
138 138 #define I40E_MIN_ITR 0x0000
139 139 #define I40E_MAX_ITR 0x0FF0
140 140 #define I40E_DEF_RX_ITR 0x0019
141 141 #define I40E_DEF_TX_ITR 0x0064
142 142 #define I40E_DEF_OTHER_ITR 0x00FA
143 143
144 144 /*
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145 145 * Indexes into the three ITR registers that we have.
146 146 */
147 147 typedef enum i40e_itr_index {
148 148 I40E_ITR_INDEX_RX = 0x0,
149 149 I40E_ITR_INDEX_TX = 0x1,
150 150 I40E_ITR_INDEX_OTHER = 0x2,
151 151 I40E_ITR_INDEX_NONE = 0x3
152 152 } i40e_itr_index_t;
153 153
154 154 /*
155 - * Table 1-5 of the PRM notes that LSO supports up to 256 KB.
155 + * The hardware claims to support LSO up to 256 KB, but due to the limitations
156 + * imposed by the IP header for non-jumbo frames, we cap it at 64 KB.
156 157 */
157 -#define I40E_LSO_MAXLEN (256 * 1024)
158 +#define I40E_LSO_MAXLEN (64 * 1024)
158 159
159 160 #define I40E_CYCLIC_PERIOD NANOSEC /* 1 second */
160 161 #define I40E_DRAIN_RX_WAIT (500 * MILLISEC) /* In us */
161 162
162 163 /*
163 164 * All the other queue types for are defined by the common code. However, this
164 165 * is the constant to indicate that it's terminated.
165 166 */
166 167 #define I40E_QUEUE_TYPE_EOL 0x7FF
167 168
168 169 /*
169 170 * See the comments in i40e_transceiver.c as to the purpose of this value and
170 171 * how it's used to ensure that the IP header is eventually aligned when it's
171 172 * received by the OS.
172 173 */
173 174 #define I40E_BUF_IPHDR_ALIGNMENT 2
174 175
175 176 /*
176 - * The XL710 controller has a limit of eight buffers being allowed to be used
177 - * for the transmission of a single frame. This is defined in 8.4.1 - Transmit
177 + * The XL710 controller has a total of eight buffers available for the
178 + * transmission of any single frame. This is defined in 8.4.1 - Transmit
178 179 * Packet in System Memory.
179 180 */
180 181 #define I40E_TX_MAX_COOKIE 8
181 182
182 183 /*
184 + * An LSO frame can be as large as 64KB, so we allow a DMA bind to span more
185 + * cookies than a non-LSO frame. The key here to is to select a value such
186 + * that once the HW has chunked up the LSO frame into MSS-sized segments that no
187 + * single segment spans more than 8 cookies (see comments for
188 + * I40E_TX_MAX_COOKIE)
189 + */
190 +#define I40E_TX_LSO_MAX_COOKIE 32
191 +
192 +/*
183 193 * Sizing to determine the amount of available descriptors at which we'll
184 194 * consider ourselves blocked. Also, when we have these available, we'll then
185 195 * consider ourselves available to transmit to MAC again. Strictly speaking, the
186 196 * MAX is based on the ring size. The default sizing is based on ixgbe.
187 197 */
188 198 #define I40E_MIN_TX_BLOCK_THRESH I40E_TX_MAX_COOKIE
189 199 #define I40E_DEF_TX_BLOCK_THRESH I40E_MIN_TX_BLOCK_THRESH
190 200
191 201 /*
192 202 * Sizing for DMA thresholds. These are used to indicate whether or not we
193 203 * should perform a bcopy or a DMA binding of a given message block. The range
194 204 * allows for setting things such that we'll always do a bcopy (a high value) or
195 205 * always perform a DMA binding (a low value).
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196 206 */
197 207 #define I40E_MIN_RX_DMA_THRESH 0
198 208 #define I40E_DEF_RX_DMA_THRESH 256
199 209 #define I40E_MAX_RX_DMA_THRESH INT32_MAX
200 210
201 211 #define I40E_MIN_TX_DMA_THRESH 0
202 212 #define I40E_DEF_TX_DMA_THRESH 256
203 213 #define I40E_MAX_TX_DMA_THRESH INT32_MAX
204 214
205 215 /*
216 + * The max size of each individual tx buffer is 16KB - 1.
217 + * See table 8-17
218 + */
219 +#define I40E_MAX_TX_BUFSZ 0x0000000000003FFFull
220 +
221 +/*
206 222 * Resource sizing counts. There are various aspects of hardware where we may
207 223 * have some variable number of elements that we need to handle. Such as the
208 224 * hardware capabilities and switch capacities. We cannot know a priori how many
209 225 * elements to do, so instead we take a starting guess and then will grow it up
210 226 * to an upper bound on a number of elements, to limit memory consumption in
211 227 * case of a hardware bug.
212 228 */
213 229 #define I40E_HW_CAP_DEFAULT 40
214 230 #define I40E_SWITCH_CAP_DEFAULT 25
215 231
216 232 /*
217 233 * Host Memory Context related constants.
218 234 */
219 235 #define I40E_HMC_RX_CTX_UNIT 128
220 236 #define I40E_HMC_RX_DBUFF_MIN 1024
221 237 #define I40E_HMC_RX_DBUFF_MAX (16 * 1024 - 128)
222 238 #define I40E_HMC_RX_DTYPE_NOSPLIT 0
223 239 #define I40E_HMC_RX_DSIZE_32BYTE 1
224 240 #define I40E_HMC_RX_CRCSTRIP_ENABLE 1
225 241 #define I40E_HMC_RX_FC_DISABLE 0
226 242 #define I40E_HMC_RX_L2TAGORDER 1
227 243 #define I40E_HMC_RX_HDRSPLIT_DISABLE 0
228 244 #define I40E_HMC_RX_INVLAN_DONTSTRIP 0
229 245 #define I40E_HMC_RX_TPH_DISABLE 0
230 246 #define I40E_HMC_RX_LOWRXQ_NOINTR 0
231 247 #define I40E_HMC_RX_PREFENA 1
232 248
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233 249 #define I40E_HMC_TX_CTX_UNIT 128
234 250 #define I40E_HMC_TX_NEW_CONTEXT 1
235 251 #define I40E_HMC_TX_FC_DISABLE 0
236 252 #define I40E_HMC_TX_TS_DISABLE 0
237 253 #define I40E_HMC_TX_FD_DISABLE 0
238 254 #define I40E_HMC_TX_ALT_VLAN_DISABLE 0
239 255 #define I40E_HMC_TX_WB_ENABLE 1
240 256 #define I40E_HMC_TX_TPH_DISABLE 0
241 257
242 258 /*
243 - * Whenever we establish and create a VSI, we need to assign some number of
244 - * queues that it's allowed to access from the PF. Because we only have a single
245 - * VSI per PF at this time, we assign it all the queues.
246 - *
247 - * Many of the devices support what's called Data-center Bridging. Which is a
248 - * feature that we don't have much use of at this time. However, we still need
249 - * to fill in this information. We follow the guidance of the note in Table 7-80
250 - * which talks about bytes 62-77. It says that if we don't want to assign
251 - * anything to traffic classes, we should set the field to zero. Effectively
252 - * this means that everything in the system is assigned to traffic class zero.
253 - */
254 -#define I40E_ASSIGN_ALL_QUEUES 0
255 -#define I40E_TRAFFIC_CLASS_NO_QUEUES 0
256 -
257 -/*
258 259 * This defines the error mask that we care about from rx descriptors. Currently
259 260 * we're only concerned with the general errors and oversize errors.
260 261 */
261 262 #define I40E_RX_ERR_BITS ((1 << I40E_RX_DESC_ERROR_RXE_SHIFT) | \
262 263 (1 << I40E_RX_DESC_ERROR_OVERSIZE_SHIFT))
263 264
264 265 /*
265 266 * Property sizing macros for firmware versions, etc. They need to be large
266 267 * enough to hold 32-bit quantities transformed to strings as %d.%d or %x.
267 268 */
268 269 #define I40E_DDI_PROP_LEN 64
269 270
270 271 /*
271 - * We currently consolidate some overrides that we use in the code here. These
272 - * will be gone in the fullness of time, but as we're bringing up the device,
273 - * this is what we use.
272 + * Place an artificial limit on the max number of groups. The X710
273 + * series supports up to 384 VSIs to be partitioned across PFs as the
274 + * driver sees fit. But until we support more interrupts this seems
275 + * like a good place to start.
274 276 */
275 -#define I40E_GROUP_MAX 1
276 -#define I40E_TRQPAIR_MAX 1
277 +#define I40E_GROUP_MAX 32
277 278
278 279 #define I40E_GROUP_NOMSIX 1
279 280 #define I40E_TRQPAIR_NOMSIX 1
280 281
281 282 /*
282 283 * It seems reasonable to cast this to void because the only reason that we
283 284 * should be getting a DDI_FAILURE is due to the fact that we specify addresses
284 285 * out of range. Because we specify no offset or address, it shouldn't happen.
285 286 */
286 287 #ifdef DEBUG
287 288 #define I40E_DMA_SYNC(handle, flag) ASSERT0(ddi_dma_sync( \
288 289 (handle)->dmab_dma_handle, 0, 0, \
289 290 (flag)))
290 291 #else /* !DEBUG */
291 292 #define I40E_DMA_SYNC(handle, flag) ((void) ddi_dma_sync( \
292 293 (handle)->dmab_dma_handle, 0, 0, \
293 294 (flag)))
294 295 #endif /* DEBUG */
295 296
296 297 /*
297 298 * Constants related to ring startup and teardown. These refer to the amount of
298 299 * time that we're willing to wait for a ring to spin up and spin down.
299 300 */
300 301 #define I40E_RING_WAIT_NTRIES 10
301 302 #define I40E_RING_WAIT_PAUSE 10 /* ms */
302 303
303 304 /*
304 305 * Printed Board Assembly (PBA) length. These are derived from Table 6-2.
305 306 */
306 307 #define I40E_PBANUM_LENGTH 12
307 308 #define I40E_PBANUM_STRLEN 13
308 309
309 310 /*
310 311 * Define the maximum number of queues for a traffic class. These values come
311 312 * from the 'Number and offset of queue pairs per TCs' section of the 'Add VSI
312 313 * Command Buffer' table. For the 710 controller family this is table 7-62
313 314 * (r2.5) and for the 722 this is table 38-216 (r2.0).
314 315 */
315 316 #define I40E_710_MAX_TC_QUEUES 64
316 317 #define I40E_722_MAX_TC_QUEUES 128
317 318
318 319 /*
319 320 * Define the size of the HLUT table size. The HLUT table can either be 128 or
320 321 * 512 bytes. We always set the table size to be 512 bytes in i40e_chip_start().
321 322 * Note, this should not be confused with the common code's macro
322 323 * I40E_HASH_LUT_SIZE_512 which is the bit pattern needed to tell the card to
323 324 * use a 512 byte HLUT.
324 325 */
325 326 #define I40E_HLUT_TABLE_SIZE 512
326 327
327 328 /*
328 329 * Bit flags for attach_progress
329 330 */
330 331 typedef enum i40e_attach_state {
331 332 I40E_ATTACH_PCI_CONFIG = 0x0001, /* PCI config setup */
332 333 I40E_ATTACH_REGS_MAP = 0x0002, /* Registers mapped */
333 334 I40E_ATTACH_PROPS = 0x0004, /* Properties initialized */
334 335 I40E_ATTACH_ALLOC_INTR = 0x0008, /* Interrupts allocated */
335 336 I40E_ATTACH_ALLOC_RINGSLOCKS = 0x0010, /* Rings & locks allocated */
336 337 I40E_ATTACH_ADD_INTR = 0x0020, /* Intr handlers added */
337 338 I40E_ATTACH_COMMON_CODE = 0x0040, /* Intel code initialized */
338 339 I40E_ATTACH_INIT = 0x0080, /* Device initialized */
339 340 I40E_ATTACH_STATS = 0x0200, /* Kstats created */
340 341 I40E_ATTACH_MAC = 0x0800, /* MAC registered */
341 342 I40E_ATTACH_ENABLE_INTR = 0x1000, /* DDI interrupts enabled */
342 343 I40E_ATTACH_FM_INIT = 0x2000, /* FMA initialized */
343 344 I40E_ATTACH_LINK_TIMER = 0x4000, /* link check timer */
344 345 } i40e_attach_state_t;
345 346
346 347
347 348 /*
348 349 * State flags that what's going on in in the device. Some of these state flags
349 350 * indicate some aspirational work that needs to happen in the driver.
350 351 *
351 352 * I40E_UNKNOWN: The device has yet to be started.
352 353 * I40E_INITIALIZED: The device has been fully attached.
353 354 * I40E_STARTED: The device has come out of the GLDV3 start routine.
354 355 * I40E_SUSPENDED: The device is suspended and I/O among other things
355 356 * should not occur. This happens because of an actual
356 357 * DDI_SUSPEND or interrupt adjustments.
357 358 * I40E_STALL: The tx stall detection logic has found a stall.
358 359 * I40E_OVERTEMP: The device has encountered a temperature alarm.
359 360 * I40E_INTR_ADJUST: Our interrupts are being manipulated and therefore we
360 361 * shouldn't be manipulating their state.
361 362 * I40E_ERROR: We've detected an FM error and degraded the device.
362 363 */
363 364 typedef enum i40e_state {
364 365 I40E_UNKNOWN = 0x00,
365 366 I40E_INITIALIZED = 0x01,
366 367 I40E_STARTED = 0x02,
367 368 I40E_SUSPENDED = 0x04,
368 369 I40E_STALL = 0x08,
369 370 I40E_OVERTEMP = 0x20,
370 371 I40E_INTR_ADJUST = 0x40,
371 372 I40E_ERROR = 0x80
372 373 } i40e_state_t;
373 374
374 375
375 376 /*
376 377 * Definitions for common Intel things that we use and some slightly more usable
377 378 * names.
378 379 */
379 380 typedef struct i40e_hw i40e_hw_t;
380 381 typedef struct i40e_aqc_switch_resource_alloc_element_resp i40e_switch_rsrc_t;
381 382
382 383 /*
383 384 * Handles and addresses of DMA buffers.
384 385 */
385 386 typedef struct i40e_dma_buffer {
386 387 caddr_t dmab_address; /* Virtual address */
387 388 uint64_t dmab_dma_address; /* DMA (Hardware) address */
388 389 ddi_acc_handle_t dmab_acc_handle; /* Data access handle */
389 390 ddi_dma_handle_t dmab_dma_handle; /* DMA handle */
390 391 size_t dmab_size; /* Buffer size */
391 392 size_t dmab_len; /* Data length in the buffer */
392 393 } i40e_dma_buffer_t;
393 394
394 395 /*
395 396 * RX Control Block
396 397 */
397 398 typedef struct i40e_rx_control_block {
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398 399 mblk_t *rcb_mp;
399 400 uint32_t rcb_ref;
400 401 i40e_dma_buffer_t rcb_dma;
401 402 frtn_t rcb_free_rtn;
402 403 struct i40e_rx_data *rcb_rxd;
403 404 } i40e_rx_control_block_t;
404 405
405 406 typedef enum {
406 407 I40E_TX_NONE,
407 408 I40E_TX_COPY,
408 - I40E_TX_DMA
409 + I40E_TX_DMA,
410 + I40E_TX_DESC,
409 411 } i40e_tx_type_t;
410 412
411 413 typedef struct i40e_tx_desc i40e_tx_desc_t;
414 +typedef struct i40e_tx_context_desc i40e_tx_context_desc_t;
412 415 typedef union i40e_32byte_rx_desc i40e_rx_desc_t;
413 416
417 +struct i40e_dma_bind_info {
418 + caddr_t dbi_paddr;
419 + size_t dbi_len;
420 +};
421 +
414 422 typedef struct i40e_tx_control_block {
415 423 struct i40e_tx_control_block *tcb_next;
416 424 mblk_t *tcb_mp;
417 425 i40e_tx_type_t tcb_type;
418 426 ddi_dma_handle_t tcb_dma_handle;
427 + ddi_dma_handle_t tcb_lso_dma_handle;
419 428 i40e_dma_buffer_t tcb_dma;
429 + struct i40e_dma_bind_info *tcb_bind_info;
430 + uint_t tcb_bind_ncookies;
431 + boolean_t tcb_used_lso;
420 432 } i40e_tx_control_block_t;
421 433
422 434 /*
423 435 * Receive ring data (used below).
424 436 */
425 437 typedef struct i40e_rx_data {
426 438 struct i40e *rxd_i40e;
427 439
428 440 /*
429 441 * RX descriptor ring definitions
430 442 */
431 443 i40e_dma_buffer_t rxd_desc_area; /* DMA buffer of rx desc ring */
432 444 i40e_rx_desc_t *rxd_desc_ring; /* Rx desc ring */
433 445 uint32_t rxd_desc_next; /* Index of next rx desc */
434 446
435 447 /*
436 448 * RX control block list definitions
437 449 */
438 450 kmutex_t rxd_free_lock; /* Lock to protect free data */
439 451 i40e_rx_control_block_t *rxd_rcb_area; /* Array of control blocks */
440 452 i40e_rx_control_block_t **rxd_work_list; /* Work list of rcbs */
441 453 i40e_rx_control_block_t **rxd_free_list; /* Free list of rcbs */
442 454 uint32_t rxd_rcb_free; /* Number of free rcbs */
443 455
444 456 /*
445 457 * RX software ring settings
446 458 */
447 459 uint32_t rxd_ring_size; /* Rx descriptor ring size */
448 460 uint32_t rxd_free_list_size; /* Rx free list size */
449 461
450 462 /*
451 463 * RX outstanding data. This is used to keep track of outstanding loaned
452 464 * descriptors after we've shut down receiving information. Note these
453 465 * are protected by the i40e_t`i40e_rx_pending_lock.
454 466 */
455 467 uint32_t rxd_rcb_pending;
456 468 boolean_t rxd_shutdown;
457 469 } i40e_rx_data_t;
458 470
459 471 /*
460 472 * Structures for unicast and multicast addresses. Note that we keep the VSI id
461 473 * around for unicast addresses, since they may belong to different VSIs.
462 474 * However, since all multicast addresses belong to the default VSI, we don't
463 475 * duplicate that information.
464 476 */
465 477 typedef struct i40e_uaddr {
466 478 uint8_t iua_mac[ETHERADDRL];
467 479 int iua_vsi;
468 480 } i40e_uaddr_t;
469 481
470 482 typedef struct i40e_maddr {
471 483 uint8_t ima_mac[ETHERADDRL];
472 484 } i40e_maddr_t;
473 485
474 486 /*
475 487 * Collection of RX statistics on a given queue.
476 488 */
477 489 typedef struct i40e_rxq_stat {
478 490 /*
479 491 * The i40e hardware does not maintain statistics on a per-ring basis,
480 492 * only on a per-PF and per-VSI level. As such, to satisfy the GLDv3, we
481 493 * need to maintain our own stats for packets and bytes.
482 494 */
483 495 kstat_named_t irxs_bytes; /* Bytes in on queue */
484 496 kstat_named_t irxs_packets; /* Packets in on queue */
485 497
486 498 /*
487 499 * The following set of stats cover non-checksum data path issues.
488 500 */
489 501 kstat_named_t irxs_rx_desc_error; /* Error bit set on desc */
490 502 kstat_named_t irxs_rx_copy_nomem; /* allocb failure for copy */
491 503 kstat_named_t irxs_rx_intr_limit; /* Hit i40e_rx_limit_per_intr */
492 504 kstat_named_t irxs_rx_bind_norcb; /* No replacement rcb free */
493 505 kstat_named_t irxs_rx_bind_nomp; /* No mblk_t in bind rcb */
494 506
495 507 /*
496 508 * The following set of statistics covers rx checksum related activity.
497 509 * These are all primarily set in i40e_rx_hcksum. If rx checksum
498 510 * activity is disabled, then these should all be zero.
499 511 */
500 512 kstat_named_t irxs_hck_v4hdrok; /* Valid IPv4 Header */
501 513 kstat_named_t irxs_hck_l4hdrok; /* Valid L4 Header */
502 514 kstat_named_t irxs_hck_unknown; /* !pinfo.known */
503 515 kstat_named_t irxs_hck_nol3l4p; /* Missing L3L4P bit in desc */
504 516 kstat_named_t irxs_hck_iperr; /* IPE error bit set */
505 517 kstat_named_t irxs_hck_eiperr; /* EIPE error bit set */
506 518 kstat_named_t irxs_hck_l4err; /* L4E error bit set */
507 519 kstat_named_t irxs_hck_v6skip; /* IPv6 case hw fails on */
508 520 kstat_named_t irxs_hck_set; /* Total times we set cksum */
509 521 kstat_named_t irxs_hck_miss; /* Times with zero cksum bits */
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510 522 } i40e_rxq_stat_t;
511 523
512 524 /*
513 525 * Collection of TX Statistics on a given queue
514 526 */
515 527 typedef struct i40e_txq_stat {
516 528 kstat_named_t itxs_bytes; /* Bytes out on queue */
517 529 kstat_named_t itxs_packets; /* Packets out on queue */
518 530 kstat_named_t itxs_descriptors; /* Descriptors issued */
519 531 kstat_named_t itxs_recycled; /* Descriptors reclaimed */
532 + kstat_named_t itxs_force_copy; /* non-TSO force copy */
533 + kstat_named_t itxs_tso_force_copy; /* TSO force copy */
520 534 /*
521 535 * Various failure conditions.
522 536 */
523 537 kstat_named_t itxs_hck_meoifail; /* ether offload failures */
524 538 kstat_named_t itxs_hck_nol2info; /* Missing l2 info */
525 539 kstat_named_t itxs_hck_nol3info; /* Missing l3 info */
526 540 kstat_named_t itxs_hck_nol4info; /* Missing l4 info */
527 541 kstat_named_t itxs_hck_badl3; /* Not IPv4/IPv6 */
528 542 kstat_named_t itxs_hck_badl4; /* Bad L4 Paylaod */
543 + kstat_named_t itxs_lso_nohck; /* Missing offloads for LSO */
544 + kstat_named_t itxs_bind_fails; /* DMA bind failures */
529 545
530 546 kstat_named_t itxs_err_notcb; /* No tcb's available */
531 547 kstat_named_t itxs_err_nodescs; /* No tcb's available */
532 548 kstat_named_t itxs_err_context; /* Total context failures */
533 549
534 550 kstat_named_t itxs_num_unblocked; /* Number of MAC unblocks */
535 551 } i40e_txq_stat_t;
536 552
537 553 /*
538 554 * An instance of an XL710 transmit/receive queue pair. This currently
539 555 * represents a combination of both a transmit and receive ring, though they
540 556 * should really be split apart into separate logical structures. Unfortunately,
541 557 * during initial work we mistakenly joined them together.
542 558 */
543 559 typedef struct i40e_trqpair {
544 560 struct i40e *itrq_i40e;
545 561
546 562 /* Receive-side structures. */
547 563 kmutex_t itrq_rx_lock;
548 564 mac_ring_handle_t itrq_macrxring; /* Receive ring handle. */
549 565 i40e_rx_data_t *itrq_rxdata; /* Receive ring rx data. */
550 566 uint64_t itrq_rxgen; /* Generation number for mac/GLDv3. */
551 567 uint32_t itrq_index; /* Queue index in the PF */
552 568 uint32_t itrq_rx_intrvec; /* Receive interrupt vector. */
553 569 boolean_t itrq_intr_poll; /* True when polling */
554 570
555 571 /* Receive-side stats. */
556 572 i40e_rxq_stat_t itrq_rxstat;
557 573 kstat_t *itrq_rxkstat;
558 574
559 575 /* Transmit-side structures. */
560 576 kmutex_t itrq_tx_lock;
561 577 mac_ring_handle_t itrq_mactxring; /* Transmit ring handle. */
562 578 uint32_t itrq_tx_intrvec; /* Transmit interrupt vector. */
563 579 boolean_t itrq_tx_blocked; /* Does MAC think we're blocked? */
564 580
565 581 /*
566 582 * TX data sizing
567 583 */
568 584 uint32_t itrq_tx_ring_size;
569 585 uint32_t itrq_tx_free_list_size;
570 586
571 587 /*
572 588 * TX descriptor ring data
573 589 */
574 590 i40e_dma_buffer_t itrq_desc_area; /* DMA buffer of tx desc ring */
575 591 i40e_tx_desc_t *itrq_desc_ring; /* TX Desc ring */
576 592 volatile uint32_t *itrq_desc_wbhead; /* TX write-back index */
577 593 uint32_t itrq_desc_head; /* Last index hw freed */
578 594 uint32_t itrq_desc_tail; /* Index of next free desc */
579 595 uint32_t itrq_desc_free; /* Number of free descriptors */
580 596
581 597 /*
582 598 * TX control block (tcb) data
583 599 */
584 600 kmutex_t itrq_tcb_lock;
585 601 i40e_tx_control_block_t *itrq_tcb_area; /* Array of control blocks */
586 602 i40e_tx_control_block_t **itrq_tcb_work_list; /* In use tcb */
587 603 i40e_tx_control_block_t **itrq_tcb_free_list; /* Available tcb */
588 604 uint32_t itrq_tcb_free; /* Count of free tcb */
589 605
590 606 /* Transmit-side stats. */
591 607 i40e_txq_stat_t itrq_txstat;
592 608 kstat_t *itrq_txkstat;
593 609
594 610 } i40e_trqpair_t;
595 611
596 612 /*
597 613 * VSI statistics.
598 614 *
599 615 * This mirrors the i40e_eth_stats structure but transforms it into a kstat.
600 616 * Note that the stock statistic structure also includes entries for tx
601 617 * discards. However, this is not actually implemented for the VSI (see Table
602 618 * 7-221), hence why we don't include the member which would always have a value
603 619 * of zero. This choice was made to minimize confusion to someone looking at
604 620 * these, as a value of zero does not necessarily equate to the fact that it's
605 621 * not implemented.
606 622 */
607 623 typedef struct i40e_vsi_stats {
608 624 uint64_t ivs_rx_bytes; /* gorc */
609 625 uint64_t ivs_rx_unicast; /* uprc */
610 626 uint64_t ivs_rx_multicast; /* mprc */
611 627 uint64_t ivs_rx_broadcast; /* bprc */
612 628 uint64_t ivs_rx_discards; /* rdpc */
613 629 uint64_t ivs_rx_unknown_protocol; /* rupp */
614 630 uint64_t ivs_tx_bytes; /* gotc */
615 631 uint64_t ivs_tx_unicast; /* uptc */
616 632 uint64_t ivs_tx_multicast; /* mptc */
617 633 uint64_t ivs_tx_broadcast; /* bptc */
618 634 uint64_t ivs_tx_errors; /* tepc */
619 635 } i40e_vsi_stats_t;
620 636
621 637 typedef struct i40e_vsi_kstats {
622 638 kstat_named_t ivk_rx_bytes;
623 639 kstat_named_t ivk_rx_unicast;
624 640 kstat_named_t ivk_rx_multicast;
625 641 kstat_named_t ivk_rx_broadcast;
626 642 kstat_named_t ivk_rx_discards;
627 643 kstat_named_t ivk_rx_unknown_protocol;
628 644 kstat_named_t ivk_tx_bytes;
629 645 kstat_named_t ivk_tx_unicast;
630 646 kstat_named_t ivk_tx_multicast;
631 647 kstat_named_t ivk_tx_broadcast;
632 648 kstat_named_t ivk_tx_errors;
633 649 } i40e_vsi_kstats_t;
634 650
635 651 /*
636 652 * For pf statistics, we opt not to use the standard statistics as defined by
637 653 * the Intel common code. This also currently combines statistics that are
638 654 * global across the entire device.
639 655 */
640 656 typedef struct i40e_pf_stats {
641 657 uint64_t ips_rx_bytes; /* gorc */
642 658 uint64_t ips_rx_unicast; /* uprc */
643 659 uint64_t ips_rx_multicast; /* mprc */
644 660 uint64_t ips_rx_broadcast; /* bprc */
645 661 uint64_t ips_tx_bytes; /* gotc */
646 662 uint64_t ips_tx_unicast; /* uptc */
647 663 uint64_t ips_tx_multicast; /* mptc */
648 664 uint64_t ips_tx_broadcast; /* bptc */
649 665
650 666 uint64_t ips_rx_size_64; /* prc64 */
651 667 uint64_t ips_rx_size_127; /* prc127 */
652 668 uint64_t ips_rx_size_255; /* prc255 */
653 669 uint64_t ips_rx_size_511; /* prc511 */
654 670 uint64_t ips_rx_size_1023; /* prc1023 */
655 671 uint64_t ips_rx_size_1522; /* prc1522 */
656 672 uint64_t ips_rx_size_9522; /* prc9522 */
657 673
658 674 uint64_t ips_tx_size_64; /* ptc64 */
659 675 uint64_t ips_tx_size_127; /* ptc127 */
660 676 uint64_t ips_tx_size_255; /* ptc255 */
661 677 uint64_t ips_tx_size_511; /* ptc511 */
662 678 uint64_t ips_tx_size_1023; /* ptc1023 */
663 679 uint64_t ips_tx_size_1522; /* ptc1522 */
664 680 uint64_t ips_tx_size_9522; /* ptc9522 */
665 681
666 682 uint64_t ips_link_xon_rx; /* lxonrxc */
667 683 uint64_t ips_link_xoff_rx; /* lxoffrxc */
668 684 uint64_t ips_link_xon_tx; /* lxontxc */
669 685 uint64_t ips_link_xoff_tx; /* lxofftxc */
670 686 uint64_t ips_priority_xon_rx[8]; /* pxonrxc[8] */
671 687 uint64_t ips_priority_xoff_rx[8]; /* pxoffrxc[8] */
672 688 uint64_t ips_priority_xon_tx[8]; /* pxontxc[8] */
673 689 uint64_t ips_priority_xoff_tx[8]; /* pxofftxc[8] */
674 690 uint64_t ips_priority_xon_2_xoff[8]; /* rxon2offcnt[8] */
675 691
676 692 uint64_t ips_crc_errors; /* crcerrs */
677 693 uint64_t ips_illegal_bytes; /* illerrc */
678 694 uint64_t ips_mac_local_faults; /* mlfc */
679 695 uint64_t ips_mac_remote_faults; /* mrfc */
680 696 uint64_t ips_rx_length_errors; /* rlec */
681 697 uint64_t ips_rx_undersize; /* ruc */
682 698 uint64_t ips_rx_fragments; /* rfc */
683 699 uint64_t ips_rx_oversize; /* roc */
684 700 uint64_t ips_rx_jabber; /* rjc */
685 701 uint64_t ips_rx_discards; /* rdpc */
686 702 uint64_t ips_rx_vm_discards; /* ldpc */
687 703 uint64_t ips_rx_short_discards; /* mspdc */
688 704 uint64_t ips_tx_dropped_link_down; /* tdold */
689 705 uint64_t ips_rx_unknown_protocol; /* rupp */
690 706 uint64_t ips_rx_err1; /* rxerr1 */
691 707 uint64_t ips_rx_err2; /* rxerr2 */
692 708 } i40e_pf_stats_t;
693 709
694 710 typedef struct i40e_pf_kstats {
695 711 kstat_named_t ipk_rx_bytes; /* gorc */
696 712 kstat_named_t ipk_rx_unicast; /* uprc */
697 713 kstat_named_t ipk_rx_multicast; /* mprc */
698 714 kstat_named_t ipk_rx_broadcast; /* bprc */
699 715 kstat_named_t ipk_tx_bytes; /* gotc */
700 716 kstat_named_t ipk_tx_unicast; /* uptc */
701 717 kstat_named_t ipk_tx_multicast; /* mptc */
702 718 kstat_named_t ipk_tx_broadcast; /* bptc */
703 719
704 720 kstat_named_t ipk_rx_size_64; /* prc64 */
705 721 kstat_named_t ipk_rx_size_127; /* prc127 */
706 722 kstat_named_t ipk_rx_size_255; /* prc255 */
707 723 kstat_named_t ipk_rx_size_511; /* prc511 */
708 724 kstat_named_t ipk_rx_size_1023; /* prc1023 */
709 725 kstat_named_t ipk_rx_size_1522; /* prc1522 */
710 726 kstat_named_t ipk_rx_size_9522; /* prc9522 */
711 727
712 728 kstat_named_t ipk_tx_size_64; /* ptc64 */
713 729 kstat_named_t ipk_tx_size_127; /* ptc127 */
714 730 kstat_named_t ipk_tx_size_255; /* ptc255 */
715 731 kstat_named_t ipk_tx_size_511; /* ptc511 */
716 732 kstat_named_t ipk_tx_size_1023; /* ptc1023 */
717 733 kstat_named_t ipk_tx_size_1522; /* ptc1522 */
718 734 kstat_named_t ipk_tx_size_9522; /* ptc9522 */
719 735
720 736 kstat_named_t ipk_link_xon_rx; /* lxonrxc */
721 737 kstat_named_t ipk_link_xoff_rx; /* lxoffrxc */
722 738 kstat_named_t ipk_link_xon_tx; /* lxontxc */
723 739 kstat_named_t ipk_link_xoff_tx; /* lxofftxc */
724 740 kstat_named_t ipk_priority_xon_rx[8]; /* pxonrxc[8] */
725 741 kstat_named_t ipk_priority_xoff_rx[8]; /* pxoffrxc[8] */
726 742 kstat_named_t ipk_priority_xon_tx[8]; /* pxontxc[8] */
727 743 kstat_named_t ipk_priority_xoff_tx[8]; /* pxofftxc[8] */
728 744 kstat_named_t ipk_priority_xon_2_xoff[8]; /* rxon2offcnt[8] */
729 745
730 746 kstat_named_t ipk_crc_errors; /* crcerrs */
731 747 kstat_named_t ipk_illegal_bytes; /* illerrc */
732 748 kstat_named_t ipk_mac_local_faults; /* mlfc */
733 749 kstat_named_t ipk_mac_remote_faults; /* mrfc */
734 750 kstat_named_t ipk_rx_length_errors; /* rlec */
735 751 kstat_named_t ipk_rx_undersize; /* ruc */
736 752 kstat_named_t ipk_rx_fragments; /* rfc */
737 753 kstat_named_t ipk_rx_oversize; /* roc */
738 754 kstat_named_t ipk_rx_jabber; /* rjc */
739 755 kstat_named_t ipk_rx_discards; /* rdpc */
740 756 kstat_named_t ipk_rx_vm_discards; /* ldpc */
741 757 kstat_named_t ipk_rx_short_discards; /* mspdc */
742 758 kstat_named_t ipk_tx_dropped_link_down; /* tdold */
743 759 kstat_named_t ipk_rx_unknown_protocol; /* rupp */
744 760 kstat_named_t ipk_rx_err1; /* rxerr1 */
745 761 kstat_named_t ipk_rx_err2; /* rxerr2 */
746 762 } i40e_pf_kstats_t;
747 763
748 764 /*
749 765 * Resources that are pooled and specific to a given i40e_t.
750 766 */
751 767 typedef struct i40e_func_rsrc {
752 768 uint_t ifr_nrx_queue;
753 769 uint_t ifr_nrx_queue_used;
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754 770 uint_t ifr_ntx_queue;
755 771 uint_t ifr_trx_queue_used;
756 772 uint_t ifr_nvsis;
757 773 uint_t ifr_nvsis_used;
758 774 uint_t ifr_nmacfilt;
759 775 uint_t ifr_nmacfilt_used;
760 776 uint_t ifr_nmcastfilt;
761 777 uint_t ifr_nmcastfilt_used;
762 778 } i40e_func_rsrc_t;
763 779
780 +typedef struct i40e_vsi {
781 + uint16_t iv_seid;
782 + uint16_t iv_number;
783 + kstat_t *iv_kstats;
784 + i40e_vsi_stats_t iv_stats;
785 + uint16_t iv_stats_id;
786 +} i40e_vsi_t;
787 +
764 788 /*
789 + * While irg_index and irg_grp_hdl aren't used anywhere, they are
790 + * still useful for debugging.
791 + */
792 +typedef struct i40e_rx_group {
793 + uint32_t irg_index; /* index in i40e_rx_groups[] */
794 + uint16_t irg_vsi_seid; /* SEID of VSI for this group */
795 + mac_group_handle_t irg_grp_hdl; /* handle to mac_group_t */
796 + struct i40e *irg_i40e; /* ref to i40e_t */
797 +} i40e_rx_group_t;
798 +
799 +/*
765 800 * Main i40e per-instance state.
766 801 */
767 802 typedef struct i40e {
768 803 list_node_t i40e_glink; /* Global list link */
769 804 list_node_t i40e_dlink; /* Device list link */
770 805 kmutex_t i40e_general_lock; /* General device lock */
771 806
772 807 /*
773 808 * General Data and management
774 809 */
775 810 dev_info_t *i40e_dip;
776 811 int i40e_instance;
777 812 int i40e_fm_capabilities;
778 813 uint_t i40e_state;
779 814 i40e_attach_state_t i40e_attach_progress;
780 815 mac_handle_t i40e_mac_hdl;
781 816 ddi_periodic_t i40e_periodic_id;
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782 817
783 818 /*
784 819 * Pointers to common code data structures and memory for the common
785 820 * code.
786 821 */
787 822 struct i40e_hw i40e_hw_space;
788 823 struct i40e_osdep i40e_osdep_space;
789 824 struct i40e_aq_get_phy_abilities_resp i40e_phy;
790 825 void *i40e_aqbuf;
791 826
827 +#define I40E_DEF_VSI_IDX 0
828 +#define I40E_DEF_VSI(i40e) ((i40e)->i40e_vsis[I40E_DEF_VSI_IDX])
829 +#define I40E_DEF_VSI_SEID(i40e) (I40E_DEF_VSI(i40e).iv_seid)
830 +
792 831 /*
793 832 * Device state, switch information, and resources.
794 833 */
795 - int i40e_vsi_id;
796 - uint16_t i40e_vsi_num;
834 + i40e_vsi_t i40e_vsis[I40E_GROUP_MAX];
835 + uint16_t i40e_mac_seid; /* SEID of physical MAC */
836 + uint16_t i40e_veb_seid; /* switch atop MAC (SEID) */
837 + uint16_t i40e_vsi_avail; /* VSIs avail to this PF */
838 + uint16_t i40e_vsi_used; /* VSIs used by this PF */
797 839 struct i40e_device *i40e_device;
798 840 i40e_func_rsrc_t i40e_resources;
799 841 uint16_t i40e_switch_rsrc_alloc;
800 842 uint16_t i40e_switch_rsrc_actual;
801 843 i40e_switch_rsrc_t *i40e_switch_rsrcs;
802 844 i40e_uaddr_t *i40e_uaddrs;
803 845 i40e_maddr_t *i40e_maddrs;
804 846 int i40e_mcast_promisc_count;
805 847 boolean_t i40e_promisc_on;
806 848 link_state_t i40e_link_state;
807 849 uint32_t i40e_link_speed; /* In Mbps */
808 850 link_duplex_t i40e_link_duplex;
809 851 uint_t i40e_sdu;
810 852 uint_t i40e_frame_max;
811 853
812 854 /*
813 855 * Transmit and receive information, tunables, and MAC info.
814 856 */
815 857 i40e_trqpair_t *i40e_trqpairs;
816 858 boolean_t i40e_mr_enable;
817 - int i40e_num_trqpairs;
859 + uint_t i40e_num_trqpairs; /* total TRQPs (per PF) */
860 + uint_t i40e_num_trqpairs_per_vsi; /* TRQPs per VSI */
818 861 uint_t i40e_other_itr;
819 862
820 - int i40e_num_rx_groups;
863 + i40e_rx_group_t *i40e_rx_groups;
864 + uint_t i40e_num_rx_groups;
821 865 int i40e_num_rx_descs;
822 - mac_group_handle_t i40e_rx_group_handle;
823 866 uint32_t i40e_rx_ring_size;
824 867 uint32_t i40e_rx_buf_size;
825 868 boolean_t i40e_rx_hcksum_enable;
826 869 uint32_t i40e_rx_dma_min;
827 870 uint32_t i40e_rx_limit_per_intr;
828 871 uint_t i40e_rx_itr;
829 872
830 873 int i40e_num_tx_descs;
831 874 uint32_t i40e_tx_ring_size;
832 875 uint32_t i40e_tx_buf_size;
833 876 uint32_t i40e_tx_block_thresh;
834 877 boolean_t i40e_tx_hcksum_enable;
878 + boolean_t i40e_tx_lso_enable;
835 879 uint32_t i40e_tx_dma_min;
836 880 uint_t i40e_tx_itr;
837 881
838 882 /*
839 883 * Interrupt state
840 884 */
841 885 uint_t i40e_intr_pri;
842 886 uint_t i40e_intr_force;
843 887 uint_t i40e_intr_type;
844 888 int i40e_intr_cap;
845 889 uint32_t i40e_intr_count;
846 890 uint32_t i40e_intr_count_max;
847 891 uint32_t i40e_intr_count_min;
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848 892 size_t i40e_intr_size;
849 893 ddi_intr_handle_t *i40e_intr_handles;
850 894 ddi_cb_handle_t i40e_callback_handle;
851 895
852 896 /*
853 897 * DMA attributes. See i40e_transceiver.c for why we have copies of them
854 898 * in the i40e_t.
855 899 */
856 900 ddi_dma_attr_t i40e_static_dma_attr;
857 901 ddi_dma_attr_t i40e_txbind_dma_attr;
902 + ddi_dma_attr_t i40e_txbind_lso_dma_attr;
858 903 ddi_device_acc_attr_t i40e_desc_acc_attr;
859 904 ddi_device_acc_attr_t i40e_buf_acc_attr;
860 905
861 906 /*
862 907 * The following two fields are used to protect and keep track of
863 908 * outstanding, loaned buffers to MAC. If we have these, we can't
864 909 * detach as we have active DMA memory outstanding.
865 910 */
866 911 kmutex_t i40e_rx_pending_lock;
867 912 kcondvar_t i40e_rx_pending_cv;
868 913 uint32_t i40e_rx_pending;
869 914
870 915 /*
871 916 * PF statistics and VSI statistics.
872 917 */
873 918 kmutex_t i40e_stat_lock;
874 919 kstat_t *i40e_pf_kstat;
875 - kstat_t *i40e_vsi_kstat;
876 920 i40e_pf_stats_t i40e_pf_stat;
877 - i40e_vsi_stats_t i40e_vsi_stat;
878 - uint16_t i40e_vsi_stat_id;
879 921
880 922 /*
881 923 * Misc. stats and counters that should maybe one day be kstats.
882 924 */
883 925 uint64_t i40e_s_link_status_errs;
884 926 uint32_t i40e_s_link_status_lasterr;
885 927
886 928 /*
887 929 * LED information. Note this state is only modified in
888 930 * i40e_gld_set_led() which is protected by MAC's serializer lock.
889 931 */
890 932 uint32_t i40e_led_status;
891 933 boolean_t i40e_led_saved;
892 934 } i40e_t;
893 935
894 936 /*
895 937 * The i40e_device represents a PCI device which encapsulates multiple physical
896 938 * functions which are represented as an i40e_t. This is used to track the use
897 939 * of pooled resources throughout all of the various devices.
898 940 */
899 941 typedef struct i40e_device {
900 942 list_node_t id_link;
901 943 dev_info_t *id_parent;
902 944 uint_t id_pci_bus;
903 945 uint_t id_pci_device;
904 946 uint_t id_nfuncs; /* Total number of functions */
905 947 uint_t id_nreg; /* Total number present */
906 948 list_t id_i40e_list; /* List of i40e_t's registered */
907 949 i40e_switch_rsrc_t *id_rsrcs; /* Switch resources for this PF */
908 950 uint_t id_rsrcs_alloc; /* Total allocated resources */
909 951 uint_t id_rsrcs_act; /* Actual number of resources */
910 952 } i40e_device_t;
911 953
912 954 /* Values for the interrupt forcing on the NIC. */
913 955 #define I40E_INTR_NONE 0
914 956 #define I40E_INTR_MSIX 1
915 957 #define I40E_INTR_MSI 2
916 958 #define I40E_INTR_LEGACY 3
917 959
918 960 /* Hint that we don't want to do any polling... */
919 961 #define I40E_POLL_NULL -1
920 962
921 963 /*
922 964 * Logging functions.
923 965 */
924 966 /*PRINTFLIKE2*/
925 967 extern void i40e_error(i40e_t *, const char *, ...) __KPRINTFLIKE(2);
926 968 /*PRINTFLIKE2*/
927 969 extern void i40e_notice(i40e_t *, const char *, ...) __KPRINTFLIKE(2);
928 970 /*PRINTFLIKE2*/
929 971 extern void i40e_log(i40e_t *, const char *, ...) __KPRINTFLIKE(2);
930 972
931 973 /*
932 974 * General link handling functions.
933 975 */
934 976 extern void i40e_link_check(i40e_t *);
935 977 extern void i40e_update_mtu(i40e_t *);
936 978
937 979 /*
938 980 * FMA functions.
939 981 */
940 982 extern int i40e_check_acc_handle(ddi_acc_handle_t);
941 983 extern int i40e_check_dma_handle(ddi_dma_handle_t);
942 984 extern void i40e_fm_ereport(i40e_t *, char *);
943 985
944 986 /*
945 987 * Interrupt handlers and interrupt handler setup.
946 988 */
947 989 extern void i40e_intr_chip_init(i40e_t *);
948 990 extern void i40e_intr_chip_fini(i40e_t *);
949 991 extern uint_t i40e_intr_msix(void *, void *);
950 992 extern uint_t i40e_intr_msi(void *, void *);
951 993 extern uint_t i40e_intr_legacy(void *, void *);
952 994 extern void i40e_intr_io_enable_all(i40e_t *);
953 995 extern void i40e_intr_io_disable_all(i40e_t *);
954 996 extern void i40e_intr_io_clear_cause(i40e_t *);
955 997 extern void i40e_intr_rx_queue_disable(i40e_trqpair_t *);
956 998 extern void i40e_intr_rx_queue_enable(i40e_trqpair_t *);
957 999 extern void i40e_intr_set_itr(i40e_t *, i40e_itr_index_t, uint_t);
958 1000
959 1001 /*
960 1002 * Receive-side functions
961 1003 */
962 1004 extern mblk_t *i40e_ring_rx(i40e_trqpair_t *, int);
963 1005 extern mblk_t *i40e_ring_rx_poll(void *, int);
964 1006 extern void i40e_rx_recycle(caddr_t);
965 1007
966 1008 /*
967 1009 * Transmit-side functions
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968 1010 */
969 1011 mblk_t *i40e_ring_tx(void *, mblk_t *);
970 1012 extern void i40e_tx_recycle_ring(i40e_trqpair_t *);
971 1013 extern void i40e_tx_cleanup_ring(i40e_trqpair_t *);
972 1014
973 1015 /*
974 1016 * Statistics functions.
975 1017 */
976 1018 extern boolean_t i40e_stats_init(i40e_t *);
977 1019 extern void i40e_stats_fini(i40e_t *);
978 -extern boolean_t i40e_stat_vsi_init(i40e_t *);
979 -extern void i40e_stat_vsi_fini(i40e_t *);
1020 +extern boolean_t i40e_stat_vsi_init(i40e_t *, uint_t);
1021 +extern void i40e_stat_vsi_fini(i40e_t *, uint_t);
980 1022 extern boolean_t i40e_stats_trqpair_init(i40e_trqpair_t *);
981 1023 extern void i40e_stats_trqpair_fini(i40e_trqpair_t *);
982 1024 extern int i40e_m_stat(void *, uint_t, uint64_t *);
983 1025 extern int i40e_rx_ring_stat(mac_ring_driver_t, uint_t, uint64_t *);
984 1026 extern int i40e_tx_ring_stat(mac_ring_driver_t, uint_t, uint64_t *);
985 1027
986 1028 /*
987 1029 * MAC/GLDv3 functions, and functions called by MAC/GLDv3 support code.
988 1030 */
989 1031 extern boolean_t i40e_register_mac(i40e_t *);
990 1032 extern boolean_t i40e_start(i40e_t *, boolean_t);
991 1033 extern void i40e_stop(i40e_t *, boolean_t);
992 1034
993 1035 /*
994 1036 * DMA & buffer functions and attributes
995 1037 */
996 1038 extern void i40e_init_dma_attrs(i40e_t *, boolean_t);
997 1039 extern boolean_t i40e_alloc_ring_mem(i40e_t *);
998 1040 extern void i40e_free_ring_mem(i40e_t *, boolean_t);
999 1041
1000 1042 #ifdef __cplusplus
1001 1043 }
1002 1044 #endif
1003 1045
1004 1046 #endif /* _I40E_SW_H */
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