1 /*
2 * This file and its contents are supplied under the terms of the
3 * Common Development and Distribution License ("CDDL"), version 1.0.
4 * You may only use this file in accordance with the terms of version
5 * 1.0 of the CDDL.
6 *
7 * A full copy of the text of the CDDL should have accompanied this
8 * source. A copy of the CDDL is also available via the Internet at
9 * http://www.illumos.org/license/CDDL.
10 */
11
12 /*
13 * Copyright 2015 OmniTI Computer Consulting, Inc. All rights reserved.
14 * Copyright (c) 2017, Joyent, Inc.
15 * Copyright 2017 Tegile Systems, Inc. All rights reserved.
16 */
17
18 /*
19 * Please see i40e_main.c for an introduction to the device driver, its layout,
20 * and more.
21 */
22
23 #ifndef _I40E_SW_H
24 #define _I40E_SW_H
25
26 #ifdef __cplusplus
27 extern "C" {
28 #endif
29
30 #include <sys/types.h>
31 #include <sys/conf.h>
32 #include <sys/debug.h>
33 #include <sys/stropts.h>
34 #include <sys/stream.h>
135 * values for TX allow for 5k interrupts per second. For other class interrupts,
136 * we limit ourselves to a rate of 2k/s.
137 */
138 #define I40E_MIN_ITR 0x0000
139 #define I40E_MAX_ITR 0x0FF0
140 #define I40E_DEF_RX_ITR 0x0019
141 #define I40E_DEF_TX_ITR 0x0064
142 #define I40E_DEF_OTHER_ITR 0x00FA
143
144 /*
145 * Indexes into the three ITR registers that we have.
146 */
147 typedef enum i40e_itr_index {
148 I40E_ITR_INDEX_RX = 0x0,
149 I40E_ITR_INDEX_TX = 0x1,
150 I40E_ITR_INDEX_OTHER = 0x2,
151 I40E_ITR_INDEX_NONE = 0x3
152 } i40e_itr_index_t;
153
154 /*
155 * Table 1-5 of the PRM notes that LSO supports up to 256 KB.
156 */
157 #define I40E_LSO_MAXLEN (256 * 1024)
158
159 #define I40E_CYCLIC_PERIOD NANOSEC /* 1 second */
160 #define I40E_DRAIN_RX_WAIT (500 * MILLISEC) /* In us */
161
162 /*
163 * All the other queue types for are defined by the common code. However, this
164 * is the constant to indicate that it's terminated.
165 */
166 #define I40E_QUEUE_TYPE_EOL 0x7FF
167
168 /*
169 * See the comments in i40e_transceiver.c as to the purpose of this value and
170 * how it's used to ensure that the IP header is eventually aligned when it's
171 * received by the OS.
172 */
173 #define I40E_BUF_IPHDR_ALIGNMENT 2
174
175 /*
176 * The XL710 controller has a limit of eight buffers being allowed to be used
177 * for the transmission of a single frame. This is defined in 8.4.1 - Transmit
178 * Packet in System Memory.
179 */
180 #define I40E_TX_MAX_COOKIE 8
181
182 /*
183 * Sizing to determine the amount of available descriptors at which we'll
184 * consider ourselves blocked. Also, when we have these available, we'll then
185 * consider ourselves available to transmit to MAC again. Strictly speaking, the
186 * MAX is based on the ring size. The default sizing is based on ixgbe.
187 */
188 #define I40E_MIN_TX_BLOCK_THRESH I40E_TX_MAX_COOKIE
189 #define I40E_DEF_TX_BLOCK_THRESH I40E_MIN_TX_BLOCK_THRESH
190
191 /*
192 * Sizing for DMA thresholds. These are used to indicate whether or not we
193 * should perform a bcopy or a DMA binding of a given message block. The range
194 * allows for setting things such that we'll always do a bcopy (a high value) or
195 * always perform a DMA binding (a low value).
196 */
197 #define I40E_MIN_RX_DMA_THRESH 0
198 #define I40E_DEF_RX_DMA_THRESH 256
199 #define I40E_MAX_RX_DMA_THRESH INT32_MAX
200
201 #define I40E_MIN_TX_DMA_THRESH 0
202 #define I40E_DEF_TX_DMA_THRESH 256
203 #define I40E_MAX_TX_DMA_THRESH INT32_MAX
204
205 /*
206 * Resource sizing counts. There are various aspects of hardware where we may
207 * have some variable number of elements that we need to handle. Such as the
208 * hardware capabilities and switch capacities. We cannot know a priori how many
209 * elements to do, so instead we take a starting guess and then will grow it up
210 * to an upper bound on a number of elements, to limit memory consumption in
211 * case of a hardware bug.
212 */
213 #define I40E_HW_CAP_DEFAULT 40
214 #define I40E_SWITCH_CAP_DEFAULT 25
215
216 /*
217 * Host Memory Context related constants.
218 */
219 #define I40E_HMC_RX_CTX_UNIT 128
220 #define I40E_HMC_RX_DBUFF_MIN 1024
221 #define I40E_HMC_RX_DBUFF_MAX (16 * 1024 - 128)
222 #define I40E_HMC_RX_DTYPE_NOSPLIT 0
223 #define I40E_HMC_RX_DSIZE_32BYTE 1
224 #define I40E_HMC_RX_CRCSTRIP_ENABLE 1
225 #define I40E_HMC_RX_FC_DISABLE 0
226 #define I40E_HMC_RX_L2TAGORDER 1
227 #define I40E_HMC_RX_HDRSPLIT_DISABLE 0
228 #define I40E_HMC_RX_INVLAN_DONTSTRIP 0
229 #define I40E_HMC_RX_TPH_DISABLE 0
230 #define I40E_HMC_RX_LOWRXQ_NOINTR 0
231 #define I40E_HMC_RX_PREFENA 1
232
233 #define I40E_HMC_TX_CTX_UNIT 128
234 #define I40E_HMC_TX_NEW_CONTEXT 1
235 #define I40E_HMC_TX_FC_DISABLE 0
236 #define I40E_HMC_TX_TS_DISABLE 0
237 #define I40E_HMC_TX_FD_DISABLE 0
238 #define I40E_HMC_TX_ALT_VLAN_DISABLE 0
239 #define I40E_HMC_TX_WB_ENABLE 1
240 #define I40E_HMC_TX_TPH_DISABLE 0
241
242 /*
243 * Whenever we establish and create a VSI, we need to assign some number of
244 * queues that it's allowed to access from the PF. Because we only have a single
245 * VSI per PF at this time, we assign it all the queues.
246 *
247 * Many of the devices support what's called Data-center Bridging. Which is a
248 * feature that we don't have much use of at this time. However, we still need
249 * to fill in this information. We follow the guidance of the note in Table 7-80
250 * which talks about bytes 62-77. It says that if we don't want to assign
251 * anything to traffic classes, we should set the field to zero. Effectively
252 * this means that everything in the system is assigned to traffic class zero.
253 */
254 #define I40E_ASSIGN_ALL_QUEUES 0
255 #define I40E_TRAFFIC_CLASS_NO_QUEUES 0
256
257 /*
258 * This defines the error mask that we care about from rx descriptors. Currently
259 * we're only concerned with the general errors and oversize errors.
260 */
261 #define I40E_RX_ERR_BITS ((1 << I40E_RX_DESC_ERROR_RXE_SHIFT) | \
262 (1 << I40E_RX_DESC_ERROR_OVERSIZE_SHIFT))
263
264 /*
265 * Property sizing macros for firmware versions, etc. They need to be large
266 * enough to hold 32-bit quantities transformed to strings as %d.%d or %x.
267 */
268 #define I40E_DDI_PROP_LEN 64
269
270 /*
271 * We currently consolidate some overrides that we use in the code here. These
272 * will be gone in the fullness of time, but as we're bringing up the device,
273 * this is what we use.
274 */
275 #define I40E_GROUP_MAX 1
276 #define I40E_TRQPAIR_MAX 1
277
278 #define I40E_GROUP_NOMSIX 1
279 #define I40E_TRQPAIR_NOMSIX 1
280
281 /*
282 * It seems reasonable to cast this to void because the only reason that we
283 * should be getting a DDI_FAILURE is due to the fact that we specify addresses
284 * out of range. Because we specify no offset or address, it shouldn't happen.
285 */
286 #ifdef DEBUG
287 #define I40E_DMA_SYNC(handle, flag) ASSERT0(ddi_dma_sync( \
288 (handle)->dmab_dma_handle, 0, 0, \
289 (flag)))
290 #else /* !DEBUG */
291 #define I40E_DMA_SYNC(handle, flag) ((void) ddi_dma_sync( \
292 (handle)->dmab_dma_handle, 0, 0, \
293 (flag)))
294 #endif /* DEBUG */
295
296 /*
388 ddi_acc_handle_t dmab_acc_handle; /* Data access handle */
389 ddi_dma_handle_t dmab_dma_handle; /* DMA handle */
390 size_t dmab_size; /* Buffer size */
391 size_t dmab_len; /* Data length in the buffer */
392 } i40e_dma_buffer_t;
393
394 /*
395 * RX Control Block
396 */
397 typedef struct i40e_rx_control_block {
398 mblk_t *rcb_mp;
399 uint32_t rcb_ref;
400 i40e_dma_buffer_t rcb_dma;
401 frtn_t rcb_free_rtn;
402 struct i40e_rx_data *rcb_rxd;
403 } i40e_rx_control_block_t;
404
405 typedef enum {
406 I40E_TX_NONE,
407 I40E_TX_COPY,
408 I40E_TX_DMA
409 } i40e_tx_type_t;
410
411 typedef struct i40e_tx_desc i40e_tx_desc_t;
412 typedef union i40e_32byte_rx_desc i40e_rx_desc_t;
413
414 typedef struct i40e_tx_control_block {
415 struct i40e_tx_control_block *tcb_next;
416 mblk_t *tcb_mp;
417 i40e_tx_type_t tcb_type;
418 ddi_dma_handle_t tcb_dma_handle;
419 i40e_dma_buffer_t tcb_dma;
420 } i40e_tx_control_block_t;
421
422 /*
423 * Receive ring data (used below).
424 */
425 typedef struct i40e_rx_data {
426 struct i40e *rxd_i40e;
427
428 /*
429 * RX descriptor ring definitions
430 */
431 i40e_dma_buffer_t rxd_desc_area; /* DMA buffer of rx desc ring */
432 i40e_rx_desc_t *rxd_desc_ring; /* Rx desc ring */
433 uint32_t rxd_desc_next; /* Index of next rx desc */
434
435 /*
436 * RX control block list definitions
437 */
438 kmutex_t rxd_free_lock; /* Lock to protect free data */
439 i40e_rx_control_block_t *rxd_rcb_area; /* Array of control blocks */
500 kstat_named_t irxs_hck_v4hdrok; /* Valid IPv4 Header */
501 kstat_named_t irxs_hck_l4hdrok; /* Valid L4 Header */
502 kstat_named_t irxs_hck_unknown; /* !pinfo.known */
503 kstat_named_t irxs_hck_nol3l4p; /* Missing L3L4P bit in desc */
504 kstat_named_t irxs_hck_iperr; /* IPE error bit set */
505 kstat_named_t irxs_hck_eiperr; /* EIPE error bit set */
506 kstat_named_t irxs_hck_l4err; /* L4E error bit set */
507 kstat_named_t irxs_hck_v6skip; /* IPv6 case hw fails on */
508 kstat_named_t irxs_hck_set; /* Total times we set cksum */
509 kstat_named_t irxs_hck_miss; /* Times with zero cksum bits */
510 } i40e_rxq_stat_t;
511
512 /*
513 * Collection of TX Statistics on a given queue
514 */
515 typedef struct i40e_txq_stat {
516 kstat_named_t itxs_bytes; /* Bytes out on queue */
517 kstat_named_t itxs_packets; /* Packets out on queue */
518 kstat_named_t itxs_descriptors; /* Descriptors issued */
519 kstat_named_t itxs_recycled; /* Descriptors reclaimed */
520 /*
521 * Various failure conditions.
522 */
523 kstat_named_t itxs_hck_meoifail; /* ether offload failures */
524 kstat_named_t itxs_hck_nol2info; /* Missing l2 info */
525 kstat_named_t itxs_hck_nol3info; /* Missing l3 info */
526 kstat_named_t itxs_hck_nol4info; /* Missing l4 info */
527 kstat_named_t itxs_hck_badl3; /* Not IPv4/IPv6 */
528 kstat_named_t itxs_hck_badl4; /* Bad L4 Paylaod */
529
530 kstat_named_t itxs_err_notcb; /* No tcb's available */
531 kstat_named_t itxs_err_nodescs; /* No tcb's available */
532 kstat_named_t itxs_err_context; /* Total context failures */
533
534 kstat_named_t itxs_num_unblocked; /* Number of MAC unblocks */
535 } i40e_txq_stat_t;
536
537 /*
538 * An instance of an XL710 transmit/receive queue pair. This currently
539 * represents a combination of both a transmit and receive ring, though they
540 * should really be split apart into separate logical structures. Unfortunately,
541 * during initial work we mistakenly joined them together.
542 */
543 typedef struct i40e_trqpair {
544 struct i40e *itrq_i40e;
545
546 /* Receive-side structures. */
547 kmutex_t itrq_rx_lock;
548 mac_ring_handle_t itrq_macrxring; /* Receive ring handle. */
744 kstat_named_t ipk_rx_err1; /* rxerr1 */
745 kstat_named_t ipk_rx_err2; /* rxerr2 */
746 } i40e_pf_kstats_t;
747
748 /*
749 * Resources that are pooled and specific to a given i40e_t.
750 */
751 typedef struct i40e_func_rsrc {
752 uint_t ifr_nrx_queue;
753 uint_t ifr_nrx_queue_used;
754 uint_t ifr_ntx_queue;
755 uint_t ifr_trx_queue_used;
756 uint_t ifr_nvsis;
757 uint_t ifr_nvsis_used;
758 uint_t ifr_nmacfilt;
759 uint_t ifr_nmacfilt_used;
760 uint_t ifr_nmcastfilt;
761 uint_t ifr_nmcastfilt_used;
762 } i40e_func_rsrc_t;
763
764 /*
765 * Main i40e per-instance state.
766 */
767 typedef struct i40e {
768 list_node_t i40e_glink; /* Global list link */
769 list_node_t i40e_dlink; /* Device list link */
770 kmutex_t i40e_general_lock; /* General device lock */
771
772 /*
773 * General Data and management
774 */
775 dev_info_t *i40e_dip;
776 int i40e_instance;
777 int i40e_fm_capabilities;
778 uint_t i40e_state;
779 i40e_attach_state_t i40e_attach_progress;
780 mac_handle_t i40e_mac_hdl;
781 ddi_periodic_t i40e_periodic_id;
782
783 /*
784 * Pointers to common code data structures and memory for the common
785 * code.
786 */
787 struct i40e_hw i40e_hw_space;
788 struct i40e_osdep i40e_osdep_space;
789 struct i40e_aq_get_phy_abilities_resp i40e_phy;
790 void *i40e_aqbuf;
791
792 /*
793 * Device state, switch information, and resources.
794 */
795 int i40e_vsi_id;
796 uint16_t i40e_vsi_num;
797 struct i40e_device *i40e_device;
798 i40e_func_rsrc_t i40e_resources;
799 uint16_t i40e_switch_rsrc_alloc;
800 uint16_t i40e_switch_rsrc_actual;
801 i40e_switch_rsrc_t *i40e_switch_rsrcs;
802 i40e_uaddr_t *i40e_uaddrs;
803 i40e_maddr_t *i40e_maddrs;
804 int i40e_mcast_promisc_count;
805 boolean_t i40e_promisc_on;
806 link_state_t i40e_link_state;
807 uint32_t i40e_link_speed; /* In Mbps */
808 link_duplex_t i40e_link_duplex;
809 uint_t i40e_sdu;
810 uint_t i40e_frame_max;
811
812 /*
813 * Transmit and receive information, tunables, and MAC info.
814 */
815 i40e_trqpair_t *i40e_trqpairs;
816 boolean_t i40e_mr_enable;
817 int i40e_num_trqpairs;
818 uint_t i40e_other_itr;
819
820 int i40e_num_rx_groups;
821 int i40e_num_rx_descs;
822 mac_group_handle_t i40e_rx_group_handle;
823 uint32_t i40e_rx_ring_size;
824 uint32_t i40e_rx_buf_size;
825 boolean_t i40e_rx_hcksum_enable;
826 uint32_t i40e_rx_dma_min;
827 uint32_t i40e_rx_limit_per_intr;
828 uint_t i40e_rx_itr;
829
830 int i40e_num_tx_descs;
831 uint32_t i40e_tx_ring_size;
832 uint32_t i40e_tx_buf_size;
833 uint32_t i40e_tx_block_thresh;
834 boolean_t i40e_tx_hcksum_enable;
835 uint32_t i40e_tx_dma_min;
836 uint_t i40e_tx_itr;
837
838 /*
839 * Interrupt state
840 */
841 uint_t i40e_intr_pri;
842 uint_t i40e_intr_force;
843 uint_t i40e_intr_type;
844 int i40e_intr_cap;
845 uint32_t i40e_intr_count;
846 uint32_t i40e_intr_count_max;
847 uint32_t i40e_intr_count_min;
848 size_t i40e_intr_size;
849 ddi_intr_handle_t *i40e_intr_handles;
850 ddi_cb_handle_t i40e_callback_handle;
851
852 /*
853 * DMA attributes. See i40e_transceiver.c for why we have copies of them
854 * in the i40e_t.
855 */
856 ddi_dma_attr_t i40e_static_dma_attr;
857 ddi_dma_attr_t i40e_txbind_dma_attr;
858 ddi_device_acc_attr_t i40e_desc_acc_attr;
859 ddi_device_acc_attr_t i40e_buf_acc_attr;
860
861 /*
862 * The following two fields are used to protect and keep track of
863 * outstanding, loaned buffers to MAC. If we have these, we can't
864 * detach as we have active DMA memory outstanding.
865 */
866 kmutex_t i40e_rx_pending_lock;
867 kcondvar_t i40e_rx_pending_cv;
868 uint32_t i40e_rx_pending;
869
870 /*
871 * PF statistics and VSI statistics.
872 */
873 kmutex_t i40e_stat_lock;
874 kstat_t *i40e_pf_kstat;
875 kstat_t *i40e_vsi_kstat;
876 i40e_pf_stats_t i40e_pf_stat;
877 i40e_vsi_stats_t i40e_vsi_stat;
878 uint16_t i40e_vsi_stat_id;
879
880 /*
881 * Misc. stats and counters that should maybe one day be kstats.
882 */
883 uint64_t i40e_s_link_status_errs;
884 uint32_t i40e_s_link_status_lasterr;
885
886 /*
887 * LED information. Note this state is only modified in
888 * i40e_gld_set_led() which is protected by MAC's serializer lock.
889 */
890 uint32_t i40e_led_status;
891 boolean_t i40e_led_saved;
892 } i40e_t;
893
894 /*
895 * The i40e_device represents a PCI device which encapsulates multiple physical
896 * functions which are represented as an i40e_t. This is used to track the use
897 * of pooled resources throughout all of the various devices.
898 */
958
959 /*
960 * Receive-side functions
961 */
962 extern mblk_t *i40e_ring_rx(i40e_trqpair_t *, int);
963 extern mblk_t *i40e_ring_rx_poll(void *, int);
964 extern void i40e_rx_recycle(caddr_t);
965
966 /*
967 * Transmit-side functions
968 */
969 mblk_t *i40e_ring_tx(void *, mblk_t *);
970 extern void i40e_tx_recycle_ring(i40e_trqpair_t *);
971 extern void i40e_tx_cleanup_ring(i40e_trqpair_t *);
972
973 /*
974 * Statistics functions.
975 */
976 extern boolean_t i40e_stats_init(i40e_t *);
977 extern void i40e_stats_fini(i40e_t *);
978 extern boolean_t i40e_stat_vsi_init(i40e_t *);
979 extern void i40e_stat_vsi_fini(i40e_t *);
980 extern boolean_t i40e_stats_trqpair_init(i40e_trqpair_t *);
981 extern void i40e_stats_trqpair_fini(i40e_trqpair_t *);
982 extern int i40e_m_stat(void *, uint_t, uint64_t *);
983 extern int i40e_rx_ring_stat(mac_ring_driver_t, uint_t, uint64_t *);
984 extern int i40e_tx_ring_stat(mac_ring_driver_t, uint_t, uint64_t *);
985
986 /*
987 * MAC/GLDv3 functions, and functions called by MAC/GLDv3 support code.
988 */
989 extern boolean_t i40e_register_mac(i40e_t *);
990 extern boolean_t i40e_start(i40e_t *, boolean_t);
991 extern void i40e_stop(i40e_t *, boolean_t);
992
993 /*
994 * DMA & buffer functions and attributes
995 */
996 extern void i40e_init_dma_attrs(i40e_t *, boolean_t);
997 extern boolean_t i40e_alloc_ring_mem(i40e_t *);
998 extern void i40e_free_ring_mem(i40e_t *, boolean_t);
999
|
1 /*
2 * This file and its contents are supplied under the terms of the
3 * Common Development and Distribution License ("CDDL"), version 1.0.
4 * You may only use this file in accordance with the terms of version
5 * 1.0 of the CDDL.
6 *
7 * A full copy of the text of the CDDL should have accompanied this
8 * source. A copy of the CDDL is also available via the Internet at
9 * http://www.illumos.org/license/CDDL.
10 */
11
12 /*
13 * Copyright 2015 OmniTI Computer Consulting, Inc. All rights reserved.
14 * Copyright 2019 Joyent, Inc.
15 * Copyright 2017 Tegile Systems, Inc. All rights reserved.
16 */
17
18 /*
19 * Please see i40e_main.c for an introduction to the device driver, its layout,
20 * and more.
21 */
22
23 #ifndef _I40E_SW_H
24 #define _I40E_SW_H
25
26 #ifdef __cplusplus
27 extern "C" {
28 #endif
29
30 #include <sys/types.h>
31 #include <sys/conf.h>
32 #include <sys/debug.h>
33 #include <sys/stropts.h>
34 #include <sys/stream.h>
135 * values for TX allow for 5k interrupts per second. For other class interrupts,
136 * we limit ourselves to a rate of 2k/s.
137 */
138 #define I40E_MIN_ITR 0x0000
139 #define I40E_MAX_ITR 0x0FF0
140 #define I40E_DEF_RX_ITR 0x0019
141 #define I40E_DEF_TX_ITR 0x0064
142 #define I40E_DEF_OTHER_ITR 0x00FA
143
144 /*
145 * Indexes into the three ITR registers that we have.
146 */
147 typedef enum i40e_itr_index {
148 I40E_ITR_INDEX_RX = 0x0,
149 I40E_ITR_INDEX_TX = 0x1,
150 I40E_ITR_INDEX_OTHER = 0x2,
151 I40E_ITR_INDEX_NONE = 0x3
152 } i40e_itr_index_t;
153
154 /*
155 * The hardware claims to support LSO up to 256 KB, but due to the limitations
156 * imposed by the IP header for non-jumbo frames, we cap it at 64 KB.
157 */
158 #define I40E_LSO_MAXLEN (64 * 1024)
159
160 #define I40E_CYCLIC_PERIOD NANOSEC /* 1 second */
161 #define I40E_DRAIN_RX_WAIT (500 * MILLISEC) /* In us */
162
163 /*
164 * All the other queue types for are defined by the common code. However, this
165 * is the constant to indicate that it's terminated.
166 */
167 #define I40E_QUEUE_TYPE_EOL 0x7FF
168
169 /*
170 * See the comments in i40e_transceiver.c as to the purpose of this value and
171 * how it's used to ensure that the IP header is eventually aligned when it's
172 * received by the OS.
173 */
174 #define I40E_BUF_IPHDR_ALIGNMENT 2
175
176 /*
177 * The XL710 controller has a total of eight buffers available for the
178 * transmission of any single frame. This is defined in 8.4.1 - Transmit
179 * Packet in System Memory.
180 */
181 #define I40E_TX_MAX_COOKIE 8
182
183 /*
184 * An LSO frame can be as large as 64KB, so we allow a DMA bind to span more
185 * cookies than a non-LSO frame. The key here to is to select a value such
186 * that once the HW has chunked up the LSO frame into MSS-sized segments that no
187 * single segment spans more than 8 cookies (see comments for
188 * I40E_TX_MAX_COOKIE)
189 */
190 #define I40E_TX_LSO_MAX_COOKIE 32
191
192 /*
193 * Sizing to determine the amount of available descriptors at which we'll
194 * consider ourselves blocked. Also, when we have these available, we'll then
195 * consider ourselves available to transmit to MAC again. Strictly speaking, the
196 * MAX is based on the ring size. The default sizing is based on ixgbe.
197 */
198 #define I40E_MIN_TX_BLOCK_THRESH I40E_TX_MAX_COOKIE
199 #define I40E_DEF_TX_BLOCK_THRESH I40E_MIN_TX_BLOCK_THRESH
200
201 /*
202 * Sizing for DMA thresholds. These are used to indicate whether or not we
203 * should perform a bcopy or a DMA binding of a given message block. The range
204 * allows for setting things such that we'll always do a bcopy (a high value) or
205 * always perform a DMA binding (a low value).
206 */
207 #define I40E_MIN_RX_DMA_THRESH 0
208 #define I40E_DEF_RX_DMA_THRESH 256
209 #define I40E_MAX_RX_DMA_THRESH INT32_MAX
210
211 #define I40E_MIN_TX_DMA_THRESH 0
212 #define I40E_DEF_TX_DMA_THRESH 256
213 #define I40E_MAX_TX_DMA_THRESH INT32_MAX
214
215 /*
216 * The max size of each individual tx buffer is 16KB - 1.
217 * See table 8-17
218 */
219 #define I40E_MAX_TX_BUFSZ 0x0000000000003FFFull
220
221 /*
222 * Resource sizing counts. There are various aspects of hardware where we may
223 * have some variable number of elements that we need to handle. Such as the
224 * hardware capabilities and switch capacities. We cannot know a priori how many
225 * elements to do, so instead we take a starting guess and then will grow it up
226 * to an upper bound on a number of elements, to limit memory consumption in
227 * case of a hardware bug.
228 */
229 #define I40E_HW_CAP_DEFAULT 40
230 #define I40E_SWITCH_CAP_DEFAULT 25
231
232 /*
233 * Host Memory Context related constants.
234 */
235 #define I40E_HMC_RX_CTX_UNIT 128
236 #define I40E_HMC_RX_DBUFF_MIN 1024
237 #define I40E_HMC_RX_DBUFF_MAX (16 * 1024 - 128)
238 #define I40E_HMC_RX_DTYPE_NOSPLIT 0
239 #define I40E_HMC_RX_DSIZE_32BYTE 1
240 #define I40E_HMC_RX_CRCSTRIP_ENABLE 1
241 #define I40E_HMC_RX_FC_DISABLE 0
242 #define I40E_HMC_RX_L2TAGORDER 1
243 #define I40E_HMC_RX_HDRSPLIT_DISABLE 0
244 #define I40E_HMC_RX_INVLAN_DONTSTRIP 0
245 #define I40E_HMC_RX_TPH_DISABLE 0
246 #define I40E_HMC_RX_LOWRXQ_NOINTR 0
247 #define I40E_HMC_RX_PREFENA 1
248
249 #define I40E_HMC_TX_CTX_UNIT 128
250 #define I40E_HMC_TX_NEW_CONTEXT 1
251 #define I40E_HMC_TX_FC_DISABLE 0
252 #define I40E_HMC_TX_TS_DISABLE 0
253 #define I40E_HMC_TX_FD_DISABLE 0
254 #define I40E_HMC_TX_ALT_VLAN_DISABLE 0
255 #define I40E_HMC_TX_WB_ENABLE 1
256 #define I40E_HMC_TX_TPH_DISABLE 0
257
258 /*
259 * This defines the error mask that we care about from rx descriptors. Currently
260 * we're only concerned with the general errors and oversize errors.
261 */
262 #define I40E_RX_ERR_BITS ((1 << I40E_RX_DESC_ERROR_RXE_SHIFT) | \
263 (1 << I40E_RX_DESC_ERROR_OVERSIZE_SHIFT))
264
265 /*
266 * Property sizing macros for firmware versions, etc. They need to be large
267 * enough to hold 32-bit quantities transformed to strings as %d.%d or %x.
268 */
269 #define I40E_DDI_PROP_LEN 64
270
271 /*
272 * Place an artificial limit on the max number of groups. The X710
273 * series supports up to 384 VSIs to be partitioned across PFs as the
274 * driver sees fit. But until we support more interrupts this seems
275 * like a good place to start.
276 */
277 #define I40E_GROUP_MAX 32
278
279 #define I40E_GROUP_NOMSIX 1
280 #define I40E_TRQPAIR_NOMSIX 1
281
282 /*
283 * It seems reasonable to cast this to void because the only reason that we
284 * should be getting a DDI_FAILURE is due to the fact that we specify addresses
285 * out of range. Because we specify no offset or address, it shouldn't happen.
286 */
287 #ifdef DEBUG
288 #define I40E_DMA_SYNC(handle, flag) ASSERT0(ddi_dma_sync( \
289 (handle)->dmab_dma_handle, 0, 0, \
290 (flag)))
291 #else /* !DEBUG */
292 #define I40E_DMA_SYNC(handle, flag) ((void) ddi_dma_sync( \
293 (handle)->dmab_dma_handle, 0, 0, \
294 (flag)))
295 #endif /* DEBUG */
296
297 /*
389 ddi_acc_handle_t dmab_acc_handle; /* Data access handle */
390 ddi_dma_handle_t dmab_dma_handle; /* DMA handle */
391 size_t dmab_size; /* Buffer size */
392 size_t dmab_len; /* Data length in the buffer */
393 } i40e_dma_buffer_t;
394
395 /*
396 * RX Control Block
397 */
398 typedef struct i40e_rx_control_block {
399 mblk_t *rcb_mp;
400 uint32_t rcb_ref;
401 i40e_dma_buffer_t rcb_dma;
402 frtn_t rcb_free_rtn;
403 struct i40e_rx_data *rcb_rxd;
404 } i40e_rx_control_block_t;
405
406 typedef enum {
407 I40E_TX_NONE,
408 I40E_TX_COPY,
409 I40E_TX_DMA,
410 I40E_TX_DESC,
411 } i40e_tx_type_t;
412
413 typedef struct i40e_tx_desc i40e_tx_desc_t;
414 typedef struct i40e_tx_context_desc i40e_tx_context_desc_t;
415 typedef union i40e_32byte_rx_desc i40e_rx_desc_t;
416
417 struct i40e_dma_bind_info {
418 caddr_t dbi_paddr;
419 size_t dbi_len;
420 };
421
422 typedef struct i40e_tx_control_block {
423 struct i40e_tx_control_block *tcb_next;
424 mblk_t *tcb_mp;
425 i40e_tx_type_t tcb_type;
426 ddi_dma_handle_t tcb_dma_handle;
427 ddi_dma_handle_t tcb_lso_dma_handle;
428 i40e_dma_buffer_t tcb_dma;
429 struct i40e_dma_bind_info *tcb_bind_info;
430 uint_t tcb_bind_ncookies;
431 boolean_t tcb_used_lso;
432 } i40e_tx_control_block_t;
433
434 /*
435 * Receive ring data (used below).
436 */
437 typedef struct i40e_rx_data {
438 struct i40e *rxd_i40e;
439
440 /*
441 * RX descriptor ring definitions
442 */
443 i40e_dma_buffer_t rxd_desc_area; /* DMA buffer of rx desc ring */
444 i40e_rx_desc_t *rxd_desc_ring; /* Rx desc ring */
445 uint32_t rxd_desc_next; /* Index of next rx desc */
446
447 /*
448 * RX control block list definitions
449 */
450 kmutex_t rxd_free_lock; /* Lock to protect free data */
451 i40e_rx_control_block_t *rxd_rcb_area; /* Array of control blocks */
512 kstat_named_t irxs_hck_v4hdrok; /* Valid IPv4 Header */
513 kstat_named_t irxs_hck_l4hdrok; /* Valid L4 Header */
514 kstat_named_t irxs_hck_unknown; /* !pinfo.known */
515 kstat_named_t irxs_hck_nol3l4p; /* Missing L3L4P bit in desc */
516 kstat_named_t irxs_hck_iperr; /* IPE error bit set */
517 kstat_named_t irxs_hck_eiperr; /* EIPE error bit set */
518 kstat_named_t irxs_hck_l4err; /* L4E error bit set */
519 kstat_named_t irxs_hck_v6skip; /* IPv6 case hw fails on */
520 kstat_named_t irxs_hck_set; /* Total times we set cksum */
521 kstat_named_t irxs_hck_miss; /* Times with zero cksum bits */
522 } i40e_rxq_stat_t;
523
524 /*
525 * Collection of TX Statistics on a given queue
526 */
527 typedef struct i40e_txq_stat {
528 kstat_named_t itxs_bytes; /* Bytes out on queue */
529 kstat_named_t itxs_packets; /* Packets out on queue */
530 kstat_named_t itxs_descriptors; /* Descriptors issued */
531 kstat_named_t itxs_recycled; /* Descriptors reclaimed */
532 kstat_named_t itxs_force_copy; /* non-TSO force copy */
533 kstat_named_t itxs_tso_force_copy; /* TSO force copy */
534 /*
535 * Various failure conditions.
536 */
537 kstat_named_t itxs_hck_meoifail; /* ether offload failures */
538 kstat_named_t itxs_hck_nol2info; /* Missing l2 info */
539 kstat_named_t itxs_hck_nol3info; /* Missing l3 info */
540 kstat_named_t itxs_hck_nol4info; /* Missing l4 info */
541 kstat_named_t itxs_hck_badl3; /* Not IPv4/IPv6 */
542 kstat_named_t itxs_hck_badl4; /* Bad L4 Paylaod */
543 kstat_named_t itxs_lso_nohck; /* Missing offloads for LSO */
544 kstat_named_t itxs_bind_fails; /* DMA bind failures */
545
546 kstat_named_t itxs_err_notcb; /* No tcb's available */
547 kstat_named_t itxs_err_nodescs; /* No tcb's available */
548 kstat_named_t itxs_err_context; /* Total context failures */
549
550 kstat_named_t itxs_num_unblocked; /* Number of MAC unblocks */
551 } i40e_txq_stat_t;
552
553 /*
554 * An instance of an XL710 transmit/receive queue pair. This currently
555 * represents a combination of both a transmit and receive ring, though they
556 * should really be split apart into separate logical structures. Unfortunately,
557 * during initial work we mistakenly joined them together.
558 */
559 typedef struct i40e_trqpair {
560 struct i40e *itrq_i40e;
561
562 /* Receive-side structures. */
563 kmutex_t itrq_rx_lock;
564 mac_ring_handle_t itrq_macrxring; /* Receive ring handle. */
760 kstat_named_t ipk_rx_err1; /* rxerr1 */
761 kstat_named_t ipk_rx_err2; /* rxerr2 */
762 } i40e_pf_kstats_t;
763
764 /*
765 * Resources that are pooled and specific to a given i40e_t.
766 */
767 typedef struct i40e_func_rsrc {
768 uint_t ifr_nrx_queue;
769 uint_t ifr_nrx_queue_used;
770 uint_t ifr_ntx_queue;
771 uint_t ifr_trx_queue_used;
772 uint_t ifr_nvsis;
773 uint_t ifr_nvsis_used;
774 uint_t ifr_nmacfilt;
775 uint_t ifr_nmacfilt_used;
776 uint_t ifr_nmcastfilt;
777 uint_t ifr_nmcastfilt_used;
778 } i40e_func_rsrc_t;
779
780 typedef struct i40e_vsi {
781 uint16_t iv_seid;
782 uint16_t iv_number;
783 kstat_t *iv_kstats;
784 i40e_vsi_stats_t iv_stats;
785 uint16_t iv_stats_id;
786 } i40e_vsi_t;
787
788 /*
789 * While irg_index and irg_grp_hdl aren't used anywhere, they are
790 * still useful for debugging.
791 */
792 typedef struct i40e_rx_group {
793 uint32_t irg_index; /* index in i40e_rx_groups[] */
794 uint16_t irg_vsi_seid; /* SEID of VSI for this group */
795 mac_group_handle_t irg_grp_hdl; /* handle to mac_group_t */
796 struct i40e *irg_i40e; /* ref to i40e_t */
797 } i40e_rx_group_t;
798
799 /*
800 * Main i40e per-instance state.
801 */
802 typedef struct i40e {
803 list_node_t i40e_glink; /* Global list link */
804 list_node_t i40e_dlink; /* Device list link */
805 kmutex_t i40e_general_lock; /* General device lock */
806
807 /*
808 * General Data and management
809 */
810 dev_info_t *i40e_dip;
811 int i40e_instance;
812 int i40e_fm_capabilities;
813 uint_t i40e_state;
814 i40e_attach_state_t i40e_attach_progress;
815 mac_handle_t i40e_mac_hdl;
816 ddi_periodic_t i40e_periodic_id;
817
818 /*
819 * Pointers to common code data structures and memory for the common
820 * code.
821 */
822 struct i40e_hw i40e_hw_space;
823 struct i40e_osdep i40e_osdep_space;
824 struct i40e_aq_get_phy_abilities_resp i40e_phy;
825 void *i40e_aqbuf;
826
827 #define I40E_DEF_VSI_IDX 0
828 #define I40E_DEF_VSI(i40e) ((i40e)->i40e_vsis[I40E_DEF_VSI_IDX])
829 #define I40E_DEF_VSI_SEID(i40e) (I40E_DEF_VSI(i40e).iv_seid)
830
831 /*
832 * Device state, switch information, and resources.
833 */
834 i40e_vsi_t i40e_vsis[I40E_GROUP_MAX];
835 uint16_t i40e_mac_seid; /* SEID of physical MAC */
836 uint16_t i40e_veb_seid; /* switch atop MAC (SEID) */
837 uint16_t i40e_vsi_avail; /* VSIs avail to this PF */
838 uint16_t i40e_vsi_used; /* VSIs used by this PF */
839 struct i40e_device *i40e_device;
840 i40e_func_rsrc_t i40e_resources;
841 uint16_t i40e_switch_rsrc_alloc;
842 uint16_t i40e_switch_rsrc_actual;
843 i40e_switch_rsrc_t *i40e_switch_rsrcs;
844 i40e_uaddr_t *i40e_uaddrs;
845 i40e_maddr_t *i40e_maddrs;
846 int i40e_mcast_promisc_count;
847 boolean_t i40e_promisc_on;
848 link_state_t i40e_link_state;
849 uint32_t i40e_link_speed; /* In Mbps */
850 link_duplex_t i40e_link_duplex;
851 uint_t i40e_sdu;
852 uint_t i40e_frame_max;
853
854 /*
855 * Transmit and receive information, tunables, and MAC info.
856 */
857 i40e_trqpair_t *i40e_trqpairs;
858 boolean_t i40e_mr_enable;
859 uint_t i40e_num_trqpairs; /* total TRQPs (per PF) */
860 uint_t i40e_num_trqpairs_per_vsi; /* TRQPs per VSI */
861 uint_t i40e_other_itr;
862
863 i40e_rx_group_t *i40e_rx_groups;
864 uint_t i40e_num_rx_groups;
865 int i40e_num_rx_descs;
866 uint32_t i40e_rx_ring_size;
867 uint32_t i40e_rx_buf_size;
868 boolean_t i40e_rx_hcksum_enable;
869 uint32_t i40e_rx_dma_min;
870 uint32_t i40e_rx_limit_per_intr;
871 uint_t i40e_rx_itr;
872
873 int i40e_num_tx_descs;
874 uint32_t i40e_tx_ring_size;
875 uint32_t i40e_tx_buf_size;
876 uint32_t i40e_tx_block_thresh;
877 boolean_t i40e_tx_hcksum_enable;
878 boolean_t i40e_tx_lso_enable;
879 uint32_t i40e_tx_dma_min;
880 uint_t i40e_tx_itr;
881
882 /*
883 * Interrupt state
884 */
885 uint_t i40e_intr_pri;
886 uint_t i40e_intr_force;
887 uint_t i40e_intr_type;
888 int i40e_intr_cap;
889 uint32_t i40e_intr_count;
890 uint32_t i40e_intr_count_max;
891 uint32_t i40e_intr_count_min;
892 size_t i40e_intr_size;
893 ddi_intr_handle_t *i40e_intr_handles;
894 ddi_cb_handle_t i40e_callback_handle;
895
896 /*
897 * DMA attributes. See i40e_transceiver.c for why we have copies of them
898 * in the i40e_t.
899 */
900 ddi_dma_attr_t i40e_static_dma_attr;
901 ddi_dma_attr_t i40e_txbind_dma_attr;
902 ddi_dma_attr_t i40e_txbind_lso_dma_attr;
903 ddi_device_acc_attr_t i40e_desc_acc_attr;
904 ddi_device_acc_attr_t i40e_buf_acc_attr;
905
906 /*
907 * The following two fields are used to protect and keep track of
908 * outstanding, loaned buffers to MAC. If we have these, we can't
909 * detach as we have active DMA memory outstanding.
910 */
911 kmutex_t i40e_rx_pending_lock;
912 kcondvar_t i40e_rx_pending_cv;
913 uint32_t i40e_rx_pending;
914
915 /*
916 * PF statistics and VSI statistics.
917 */
918 kmutex_t i40e_stat_lock;
919 kstat_t *i40e_pf_kstat;
920 i40e_pf_stats_t i40e_pf_stat;
921
922 /*
923 * Misc. stats and counters that should maybe one day be kstats.
924 */
925 uint64_t i40e_s_link_status_errs;
926 uint32_t i40e_s_link_status_lasterr;
927
928 /*
929 * LED information. Note this state is only modified in
930 * i40e_gld_set_led() which is protected by MAC's serializer lock.
931 */
932 uint32_t i40e_led_status;
933 boolean_t i40e_led_saved;
934 } i40e_t;
935
936 /*
937 * The i40e_device represents a PCI device which encapsulates multiple physical
938 * functions which are represented as an i40e_t. This is used to track the use
939 * of pooled resources throughout all of the various devices.
940 */
1000
1001 /*
1002 * Receive-side functions
1003 */
1004 extern mblk_t *i40e_ring_rx(i40e_trqpair_t *, int);
1005 extern mblk_t *i40e_ring_rx_poll(void *, int);
1006 extern void i40e_rx_recycle(caddr_t);
1007
1008 /*
1009 * Transmit-side functions
1010 */
1011 mblk_t *i40e_ring_tx(void *, mblk_t *);
1012 extern void i40e_tx_recycle_ring(i40e_trqpair_t *);
1013 extern void i40e_tx_cleanup_ring(i40e_trqpair_t *);
1014
1015 /*
1016 * Statistics functions.
1017 */
1018 extern boolean_t i40e_stats_init(i40e_t *);
1019 extern void i40e_stats_fini(i40e_t *);
1020 extern boolean_t i40e_stat_vsi_init(i40e_t *, uint_t);
1021 extern void i40e_stat_vsi_fini(i40e_t *, uint_t);
1022 extern boolean_t i40e_stats_trqpair_init(i40e_trqpair_t *);
1023 extern void i40e_stats_trqpair_fini(i40e_trqpair_t *);
1024 extern int i40e_m_stat(void *, uint_t, uint64_t *);
1025 extern int i40e_rx_ring_stat(mac_ring_driver_t, uint_t, uint64_t *);
1026 extern int i40e_tx_ring_stat(mac_ring_driver_t, uint_t, uint64_t *);
1027
1028 /*
1029 * MAC/GLDv3 functions, and functions called by MAC/GLDv3 support code.
1030 */
1031 extern boolean_t i40e_register_mac(i40e_t *);
1032 extern boolean_t i40e_start(i40e_t *, boolean_t);
1033 extern void i40e_stop(i40e_t *, boolean_t);
1034
1035 /*
1036 * DMA & buffer functions and attributes
1037 */
1038 extern void i40e_init_dma_attrs(i40e_t *, boolean_t);
1039 extern boolean_t i40e_alloc_ring_mem(i40e_t *);
1040 extern void i40e_free_ring_mem(i40e_t *, boolean_t);
1041
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