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NEX-5717 import QLogic 16G FC drivers
Reviewed by: Steve Peng <steve.peng@nexenta.com>
Reviewed by: Josef 'Jeff' Sipek <josef.sipek@nexenta.com>
Reviewed by: Yuri Pankov <yuri.pankov@nexenta.com>
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--- old/usr/src/uts/common/io/fibre-channel/fca/qlc/ql_init.c
+++ new/usr/src/uts/common/io/fibre-channel/fca/qlc/ql_init.c
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
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12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21
22 -/* Copyright 2010 QLogic Corporation */
22 +/* Copyright 2015 QLogic Corporation */
23 23
24 24 /*
25 - * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved.
25 + * Copyright (c) 2008, 2011, Oracle and/or its affiliates. All rights reserved.
26 26 */
27 27
28 -#pragma ident "Copyright 2010 QLogic Corporation; ql_init.c"
28 +#pragma ident "Copyright 2015 QLogic Corporation; ql_init.c"
29 29
30 30 /*
31 31 * ISP2xxx Solaris Fibre Channel Adapter (FCA) driver source file.
32 32 *
33 33 * ***********************************************************************
34 34 * * **
35 35 * * NOTICE **
36 - * * COPYRIGHT (C) 1996-2010 QLOGIC CORPORATION **
36 + * * COPYRIGHT (C) 1996-2015 QLOGIC CORPORATION **
37 37 * * ALL RIGHTS RESERVED **
38 38 * * **
39 39 * ***********************************************************************
40 40 *
41 41 */
42 42
43 43 #include <ql_apps.h>
44 44 #include <ql_api.h>
45 45 #include <ql_debug.h>
46 46 #include <ql_init.h>
47 47 #include <ql_iocb.h>
48 48 #include <ql_isr.h>
49 49 #include <ql_mbx.h>
50 50 #include <ql_nx.h>
51 51 #include <ql_xioctl.h>
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52 52
53 53 /*
54 54 * Local data
55 55 */
56 56
57 57 /*
58 58 * Local prototypes
59 59 */
60 60 static uint16_t ql_nvram_request(ql_adapter_state_t *, uint32_t);
61 61 static int ql_nvram_24xx_config(ql_adapter_state_t *);
62 -static void ql_23_properties(ql_adapter_state_t *, nvram_t *);
63 -static void ql_24xx_properties(ql_adapter_state_t *, nvram_24xx_t *);
62 +static void ql_23_properties(ql_adapter_state_t *, ql_init_cb_t *);
63 +static void ql_24xx_properties(ql_adapter_state_t *, ql_init_24xx_cb_t *);
64 64 static int ql_check_isp_firmware(ql_adapter_state_t *);
65 -static int ql_chip_diag(ql_adapter_state_t *);
66 65 static int ql_load_flash_fw(ql_adapter_state_t *);
67 66 static int ql_configure_loop(ql_adapter_state_t *);
68 67 static int ql_configure_hba(ql_adapter_state_t *);
69 68 static int ql_configure_fabric(ql_adapter_state_t *);
70 69 static int ql_configure_device_d_id(ql_adapter_state_t *);
70 +static void ql_update_dev(ql_adapter_state_t *, uint32_t);
71 71 static void ql_set_max_read_req(ql_adapter_state_t *);
72 72 static void ql_configure_n_port_info(ql_adapter_state_t *);
73 -static void ql_clear_mcp(ql_adapter_state_t *);
73 +static void ql_reset_24xx_chip(ql_adapter_state_t *);
74 74 static void ql_mps_reset(ql_adapter_state_t *);
75 75
76 76 /*
77 77 * ql_initialize_adapter
78 78 * Initialize board.
79 79 *
80 80 * Input:
81 81 * ha = adapter state pointer.
82 82 *
83 83 * Returns:
84 84 * ql local function return status code.
85 85 *
86 86 * Context:
87 87 * Kernel context.
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88 88 */
89 89 int
90 90 ql_initialize_adapter(ql_adapter_state_t *ha)
91 91 {
92 92 int rval;
93 93 class_svc_param_t *class3_param;
94 94 caddr_t msg;
95 95 la_els_logi_t *els = &ha->loginparams;
96 96 int retries = 5;
97 97
98 - QL_PRINT_3(CE_CONT, "(%d): started\n", ha->instance);
98 + QL_PRINT_10(ha, "started cfg=0x%llx\n", ha->cfg_flags);
99 99
100 100 do {
101 101 /* Clear adapter flags. */
102 102 TASK_DAEMON_LOCK(ha);
103 103 ha->task_daemon_flags &= TASK_DAEMON_STOP_FLG |
104 104 TASK_DAEMON_SLEEPING_FLG | TASK_DAEMON_ALIVE_FLG |
105 105 TASK_DAEMON_IDLE_CHK_FLG;
106 106 ha->task_daemon_flags |= LOOP_DOWN;
107 107 TASK_DAEMON_UNLOCK(ha);
108 108
109 109 ha->loop_down_timer = LOOP_DOWN_TIMER_OFF;
110 110 ADAPTER_STATE_LOCK(ha);
111 111 ha->flags |= ABORT_CMDS_LOOP_DOWN_TMO;
112 112 ha->flags &= ~ONLINE;
113 113 ADAPTER_STATE_UNLOCK(ha);
114 114
115 115 ha->state = FC_STATE_OFFLINE;
116 116 msg = "Loop OFFLINE";
117 117
118 118 rval = ql_pci_sbus_config(ha);
119 119 if (rval != QL_SUCCESS) {
120 120 TASK_DAEMON_LOCK(ha);
121 121 if (!(ha->task_daemon_flags & ABORT_ISP_ACTIVE)) {
122 122 EL(ha, "ql_pci_sbus_cfg, isp_abort_needed\n");
123 123 ha->task_daemon_flags |= ISP_ABORT_NEEDED;
124 124 }
125 125 TASK_DAEMON_UNLOCK(ha);
126 126 continue;
127 127 }
128 128
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129 129 (void) ql_setup_fcache(ha);
130 130
131 131 /* Reset ISP chip. */
132 132 ql_reset_chip(ha);
133 133
134 134 /* Get NVRAM configuration if needed. */
135 135 if (ha->init_ctrl_blk.cb.version == 0) {
136 136 (void) ql_nvram_config(ha);
137 137 }
138 138
139 - /* Set login parameters. */
140 - if (CFG_IST(ha, CFG_CTRL_24258081)) {
141 - els->common_service.rx_bufsize = CHAR_TO_SHORT(
142 - ha->init_ctrl_blk.cb24.max_frame_length[0],
143 - ha->init_ctrl_blk.cb24.max_frame_length[1]);
144 - bcopy((void *)&ha->init_ctrl_blk.cb24.port_name[0],
145 - (void *)&els->nport_ww_name.raw_wwn[0], 8);
146 - bcopy((void *)&ha->init_ctrl_blk.cb24.node_name[0],
147 - (void *)&els->node_ww_name.raw_wwn[0], 8);
148 - } else {
149 - els->common_service.rx_bufsize = CHAR_TO_SHORT(
150 - ha->init_ctrl_blk.cb.max_frame_length[0],
151 - ha->init_ctrl_blk.cb.max_frame_length[1]);
152 - bcopy((void *)&ha->init_ctrl_blk.cb.port_name[0],
153 - (void *)&els->nport_ww_name.raw_wwn[0], 8);
154 - bcopy((void *)&ha->init_ctrl_blk.cb.node_name[0],
155 - (void *)&els->node_ww_name.raw_wwn[0], 8);
156 - }
157 - bcopy(QL_VERSION, ha->adapter_stats->revlvl.qlddv,
158 - strlen(QL_VERSION));
159 -
160 139 /* Determine which RISC code to use. */
161 140 if ((rval = ql_check_isp_firmware(ha)) != QL_SUCCESS) {
162 - if ((rval = ql_chip_diag(ha)) == QL_SUCCESS) {
141 + if (ha->dev_state != NX_DEV_READY) {
142 + EL(ha, "dev_state not ready, isp_abort_needed_2"
143 + "\n");
144 + TASK_DAEMON_LOCK(ha);
145 + ha->task_daemon_flags |= ISP_ABORT_NEEDED;
146 + TASK_DAEMON_UNLOCK(ha);
147 + break;
148 + }
149 + if ((rval = ql_mbx_wrap_test(ha, NULL)) == QL_SUCCESS) {
163 150 rval = ql_load_isp_firmware(ha);
164 151 }
165 152 }
166 153
167 154 if (rval == QL_SUCCESS && (rval = ql_set_cache_line(ha)) ==
168 155 QL_SUCCESS && (rval = ql_init_rings(ha)) == QL_SUCCESS) {
169 156
157 + ql_enable_intr(ha);
170 158 (void) ql_fw_ready(ha, ha->fwwait);
171 159
172 - if (!(ha->task_daemon_flags & QL_SUSPENDED) &&
160 + if (!DRIVER_SUSPENDED(ha) &&
173 161 ha->loop_down_timer == LOOP_DOWN_TIMER_OFF) {
174 162 if (ha->topology & QL_LOOP_CONNECTION) {
175 163 ha->state = ha->state | FC_STATE_LOOP;
176 164 msg = "Loop ONLINE";
165 + TASK_DAEMON_LOCK(ha);
177 166 ha->task_daemon_flags |= STATE_ONLINE;
167 + TASK_DAEMON_UNLOCK(ha);
178 168 } else if (ha->topology & QL_P2P_CONNECTION) {
179 169 ha->state = ha->state |
180 170 FC_STATE_ONLINE;
181 171 msg = "Link ONLINE";
172 + TASK_DAEMON_LOCK(ha);
182 173 ha->task_daemon_flags |= STATE_ONLINE;
174 + TASK_DAEMON_UNLOCK(ha);
183 175 } else {
184 176 msg = "Unknown Link state";
185 177 }
186 178 }
187 179 } else {
188 180 TASK_DAEMON_LOCK(ha);
189 181 if (!(ha->task_daemon_flags & ABORT_ISP_ACTIVE)) {
190 182 EL(ha, "failed, isp_abort_needed\n");
191 183 ha->task_daemon_flags |= ISP_ABORT_NEEDED |
192 184 LOOP_DOWN;
193 185 }
194 186 TASK_DAEMON_UNLOCK(ha);
195 187 }
196 188
197 189 } while (retries-- != 0 && ha->task_daemon_flags & ISP_ABORT_NEEDED);
198 190
199 191 cmn_err(CE_NOTE, "!Qlogic %s(%d): %s", QL_NAME, ha->instance, msg);
200 192
201 - /* Enable ISP interrupts and login parameters. */
202 - if (CFG_IST(ha, CFG_CTRL_8021)) {
203 - ql_8021_enable_intrs(ha);
204 - } else if (CFG_IST(ha, CFG_CTRL_242581)) {
205 - WRT32_IO_REG(ha, ictrl, ISP_EN_RISC);
206 - } else {
207 - WRT16_IO_REG(ha, ictrl, ISP_EN_INT + ISP_EN_RISC);
193 + /* Enable ISP interrupts if not already enabled. */
194 + if (!(ha->flags & INTERRUPTS_ENABLED)) {
195 + ql_enable_intr(ha);
208 196 }
209 197
210 198 ADAPTER_STATE_LOCK(ha);
211 - ha->flags |= (INTERRUPTS_ENABLED | ONLINE);
199 + ha->flags |= ONLINE;
212 200 ADAPTER_STATE_UNLOCK(ha);
213 201
214 - ha->task_daemon_flags &= ~(FC_STATE_CHANGE | RESET_MARKER_NEEDED |
202 + /*
203 + * Set flash write-protection.
204 + */
205 + if (CFG_IST(ha, CFG_ISP_FW_TYPE_2) &&
206 + ha->dev_state == NX_DEV_READY) {
207 + ql_24xx_protect_flash(ha);
208 + }
209 +
210 + TASK_DAEMON_LOCK(ha);
211 + ha->task_daemon_flags &= ~(FC_STATE_CHANGE | MARKER_NEEDED |
215 212 COMMAND_WAIT_NEEDED);
213 + TASK_DAEMON_UNLOCK(ha);
216 214
217 215 /*
218 216 * Setup login parameters.
219 217 */
218 + bcopy(QL_VERSION, ha->adapter_stats->revlvl.qlddv, strlen(QL_VERSION));
219 +
220 220 els->common_service.fcph_version = 0x2006;
221 221 els->common_service.btob_credit = 3;
222 - els->common_service.cmn_features = 0x8800;
222 + els->common_service.cmn_features =
223 + ha->topology & QL_N_PORT ? 0x8000 : 0x8800;
223 224 els->common_service.conc_sequences = 0xff;
224 225 els->common_service.relative_offset = 3;
225 226 els->common_service.e_d_tov = 0x07d0;
226 227
227 228 class3_param = (class_svc_param_t *)&els->class_3;
228 229 class3_param->class_valid_svc_opt = 0x8800;
229 230 class3_param->rcv_data_size = els->common_service.rx_bufsize;
230 231 class3_param->conc_sequences = 0xff;
232 + class3_param->open_sequences_per_exch = 1;
231 233
232 234 if (rval != QL_SUCCESS) {
233 235 EL(ha, "failed, rval = %xh\n", rval);
234 236 } else {
235 237 /*EMPTY*/
236 - QL_PRINT_3(CE_CONT, "(%d): done\n", ha->instance);
238 + QL_PRINT_10(ha, "done\n");
237 239 }
238 240 return (rval);
239 241 }
240 242
241 243 /*
242 244 * ql_pci_sbus_config
243 245 * Setup device PCI/SBUS configuration registers.
244 246 *
245 247 * Input:
246 248 * ha = adapter state pointer.
247 249 *
248 250 * Returns:
249 251 * ql local function return status code.
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250 252 *
251 253 * Context:
252 254 * Kernel context.
253 255 */
254 256 int
255 257 ql_pci_sbus_config(ql_adapter_state_t *ha)
256 258 {
257 259 uint32_t timer;
258 260 uint16_t cmd, w16;
259 261
260 - QL_PRINT_3(CE_CONT, "(%d): started\n", ha->instance);
262 + QL_PRINT_10(ha, "started\n");
261 263
262 264 if (CFG_IST(ha, CFG_SBUS_CARD)) {
263 265 w16 = (uint16_t)ddi_get16(ha->sbus_fpga_dev_handle,
264 266 (uint16_t *)(ha->sbus_fpga_iobase + FPGA_REVISION));
265 267 EL(ha, "FPGA rev is %d.%d", (w16 & 0xf0) >> 4,
266 268 w16 & 0xf);
267 269 } else {
268 270 /*
269 271 * we want to respect framework's setting of PCI
270 272 * configuration space command register and also
271 273 * want to make sure that all bits of interest to us
272 274 * are properly set in command register.
273 275 */
274 276 cmd = (uint16_t)ql_pci_config_get16(ha, PCI_CONF_COMM);
275 277 cmd = (uint16_t)(cmd | PCI_COMM_IO | PCI_COMM_MAE |
276 - PCI_COMM_ME | PCI_COMM_MEMWR_INVAL |
277 - PCI_COMM_PARITY_DETECT | PCI_COMM_SERR_ENABLE);
278 + PCI_COMM_ME | PCI_COMM_PARITY_DETECT |
279 + PCI_COMM_SERR_ENABLE);
280 + if (ql_get_cap_ofst(ha, PCI_CAP_ID_PCIX)) {
281 + cmd = (uint16_t)(cmd | PCI_COMM_MEMWR_INVAL);
282 + }
278 283
279 284 /*
280 285 * If this is a 2300 card and not 2312, reset the
281 286 * MEMWR_INVAL due to a bug in the 2300. Unfortunately, the
282 287 * 2310 also reports itself as a 2300 so we need to get the
283 288 * fb revision level -- a 6 indicates it really is a 2300 and
284 289 * not a 2310.
285 290 */
286 291
287 292 if (ha->device_id == 0x2300) {
288 293 /* Pause RISC. */
289 294 WRT16_IO_REG(ha, hccr, HC_PAUSE_RISC);
290 295 for (timer = 0; timer < 30000; timer++) {
291 296 if ((RD16_IO_REG(ha, hccr) & HC_RISC_PAUSE) !=
292 297 0) {
293 298 break;
294 299 } else {
295 300 drv_usecwait(MILLISEC);
296 301 }
297 302 }
298 303
299 304 /* Select FPM registers. */
300 305 WRT16_IO_REG(ha, ctrl_status, 0x20);
301 306
302 307 /* Get the fb rev level */
303 308 if (RD16_IO_REG(ha, fb_cmd) == 6) {
304 309 cmd = (uint16_t)(cmd & ~PCI_COMM_MEMWR_INVAL);
305 310 }
306 311
307 312 /* Deselect FPM registers. */
308 313 WRT16_IO_REG(ha, ctrl_status, 0x0);
309 314
310 315 /* Release RISC module. */
311 316 WRT16_IO_REG(ha, hccr, HC_RELEASE_RISC);
312 317 for (timer = 0; timer < 30000; timer++) {
313 318 if ((RD16_IO_REG(ha, hccr) & HC_RISC_PAUSE) ==
314 319 0) {
315 320 break;
316 321 } else {
317 322 drv_usecwait(MILLISEC);
318 323 }
319 324 }
320 325 } else if (ha->device_id == 0x2312) {
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321 326 /*
322 327 * cPCI ISP2312 specific code to service function 1
323 328 * hot-swap registers.
324 329 */
325 330 if ((RD16_IO_REG(ha, ctrl_status) & ISP_FUNC_NUM_MASK)
326 331 != 0) {
327 332 ql_pci_config_put8(ha, 0x66, 0xc2);
328 333 }
329 334 }
330 335
331 - if (!(CFG_IST(ha, CFG_CTRL_8021)) &&
336 + if (!(CFG_IST(ha, CFG_CTRL_82XX)) &&
332 337 ha->pci_max_read_req != 0) {
333 338 ql_set_max_read_req(ha);
334 339 }
335 340
336 341 ql_pci_config_put16(ha, PCI_CONF_COMM, cmd);
337 342
338 343 /* Set cache line register. */
339 344 ql_pci_config_put8(ha, PCI_CONF_CACHE_LINESZ, 0x10);
340 345
341 346 /* Set latency register. */
342 347 ql_pci_config_put8(ha, PCI_CONF_LATENCY_TIMER, 0x40);
343 348
344 349 /* Reset expansion ROM address decode enable. */
345 - w16 = (uint16_t)ql_pci_config_get16(ha, PCI_CONF_ROM);
346 - w16 = (uint16_t)(w16 & ~BIT_0);
347 - ql_pci_config_put16(ha, PCI_CONF_ROM, w16);
350 + if (!CFG_IST(ha, CFG_CTRL_278083)) {
351 + w16 = (uint16_t)ql_pci_config_get16(ha, PCI_CONF_ROM);
352 + w16 = (uint16_t)(w16 & ~BIT_0);
353 + ql_pci_config_put16(ha, PCI_CONF_ROM, w16);
354 + }
348 355 }
349 356
350 - QL_PRINT_3(CE_CONT, "(%d): done\n", ha->instance);
357 + QL_PRINT_10(ha, "done\n");
351 358
352 359 return (QL_SUCCESS);
353 360 }
354 361
355 362 /*
356 363 * Set the PCI max read request value.
357 364 *
358 365 * Input:
359 366 * ha: adapter state pointer.
360 367 *
361 368 * Output:
362 369 * none.
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363 370 *
364 371 * Returns:
365 372 *
366 373 * Context:
367 374 * Kernel context.
368 375 */
369 376
370 377 static void
371 378 ql_set_max_read_req(ql_adapter_state_t *ha)
372 379 {
380 + int ofst;
373 381 uint16_t read_req, w16;
374 382 uint16_t tmp = ha->pci_max_read_req;
375 383
376 - if ((ha->device_id == 0x2422) ||
377 - ((ha->device_id & 0xff00) == 0x2300)) {
384 + QL_PRINT_3(ha, "started\n");
385 +
386 + if ((ofst = ql_get_cap_ofst(ha, PCI_CAP_ID_PCIX))) {
387 + ofst += PCI_PCIX_COMMAND;
388 + QL_PRINT_10(ha, "PCI-X Command Reg = %xh\n", ofst);
378 389 /* check for vaild override value */
379 390 if (tmp == 512 || tmp == 1024 || tmp == 2048 ||
380 391 tmp == 4096) {
381 392 /* shift away the don't cares */
382 393 tmp = (uint16_t)(tmp >> 10);
383 394 /* convert bit pos to request value */
384 395 for (read_req = 0; tmp != 0; read_req++) {
385 396 tmp = (uint16_t)(tmp >> 1);
386 397 }
387 - w16 = (uint16_t)ql_pci_config_get16(ha, 0x4e);
398 + w16 = (uint16_t)ql_pci_config_get16(ha, ofst);
388 399 w16 = (uint16_t)(w16 & ~(BIT_3 & BIT_2));
389 400 w16 = (uint16_t)(w16 | (read_req << 2));
390 - ql_pci_config_put16(ha, 0x4e, w16);
401 + ql_pci_config_put16(ha, ofst, w16);
391 402 } else {
392 403 EL(ha, "invalid parameter value for "
393 404 "'pci-max-read-request': %d; using system "
394 405 "default\n", tmp);
395 406 }
396 - } else if ((ha->device_id == 0x2432) || ((ha->device_id & 0xff00) ==
397 - 0x2500) || (ha->device_id == 0x8432)) {
398 - /* check for vaild override value */
407 + } else if ((ofst = ql_get_cap_ofst(ha, PCI_CAP_ID_PCI_E))) {
408 + ofst += PCI_PCIE_DEVICE_CONTROL;
409 + QL_PRINT_10(ha, "PCI-E Device Control Reg = %xh\n", ofst);
399 410 if (tmp == 128 || tmp == 256 || tmp == 512 ||
400 411 tmp == 1024 || tmp == 2048 || tmp == 4096) {
401 412 /* shift away the don't cares */
402 413 tmp = (uint16_t)(tmp >> 8);
403 414 /* convert bit pos to request value */
404 415 for (read_req = 0; tmp != 0; read_req++) {
405 416 tmp = (uint16_t)(tmp >> 1);
406 417 }
407 - w16 = (uint16_t)ql_pci_config_get16(ha, 0x54);
418 + w16 = (uint16_t)ql_pci_config_get16(ha, ofst);
408 419 w16 = (uint16_t)(w16 & ~(BIT_14 | BIT_13 |
409 420 BIT_12));
410 421 w16 = (uint16_t)(w16 | (read_req << 12));
411 - ql_pci_config_put16(ha, 0x54, w16);
422 + ql_pci_config_put16(ha, ofst, w16);
412 423 } else {
413 424 EL(ha, "invalid parameter value for "
414 425 "'pci-max-read-request': %d; using system "
415 426 "default\n", tmp);
416 427 }
417 428 }
429 + QL_PRINT_3(ha, "done\n");
418 430 }
419 431
420 432 /*
421 433 * NVRAM configuration.
422 434 *
423 435 * Input:
424 436 * ha: adapter state pointer.
425 - * ha->hba_buf = request and response rings
437 + * ha->req_q[0]: request ring
426 438 *
427 439 * Output:
428 440 * ha->init_ctrl_blk = initialization control block
429 441 * host adapters parameters in host adapter block
430 442 *
431 443 * Returns:
432 444 * ql local function return status code.
433 445 *
434 446 * Context:
435 447 * Kernel context.
436 448 */
437 449 int
438 450 ql_nvram_config(ql_adapter_state_t *ha)
439 451 {
440 452 uint32_t cnt;
441 453 caddr_t dptr1, dptr2;
442 454 ql_init_cb_t *icb = &ha->init_ctrl_blk.cb;
443 455 ql_ip_init_cb_t *ip_icb = &ha->ip_init_ctrl_blk.cb;
444 - nvram_t *nv = (nvram_t *)ha->request_ring_bp;
445 - uint16_t *wptr = (uint16_t *)ha->request_ring_bp;
456 + nvram_t *nv = (nvram_t *)ha->req_q[0]->req_ring.bp;
457 + uint16_t *wptr = (uint16_t *)ha->req_q[0]->req_ring.bp;
446 458 uint8_t chksum = 0;
447 459 int rval;
448 460 int idpromlen;
449 461 char idprombuf[32];
450 462 uint32_t start_addr;
463 + la_els_logi_t *els = &ha->loginparams;
451 464
452 - QL_PRINT_3(CE_CONT, "(%d): started\n", ha->instance);
465 + QL_PRINT_10(ha, "started\n");
453 466
454 - if (CFG_IST(ha, CFG_CTRL_24258081)) {
467 + if (CFG_IST(ha, CFG_ISP_FW_TYPE_2)) {
455 468 return (ql_nvram_24xx_config(ha));
456 469 }
457 470
458 471 start_addr = 0;
459 472 if ((rval = ql_lock_nvram(ha, &start_addr, LNF_NVRAM_DATA)) ==
460 473 QL_SUCCESS) {
461 474 /* Verify valid NVRAM checksum. */
462 - for (cnt = 0; cnt < sizeof (nvram_t)/2; cnt++) {
475 + for (cnt = 0; cnt < sizeof (nvram_t) / 2; cnt++) {
463 476 *wptr = (uint16_t)ql_get_nvram_word(ha,
464 477 (uint32_t)(cnt + start_addr));
465 478 chksum = (uint8_t)(chksum + (uint8_t)*wptr);
466 479 chksum = (uint8_t)(chksum + (uint8_t)(*wptr >> 8));
467 480 wptr++;
468 481 }
469 482 ql_release_nvram(ha);
470 483 }
471 484
472 485 /* Bad NVRAM data, set defaults parameters. */
473 486 if (rval != QL_SUCCESS || chksum || nv->id[0] != 'I' ||
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474 487 nv->id[1] != 'S' || nv->id[2] != 'P' || nv->id[3] != ' ' ||
475 488 nv->nvram_version < 1) {
476 489
477 490 EL(ha, "failed, rval=%xh, checksum=%xh, "
478 491 "id=%02x%02x%02x%02xh, flsz=%xh, pciconfvid=%xh, "
479 492 "nvram_version=%x\n", rval, chksum, nv->id[0], nv->id[1],
480 493 nv->id[2], nv->id[3], ha->xioctl->fdesc.flash_size,
481 494 ha->subven_id, nv->nvram_version);
482 495
483 496 /* Don't print nvram message if it's an on-board 2200 */
484 - if (!((CFG_IST(ha, CFG_CTRL_2200)) &&
497 + if (!((CFG_IST(ha, CFG_CTRL_22XX)) &&
485 498 (ha->xioctl->fdesc.flash_size == 0))) {
486 499 cmn_err(CE_WARN, "%s(%d): NVRAM configuration failed,"
487 500 " using driver defaults.", QL_NAME, ha->instance);
488 501 }
489 502
490 503 /* Reset NVRAM data. */
491 504 bzero((void *)nv, sizeof (nvram_t));
492 505
493 506 /*
494 507 * Set default initialization control block.
495 508 */
496 509 nv->parameter_block_version = ICB_VERSION;
497 510 nv->firmware_options[0] = BIT_4 | BIT_3 | BIT_2 | BIT_1;
498 511 nv->firmware_options[1] = BIT_7 | BIT_5 | BIT_2;
499 512
500 513 nv->max_frame_length[1] = 4;
501 514
502 515 /*
503 516 * Allow 2048 byte frames for 2300
504 517 */
505 - if (CFG_IST(ha, (CFG_CTRL_2300 | CFG_CTRL_6322))) {
518 + if (CFG_IST(ha, CFG_CTRL_2363)) {
506 519 nv->max_frame_length[1] = 8;
507 520 }
508 521 nv->max_iocb_allocation[1] = 1;
509 522 nv->execution_throttle[0] = 16;
510 523 nv->login_retry_count = 8;
511 524
512 525 idpromlen = 32;
513 526
514 527 /*LINTED [Solaris DDI_DEV_T_ANY Lint warning]*/
515 528 if (ddi_getlongprop_buf(DDI_DEV_T_ANY, ha->dip,
516 529 DDI_PROP_CANSLEEP, "idprom", (caddr_t)idprombuf,
517 530 &idpromlen) != DDI_PROP_SUCCESS) {
518 531
519 - QL_PRINT_3(CE_CONT, "(%d): Unable to read idprom "
520 - "property\n", ha->instance);
532 + QL_PRINT_10(ha, "Unable to read idprom "
533 + "property\n");
521 534 cmn_err(CE_WARN, "%s(%d) : Unable to read idprom "
522 535 "property", QL_NAME, ha->instance);
523 536
524 537 nv->port_name[2] = 33;
525 538 nv->port_name[3] = 224;
526 539 nv->port_name[4] = 139;
527 540 nv->port_name[7] = (uint8_t)
528 541 (NAA_ID_IEEE_EXTENDED << 4 | ha->instance);
529 542 } else {
530 543
531 544 nv->port_name[2] = idprombuf[2];
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532 545 nv->port_name[3] = idprombuf[3];
533 546 nv->port_name[4] = idprombuf[4];
534 547 nv->port_name[5] = idprombuf[5];
535 548 nv->port_name[6] = idprombuf[6];
536 549 nv->port_name[7] = idprombuf[7];
537 550 nv->port_name[0] = (uint8_t)
538 551 (NAA_ID_IEEE_EXTENDED << 4 | ha->instance);
539 552 }
540 553
541 554 /* Don't print nvram message if it's an on-board 2200 */
542 - if (!(CFG_IST(ha, CFG_CTRL_2200)) &&
555 + if (!(CFG_IST(ha, CFG_CTRL_22XX)) &&
543 556 (ha->xioctl->fdesc.flash_size == 0)) {
544 557 cmn_err(CE_WARN, "%s(%d): Unreliable HBA NVRAM, using"
545 558 " default HBA parameters and temporary WWPN:"
546 559 " %02x%02x%02x%02x%02x%02x%02x%02x", QL_NAME,
547 560 ha->instance, nv->port_name[0], nv->port_name[1],
548 561 nv->port_name[2], nv->port_name[3],
549 562 nv->port_name[4], nv->port_name[5],
550 563 nv->port_name[6], nv->port_name[7]);
551 564 }
552 565
553 566 nv->login_timeout = 4;
554 567
555 568 /* Set default connection options for the 23xx to 2 */
556 - if (!(CFG_IST(ha, CFG_CTRL_2200))) {
569 + if (!(CFG_IST(ha, CFG_CTRL_22XX))) {
557 570 nv->add_fw_opt[0] = (uint8_t)(nv->add_fw_opt[0] |
558 571 BIT_5);
559 572 }
560 573
561 574 /*
562 575 * Set default host adapter parameters
563 576 */
564 577 nv->host_p[0] = BIT_1;
565 578 nv->host_p[1] = BIT_2;
566 579 nv->reset_delay = 5;
567 580 nv->port_down_retry_count = 8;
568 581 nv->maximum_luns_per_target[0] = 8;
569 582
570 583 rval = QL_FUNCTION_FAILED;
571 584 }
572 585
573 - /* Check for adapter node name (big endian). */
574 - for (cnt = 0; cnt < 8; cnt++) {
575 - if (nv->node_name[cnt] != 0) {
576 - break;
577 - }
578 - }
579 -
580 - /* Copy port name if no node name (big endian). */
581 - if (cnt == 8) {
582 - bcopy((void *)&nv->port_name[0], (void *)&nv->node_name[0], 8);
583 - nv->node_name[0] = (uint8_t)(nv->node_name[0] & ~BIT_0);
584 - nv->port_name[0] = (uint8_t)(nv->node_name[0] | BIT_0);
585 - }
586 -
587 586 /* Reset initialization control blocks. */
588 587 bzero((void *)icb, sizeof (ql_init_cb_t));
588 + bzero((void *)ip_icb, sizeof (ql_ip_init_cb_t));
589 589
590 - /* Get driver properties. */
591 - ql_23_properties(ha, nv);
592 -
593 - cmn_err(CE_CONT, "!Qlogic %s(%d) WWPN=%02x%02x%02x%02x"
594 - "%02x%02x%02x%02x : WWNN=%02x%02x%02x%02x%02x%02x%02x%02x\n",
595 - QL_NAME, ha->instance, nv->port_name[0], nv->port_name[1],
596 - nv->port_name[2], nv->port_name[3], nv->port_name[4],
597 - nv->port_name[5], nv->port_name[6], nv->port_name[7],
598 - nv->node_name[0], nv->node_name[1], nv->node_name[2],
599 - nv->node_name[3], nv->node_name[4], nv->node_name[5],
600 - nv->node_name[6], nv->node_name[7]);
601 -
602 590 /*
603 591 * Copy over NVRAM RISC parameter block
604 592 * to initialization control block.
605 593 */
606 594 dptr1 = (caddr_t)icb;
607 595 dptr2 = (caddr_t)&nv->parameter_block_version;
608 596 cnt = (uint32_t)((uintptr_t)&icb->request_q_outpointer[0] -
609 597 (uintptr_t)&icb->version);
610 598 while (cnt-- != 0) {
611 599 *dptr1++ = *dptr2++;
612 600 }
613 601
614 602 /* Copy 2nd half. */
615 603 dptr1 = (caddr_t)&icb->add_fw_opt[0];
616 604 cnt = (uint32_t)((uintptr_t)&icb->reserved_3[0] -
617 605 (uintptr_t)&icb->add_fw_opt[0]);
618 -
619 606 while (cnt-- != 0) {
620 607 *dptr1++ = *dptr2++;
621 608 }
622 609
610 + ha->execution_throttle = CHAR_TO_SHORT(nv->execution_throttle[0],
611 + nv->execution_throttle[1]);
612 + ha->loop_reset_delay = nv->reset_delay;
613 + ha->port_down_retry_count = nv->port_down_retry_count;
614 + ha->maximum_luns_per_target = CHAR_TO_SHORT(
615 + nv->maximum_luns_per_target[0], nv->maximum_luns_per_target[1]);
616 + if (ha->maximum_luns_per_target == 0) {
617 + ha->maximum_luns_per_target++;
618 + }
619 + ha->adapter_features = CHAR_TO_SHORT(nv->adapter_features[0],
620 + nv->adapter_features[1]);
621 +
622 + /* Check for adapter node name (big endian). */
623 + for (cnt = 0; cnt < 8; cnt++) {
624 + if (icb->node_name[cnt] != 0) {
625 + break;
626 + }
627 + }
628 +
629 + /* Copy port name if no node name (big endian). */
630 + if (cnt == 8) {
631 + for (cnt = 0; cnt < 8; cnt++) {
632 + icb->node_name[cnt] = icb->port_name[cnt];
633 + }
634 + icb->node_name[0] = (uint8_t)(icb->node_name[0] & ~BIT_0);
635 + icb->port_name[0] = (uint8_t)(icb->node_name[0] | BIT_0);
636 + }
637 +
638 + ADAPTER_STATE_LOCK(ha);
639 + ha->cfg_flags &= ~(CFG_ENABLE_FULL_LIP_LOGIN | CFG_ENABLE_TARGET_RESET |
640 + CFG_ENABLE_LIP_RESET | CFG_LOAD_FLASH_FW | CFG_FAST_TIMEOUT |
641 + CFG_DISABLE_RISC_CODE_LOAD | CFG_ENABLE_FWEXTTRACE |
642 + CFG_ENABLE_FWFCETRACE | CFG_SET_CACHE_LINE_SIZE_1 | CFG_LR_SUPPORT);
643 + if (nv->host_p[0] & BIT_4) {
644 + ha->cfg_flags |= CFG_DISABLE_RISC_CODE_LOAD;
645 + }
646 + if (nv->host_p[0] & BIT_5) {
647 + ha->cfg_flags |= CFG_SET_CACHE_LINE_SIZE_1;
648 + }
649 + if (nv->host_p[1] & BIT_2) {
650 + ha->cfg_flags |= CFG_ENABLE_FULL_LIP_LOGIN;
651 + }
652 + if (nv->host_p[1] & BIT_3) {
653 + ha->cfg_flags |= CFG_ENABLE_TARGET_RESET;
654 + }
655 + nv->adapter_features[0] & BIT_3 ?
656 + (ha->flags |= MULTI_CHIP_ADAPTER) :
657 + (ha->flags &= ~MULTI_CHIP_ADAPTER);
658 + ADAPTER_STATE_UNLOCK(ha);
659 +
660 + /* Get driver properties. */
661 + ql_23_properties(ha, icb);
662 +
623 663 /*
624 664 * Setup driver firmware options.
625 665 */
626 666 icb->firmware_options[0] = (uint8_t)
627 667 (icb->firmware_options[0] | BIT_6 | BIT_1);
628 668
629 669 /*
630 670 * There is no use enabling fast post for SBUS or 2300
631 671 * Always enable 64bit addressing, except SBUS cards.
632 672 */
633 673 ha->cfg_flags |= CFG_ENABLE_64BIT_ADDRESSING;
634 - if (CFG_IST(ha, (CFG_SBUS_CARD | CFG_CTRL_2300 | CFG_CTRL_6322))) {
674 + if (CFG_IST(ha, CFG_SBUS_CARD | CFG_CTRL_2363)) {
635 675 icb->firmware_options[0] = (uint8_t)
636 676 (icb->firmware_options[0] & ~BIT_3);
637 677 if (CFG_IST(ha, CFG_SBUS_CARD)) {
638 678 icb->special_options[0] = (uint8_t)
639 679 (icb->special_options[0] | BIT_5);
640 680 ha->cfg_flags &= ~CFG_ENABLE_64BIT_ADDRESSING;
641 681 }
642 682 } else {
643 683 icb->firmware_options[0] = (uint8_t)
644 684 (icb->firmware_options[0] | BIT_3);
645 685 }
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646 686 /* RIO and ZIO not supported. */
647 687 icb->add_fw_opt[0] = (uint8_t)(icb->add_fw_opt[0] &
648 688 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
649 689
650 690 icb->firmware_options[1] = (uint8_t)(icb->firmware_options[1] |
651 691 BIT_7 | BIT_6 | BIT_5 | BIT_2 | BIT_0);
652 692 icb->firmware_options[0] = (uint8_t)
653 693 (icb->firmware_options[0] & ~(BIT_5 | BIT_4));
654 694 icb->firmware_options[1] = (uint8_t)
655 695 (icb->firmware_options[1] & ~BIT_4);
656 -
696 + if (CFG_IST(ha, CFG_ENABLE_FCP_2_SUPPORT)) {
697 + icb->firmware_options[1] = (uint8_t)
698 + (icb->firmware_options[1] | BIT_7 | BIT_6);
699 + icb->add_fw_opt[1] = (uint8_t)
700 + (icb->add_fw_opt[1] | BIT_5 | BIT_4);
701 + }
657 702 icb->add_fw_opt[1] = (uint8_t)(icb->add_fw_opt[1] & ~(BIT_5 | BIT_4));
658 703 icb->special_options[0] = (uint8_t)(icb->special_options[0] | BIT_1);
659 704
660 - if (CFG_IST(ha, (CFG_CTRL_2300 | CFG_CTRL_6322))) {
705 + if (CFG_IST(ha, CFG_CTRL_2363)) {
661 706 if ((icb->special_options[1] & 0x20) == 0) {
662 707 EL(ha, "50 ohm is not set\n");
663 708 }
664 709 }
665 - icb->execution_throttle[0] = 0xff;
666 - icb->execution_throttle[1] = 0xff;
667 710
668 - if (CFG_IST(ha, CFG_ENABLE_FCP_2_SUPPORT)) {
669 - icb->firmware_options[1] = (uint8_t)
670 - (icb->firmware_options[1] | BIT_7 | BIT_6);
671 - icb->add_fw_opt[1] = (uint8_t)
672 - (icb->add_fw_opt[1] | BIT_5 | BIT_4);
673 - }
674 -
675 711 /*
676 712 * Set host adapter parameters
677 713 */
678 - ADAPTER_STATE_LOCK(ha);
679 - ha->nvram_version = nv->nvram_version;
680 - ha->adapter_features = CHAR_TO_SHORT(nv->adapter_features[0],
681 - nv->adapter_features[1]);
714 + /* Get adapter id string for Sun branded 23xx only */
715 + if (CFG_IST(ha, CFG_CTRL_23XX) && nv->adapInfo[0] != 0) {
716 + (void) snprintf((int8_t *)ha->adapInfo, 16, "%s",
717 + nv->adapInfo);
718 + }
682 719
683 - nv->host_p[0] & BIT_4 ? (ha->cfg_flags |= CFG_DISABLE_RISC_CODE_LOAD) :
684 - (ha->cfg_flags &= ~CFG_DISABLE_RISC_CODE_LOAD);
685 - nv->host_p[0] & BIT_5 ? (ha->cfg_flags |= CFG_SET_CACHE_LINE_SIZE_1) :
686 - (ha->cfg_flags &= ~CFG_SET_CACHE_LINE_SIZE_1);
687 -
688 - nv->host_p[1] & BIT_1 ? (ha->cfg_flags |= CFG_ENABLE_LIP_RESET) :
689 - (ha->cfg_flags &= ~CFG_ENABLE_LIP_RESET);
690 - nv->host_p[1] & BIT_2 ? (ha->cfg_flags |= CFG_ENABLE_FULL_LIP_LOGIN) :
691 - (ha->cfg_flags &= ~CFG_ENABLE_FULL_LIP_LOGIN);
692 - nv->host_p[1] & BIT_3 ? (ha->cfg_flags |= CFG_ENABLE_TARGET_RESET) :
693 - (ha->cfg_flags &= ~CFG_ENABLE_TARGET_RESET);
694 -
695 - nv->adapter_features[0] & BIT_3 ?
696 - (ha->cfg_flags |= CFG_MULTI_CHIP_ADAPTER) :
697 - (ha->cfg_flags &= ~CFG_MULTI_CHIP_ADAPTER);
698 -
699 - ADAPTER_STATE_UNLOCK(ha);
700 -
701 - ha->execution_throttle = CHAR_TO_SHORT(nv->execution_throttle[0],
702 - nv->execution_throttle[1]);
703 - ha->loop_reset_delay = nv->reset_delay;
704 - ha->port_down_retry_count = nv->port_down_retry_count;
705 720 ha->r_a_tov = (uint16_t)(icb->login_timeout < R_A_TOV_DEFAULT ?
706 721 R_A_TOV_DEFAULT : icb->login_timeout);
707 - ha->maximum_luns_per_target = CHAR_TO_SHORT(
708 - nv->maximum_luns_per_target[0], nv->maximum_luns_per_target[1]);
709 - if (ha->maximum_luns_per_target == 0) {
710 - ha->maximum_luns_per_target++;
711 - }
712 722
723 + els->common_service.rx_bufsize = CHAR_TO_SHORT(
724 + icb->max_frame_length[0], icb->max_frame_length[1]);
725 + bcopy((void *)icb->port_name, (void *)els->nport_ww_name.raw_wwn, 8);
726 + bcopy((void *)icb->node_name, (void *)els->node_ww_name.raw_wwn, 8);
727 +
728 + cmn_err(CE_CONT, "!Qlogic %s(%d) WWPN=%02x%02x%02x%02x"
729 + "%02x%02x%02x%02x : WWNN=%02x%02x%02x%02x%02x%02x%02x%02x\n",
730 + QL_NAME, ha->instance,
731 + els->nport_ww_name.raw_wwn[0], els->nport_ww_name.raw_wwn[1],
732 + els->nport_ww_name.raw_wwn[2], els->nport_ww_name.raw_wwn[3],
733 + els->nport_ww_name.raw_wwn[4], els->nport_ww_name.raw_wwn[5],
734 + els->nport_ww_name.raw_wwn[6], els->nport_ww_name.raw_wwn[7],
735 + els->node_ww_name.raw_wwn[0], els->node_ww_name.raw_wwn[1],
736 + els->node_ww_name.raw_wwn[2], els->node_ww_name.raw_wwn[3],
737 + els->node_ww_name.raw_wwn[4], els->node_ww_name.raw_wwn[5],
738 + els->node_ww_name.raw_wwn[6], els->node_ww_name.raw_wwn[7]);
713 739 /*
714 740 * Setup ring parameters in initialization control block
715 741 */
716 - cnt = REQUEST_ENTRY_CNT;
742 + cnt = ha->req_q[0]->req_entry_cnt;
717 743 icb->request_q_length[0] = LSB(cnt);
718 744 icb->request_q_length[1] = MSB(cnt);
719 - cnt = RESPONSE_ENTRY_CNT;
745 + cnt = ha->rsp_queues[0]->rsp_entry_cnt;
720 746 icb->response_q_length[0] = LSB(cnt);
721 747 icb->response_q_length[1] = MSB(cnt);
722 748
723 - icb->request_q_address[0] = LSB(LSW(LSD(ha->request_dvma)));
724 - icb->request_q_address[1] = MSB(LSW(LSD(ha->request_dvma)));
725 - icb->request_q_address[2] = LSB(MSW(LSD(ha->request_dvma)));
726 - icb->request_q_address[3] = MSB(MSW(LSD(ha->request_dvma)));
727 - icb->request_q_address[4] = LSB(LSW(MSD(ha->request_dvma)));
728 - icb->request_q_address[5] = MSB(LSW(MSD(ha->request_dvma)));
729 - icb->request_q_address[6] = LSB(MSW(MSD(ha->request_dvma)));
730 - icb->request_q_address[7] = MSB(MSW(MSD(ha->request_dvma)));
749 + start_addr = ha->req_q[0]->req_ring.cookie.dmac_address;
750 + icb->request_q_address[0] = LSB(LSW(start_addr));
751 + icb->request_q_address[1] = MSB(LSW(start_addr));
752 + icb->request_q_address[2] = LSB(MSW(start_addr));
753 + icb->request_q_address[3] = MSB(MSW(start_addr));
731 754
732 - icb->response_q_address[0] = LSB(LSW(LSD(ha->response_dvma)));
733 - icb->response_q_address[1] = MSB(LSW(LSD(ha->response_dvma)));
734 - icb->response_q_address[2] = LSB(MSW(LSD(ha->response_dvma)));
735 - icb->response_q_address[3] = MSB(MSW(LSD(ha->response_dvma)));
736 - icb->response_q_address[4] = LSB(LSW(MSD(ha->response_dvma)));
737 - icb->response_q_address[5] = MSB(LSW(MSD(ha->response_dvma)));
738 - icb->response_q_address[6] = LSB(MSW(MSD(ha->response_dvma)));
739 - icb->response_q_address[7] = MSB(MSW(MSD(ha->response_dvma)));
755 + start_addr = ha->req_q[0]->req_ring.cookie.dmac_notused;
756 + icb->request_q_address[4] = LSB(LSW(start_addr));
757 + icb->request_q_address[5] = MSB(LSW(start_addr));
758 + icb->request_q_address[6] = LSB(MSW(start_addr));
759 + icb->request_q_address[7] = MSB(MSW(start_addr));
740 760
761 + start_addr = ha->rsp_queues[0]->rsp_ring.cookie.dmac_address;
762 + icb->response_q_address[0] = LSB(LSW(start_addr));
763 + icb->response_q_address[1] = MSB(LSW(start_addr));
764 + icb->response_q_address[2] = LSB(MSW(start_addr));
765 + icb->response_q_address[3] = MSB(MSW(start_addr));
766 +
767 + start_addr = ha->rsp_queues[0]->rsp_ring.cookie.dmac_notused;
768 + icb->response_q_address[4] = LSB(LSW(start_addr));
769 + icb->response_q_address[5] = MSB(LSW(start_addr));
770 + icb->response_q_address[6] = LSB(MSW(start_addr));
771 + icb->response_q_address[7] = MSB(MSW(start_addr));
772 +
741 773 /*
742 774 * Setup IP initialization control block
743 775 */
744 776 ip_icb->version = IP_ICB_VERSION;
745 777
746 778 if (CFG_IST(ha, CFG_ENABLE_64BIT_ADDRESSING)) {
747 779 ip_icb->ip_firmware_options[0] = (uint8_t)
748 780 (ip_icb->ip_firmware_options[0] | BIT_2 | BIT_0);
749 781 } else {
750 782 ip_icb->ip_firmware_options[0] = (uint8_t)
751 783 (ip_icb->ip_firmware_options[0] | BIT_2);
752 784 }
753 785
754 786 cnt = RCVBUF_CONTAINER_CNT;
755 787 ip_icb->queue_size[0] = LSB(cnt);
756 788 ip_icb->queue_size[1] = MSB(cnt);
757 789
758 - ip_icb->queue_address[0] = LSB(LSW(LSD(ha->rcvbuf_dvma)));
759 - ip_icb->queue_address[1] = MSB(LSW(LSD(ha->rcvbuf_dvma)));
760 - ip_icb->queue_address[2] = LSB(MSW(LSD(ha->rcvbuf_dvma)));
761 - ip_icb->queue_address[3] = MSB(MSW(LSD(ha->rcvbuf_dvma)));
762 - ip_icb->queue_address[4] = LSB(LSW(MSD(ha->rcvbuf_dvma)));
763 - ip_icb->queue_address[5] = MSB(LSW(MSD(ha->rcvbuf_dvma)));
764 - ip_icb->queue_address[6] = LSB(MSW(MSD(ha->rcvbuf_dvma)));
765 - ip_icb->queue_address[7] = MSB(MSW(MSD(ha->rcvbuf_dvma)));
790 + start_addr = ha->rcv_ring.cookie.dmac_address;
791 + ip_icb->queue_address[0] = LSB(LSW(start_addr));
792 + ip_icb->queue_address[1] = MSB(LSW(start_addr));
793 + ip_icb->queue_address[2] = LSB(MSW(start_addr));
794 + ip_icb->queue_address[3] = MSB(MSW(start_addr));
766 795
796 + start_addr = ha->rcv_ring.cookie.dmac_notused;
797 + ip_icb->queue_address[4] = LSB(LSW(start_addr));
798 + ip_icb->queue_address[5] = MSB(LSW(start_addr));
799 + ip_icb->queue_address[6] = LSB(MSW(start_addr));
800 + ip_icb->queue_address[7] = MSB(MSW(start_addr));
801 +
767 802 if (rval != QL_SUCCESS) {
768 803 EL(ha, "failed, rval = %xh\n", rval);
769 804 } else {
770 805 /*EMPTY*/
771 - QL_PRINT_3(CE_CONT, "(%d): done\n", ha->instance);
806 + QL_PRINT_10(ha, "done\n");
772 807 }
773 808 return (rval);
774 809 }
775 810
776 811 /*
777 812 * Get NVRAM data word
778 813 * Calculates word position in NVRAM and calls request routine to
779 814 * get the word from NVRAM.
780 815 *
781 816 * Input:
782 817 * ha = adapter state pointer.
783 818 * address = NVRAM word address.
784 819 *
785 820 * Returns:
786 821 * data word.
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787 822 *
788 823 * Context:
789 824 * Kernel context.
790 825 */
791 826 uint16_t
792 827 ql_get_nvram_word(ql_adapter_state_t *ha, uint32_t address)
793 828 {
794 829 uint32_t nv_cmd;
795 830 uint16_t rval;
796 831
797 - QL_PRINT_4(CE_CONT, "(%d): started\n", ha->instance);
832 + QL_PRINT_4(ha, "started\n");
798 833
799 834 nv_cmd = address << 16;
800 835 nv_cmd = nv_cmd | NV_READ_OP;
801 836
802 837 rval = (uint16_t)ql_nvram_request(ha, nv_cmd);
803 838
804 - QL_PRINT_4(CE_CONT, "(%d): NVRAM data = %xh\n", ha->instance, rval);
839 + QL_PRINT_4(ha, "NVRAM data = %xh\n", rval);
805 840
806 841 return (rval);
807 842 }
808 843
809 844 /*
810 845 * NVRAM request
811 846 * Sends read command to NVRAM and gets data from NVRAM.
812 847 *
813 848 * Input:
814 849 * ha = adapter state pointer.
815 850 * nv_cmd = Bit 26= start bit
816 851 * Bit 25, 24 = opcode
817 852 * Bit 23-16 = address
818 853 * Bit 15-0 = write data
819 854 *
820 855 * Returns:
821 856 * data word.
822 857 *
823 858 * Context:
824 859 * Kernel context.
825 860 */
826 861 static uint16_t
827 862 ql_nvram_request(ql_adapter_state_t *ha, uint32_t nv_cmd)
828 863 {
829 864 uint8_t cnt;
830 865 uint16_t reg_data;
831 866 uint16_t data = 0;
832 867
833 868 /* Send command to NVRAM. */
834 869
835 870 nv_cmd <<= 5;
836 871 for (cnt = 0; cnt < 11; cnt++) {
837 872 if (nv_cmd & BIT_31) {
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838 873 ql_nv_write(ha, NV_DATA_OUT);
839 874 } else {
840 875 ql_nv_write(ha, 0);
841 876 }
842 877 nv_cmd <<= 1;
843 878 }
844 879
845 880 /* Read data from NVRAM. */
846 881
847 882 for (cnt = 0; cnt < 16; cnt++) {
848 - WRT16_IO_REG(ha, nvram, NV_SELECT+NV_CLOCK);
883 + WRT16_IO_REG(ha, nvram, NV_SELECT + NV_CLOCK);
849 884 ql_nv_delay();
850 885 data <<= 1;
851 886 reg_data = RD16_IO_REG(ha, nvram);
852 887 if (reg_data & NV_DATA_IN) {
853 888 data = (uint16_t)(data | BIT_0);
854 889 }
855 890 WRT16_IO_REG(ha, nvram, NV_SELECT);
856 891 ql_nv_delay();
857 892 }
858 893
859 894 /* Deselect chip. */
860 895
861 896 WRT16_IO_REG(ha, nvram, NV_DESELECT);
862 897 ql_nv_delay();
863 898
864 899 return (data);
865 900 }
866 901
867 902 void
868 903 ql_nv_write(ql_adapter_state_t *ha, uint16_t data)
869 904 {
870 905 WRT16_IO_REG(ha, nvram, (uint16_t)(data | NV_SELECT));
871 906 ql_nv_delay();
872 907 WRT16_IO_REG(ha, nvram, (uint16_t)(data | NV_SELECT | NV_CLOCK));
873 908 ql_nv_delay();
874 909 WRT16_IO_REG(ha, nvram, (uint16_t)(data | NV_SELECT));
875 910 ql_nv_delay();
876 911 }
877 912
878 913 void
879 914 ql_nv_delay(void)
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880 915 {
881 916 drv_usecwait(NV_DELAY_COUNT);
882 917 }
883 918
884 919 /*
885 920 * ql_nvram_24xx_config
886 921 * ISP2400 nvram.
887 922 *
888 923 * Input:
889 924 * ha: adapter state pointer.
890 - * ha->hba_buf = request and response rings
925 + * ha->req_q[0]: request ring
891 926 *
892 927 * Output:
893 928 * ha->init_ctrl_blk = initialization control block
894 929 * host adapters parameters in host adapter block
895 930 *
896 931 * Returns:
897 932 * ql local function return status code.
898 933 *
899 934 * Context:
900 935 * Kernel context.
901 936 */
902 937 int
903 938 ql_nvram_24xx_config(ql_adapter_state_t *ha)
904 939 {
905 - uint32_t index, addr, chksum, saved_chksum;
940 + uint32_t index, addr;
941 + uint32_t chksum = 0, saved_chksum = 0;
906 942 uint32_t *longptr;
907 943 nvram_24xx_t nvram;
908 944 int idpromlen;
909 945 char idprombuf[32];
910 946 caddr_t src, dst;
911 947 uint16_t w1;
912 948 int rval;
913 949 nvram_24xx_t *nv = (nvram_24xx_t *)&nvram;
914 950 ql_init_24xx_cb_t *icb =
915 951 (ql_init_24xx_cb_t *)&ha->init_ctrl_blk.cb24;
916 952 ql_ip_init_24xx_cb_t *ip_icb = &ha->ip_init_ctrl_blk.cb24;
953 + la_els_logi_t *els = &ha->loginparams;
917 954
918 - QL_PRINT_3(CE_CONT, "(%d): started\n", ha->instance);
955 + QL_PRINT_10(ha, "started\n");
919 956
920 957 if ((rval = ql_lock_nvram(ha, &addr, LNF_NVRAM_DATA)) == QL_SUCCESS) {
921 958
922 959 /* Get NVRAM data and calculate checksum. */
923 960 longptr = (uint32_t *)nv;
924 961 chksum = saved_chksum = 0;
925 962 for (index = 0; index < sizeof (nvram_24xx_t) / 4; index++) {
926 963 rval = ql_24xx_read_flash(ha, addr++, longptr);
927 964 if (rval != QL_SUCCESS) {
928 965 EL(ha, "24xx_read_flash failed=%xh\n", rval);
929 966 break;
930 967 }
931 968 saved_chksum = chksum;
932 969 chksum += *longptr;
933 970 LITTLE_ENDIAN_32(longptr);
934 971 longptr++;
935 972 }
936 973
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937 974 ql_release_nvram(ha);
938 975 }
939 976
940 977 /* Bad NVRAM data, set defaults parameters. */
941 978 if (rval != QL_SUCCESS || chksum || nv->id[0] != 'I' ||
942 979 nv->id[1] != 'S' || nv->id[2] != 'P' || nv->id[3] != ' ' ||
943 980 (nv->nvram_version[0] | nv->nvram_version[1]) == 0) {
944 981
945 982 cmn_err(CE_WARN, "%s(%d): NVRAM configuration failed, using "
946 983 "driver defaults.", QL_NAME, ha->instance);
947 -
948 984 EL(ha, "failed, rval=%xh, checksum=%xh, id=%c%c%c%c, "
949 985 "nvram_version=%x\n", rval, chksum, nv->id[0], nv->id[1],
950 986 nv->id[2], nv->id[3], CHAR_TO_SHORT(nv->nvram_version[0],
951 987 nv->nvram_version[1]));
952 988
953 989 saved_chksum = ~saved_chksum + 1;
954 990
955 991 (void) ql_flash_errlog(ha, FLASH_ERRLOG_NVRAM_CHKSUM_ERR, 0,
956 992 MSW(saved_chksum), LSW(saved_chksum));
957 993
958 994 /* Reset NVRAM data. */
959 995 bzero((void *)nv, sizeof (nvram_24xx_t));
960 996
961 997 /*
962 998 * Set default initialization control block.
963 999 */
964 1000 nv->nvram_version[0] = LSB(ICB_24XX_VERSION);
965 1001 nv->nvram_version[1] = MSB(ICB_24XX_VERSION);
966 1002
967 1003 nv->version[0] = 1;
968 1004 nv->max_frame_length[1] = 8;
969 1005 nv->execution_throttle[0] = 16;
970 1006 nv->exchange_count[0] = 128;
971 1007 nv->max_luns_per_target[0] = 8;
972 1008
973 1009 idpromlen = 32;
974 1010
975 1011 /*LINTED [Solaris DDI_DEV_T_ANY Lint warning]*/
976 1012 if (rval = ddi_getlongprop_buf(DDI_DEV_T_ANY, ha->dip,
977 1013 DDI_PROP_CANSLEEP, "idprom", (caddr_t)idprombuf,
978 1014 &idpromlen) != DDI_PROP_SUCCESS) {
979 1015
980 1016 cmn_err(CE_WARN, "%s(%d) : Unable to read idprom "
981 1017 "property, rval=%x", QL_NAME, ha->instance, rval);
982 1018
983 1019 nv->port_name[0] = 33;
984 1020 nv->port_name[3] = 224;
985 1021 nv->port_name[4] = 139;
986 1022 nv->port_name[7] = (uint8_t)
987 1023 (NAA_ID_IEEE_EXTENDED << 4 | ha->instance);
988 1024 } else {
989 1025 nv->port_name[2] = idprombuf[2];
990 1026 nv->port_name[3] = idprombuf[3];
991 1027 nv->port_name[4] = idprombuf[4];
992 1028 nv->port_name[5] = idprombuf[5];
993 1029 nv->port_name[6] = idprombuf[6];
994 1030 nv->port_name[7] = idprombuf[7];
995 1031 nv->port_name[0] = (uint8_t)
996 1032 (NAA_ID_IEEE_EXTENDED << 4 | ha->instance);
997 1033 }
998 1034
999 1035 cmn_err(CE_WARN, "%s(%d): Unreliable HBA NVRAM, using default "
1000 1036 "HBA parameters and temporary "
1001 1037 "WWPN: %02x%02x%02x%02x%02x%02x%02x%02x", QL_NAME,
1002 1038 ha->instance, nv->port_name[0], nv->port_name[1],
1003 1039 nv->port_name[2], nv->port_name[3], nv->port_name[4],
1004 1040 nv->port_name[5], nv->port_name[6], nv->port_name[7]);
1005 1041
1006 1042 nv->login_retry_count[0] = 8;
1007 1043
1008 1044 nv->firmware_options_1[0] = BIT_2 | BIT_1;
1009 1045 nv->firmware_options_1[1] = BIT_5;
1010 1046 nv->firmware_options_2[0] = BIT_5;
1011 1047 nv->firmware_options_2[1] = BIT_4;
1012 1048 nv->firmware_options_3[1] = BIT_6;
1013 1049
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1014 1050 /*
1015 1051 * Set default host adapter parameters
1016 1052 */
1017 1053 nv->host_p[0] = BIT_4 | BIT_1;
1018 1054 nv->host_p[1] = BIT_3 | BIT_2;
1019 1055 nv->reset_delay = 5;
1020 1056 nv->max_luns_per_target[0] = 128;
1021 1057 nv->port_down_retry_count[0] = 30;
1022 1058 nv->link_down_timeout[0] = 30;
1023 1059
1024 - if (CFG_IST(ha, CFG_CTRL_8081)) {
1060 + if (CFG_IST(ha, CFG_FCOE_SUPPORT)) {
1025 1061 nv->firmware_options_3[2] = BIT_4;
1026 1062 nv->feature_mask_l[0] = 9;
1027 1063 nv->ext_blk.version[0] = 1;
1028 1064 nv->ext_blk.fcf_vlan_match = 1;
1029 1065 nv->ext_blk.fcf_vlan_id[0] = LSB(1002);
1030 1066 nv->ext_blk.fcf_vlan_id[1] = MSB(1002);
1031 1067 nv->fw.isp8001.e_node_mac_addr[1] = 2;
1032 1068 nv->fw.isp8001.e_node_mac_addr[2] = 3;
1033 1069 nv->fw.isp8001.e_node_mac_addr[3] = 4;
1034 1070 nv->fw.isp8001.e_node_mac_addr[4] = MSB(ha->instance);
1035 1071 nv->fw.isp8001.e_node_mac_addr[5] = LSB(ha->instance);
1036 1072 }
1037 1073
1038 1074 rval = QL_FUNCTION_FAILED;
1039 1075 }
1040 1076
1041 - /* Check for adapter node name (big endian). */
1042 - for (index = 0; index < 8; index++) {
1043 - if (nv->node_name[index] != 0) {
1044 - break;
1045 - }
1046 - }
1047 -
1048 - /* Copy port name if no node name (big endian). */
1049 - if (index == 8) {
1050 - bcopy((void *)&nv->port_name[0], (void *)&nv->node_name[0], 8);
1051 - nv->node_name[0] = (uint8_t)(nv->node_name[0] & ~BIT_0);
1052 - nv->port_name[0] = (uint8_t)(nv->node_name[0] | BIT_0);
1053 - }
1054 -
1055 1077 /* Reset initialization control blocks. */
1056 1078 bzero((void *)icb, sizeof (ql_init_24xx_cb_t));
1057 1079
1058 - /* Get driver properties. */
1059 - ql_24xx_properties(ha, nv);
1060 -
1061 - cmn_err(CE_CONT, "!Qlogic %s(%d) WWPN=%02x%02x%02x%02x"
1062 - "%02x%02x%02x%02x : WWNN=%02x%02x%02x%02x%02x%02x%02x%02x\n",
1063 - QL_NAME, ha->instance, nv->port_name[0], nv->port_name[1],
1064 - nv->port_name[2], nv->port_name[3], nv->port_name[4],
1065 - nv->port_name[5], nv->port_name[6], nv->port_name[7],
1066 - nv->node_name[0], nv->node_name[1], nv->node_name[2],
1067 - nv->node_name[3], nv->node_name[4], nv->node_name[5],
1068 - nv->node_name[6], nv->node_name[7]);
1069 -
1070 1080 /*
1071 1081 * Copy over NVRAM Firmware Initialization Control Block.
1072 1082 */
1073 1083 dst = (caddr_t)icb;
1074 1084 src = (caddr_t)&nv->version;
1075 1085 index = (uint32_t)((uintptr_t)&icb->response_q_inpointer[0] -
1076 1086 (uintptr_t)icb);
1077 1087 while (index--) {
1078 1088 *dst++ = *src++;
1079 1089 }
1080 1090 icb->login_retry_count[0] = nv->login_retry_count[0];
1081 1091 icb->login_retry_count[1] = nv->login_retry_count[1];
1082 1092 icb->link_down_on_nos[0] = nv->link_down_on_nos[0];
1083 1093 icb->link_down_on_nos[1] = nv->link_down_on_nos[1];
1084 1094
1095 + /* Copy 2nd half. */
1085 1096 dst = (caddr_t)&icb->interrupt_delay_timer;
1086 1097 src = (caddr_t)&nv->interrupt_delay_timer;
1087 1098 index = (uint32_t)((uintptr_t)&icb->qos -
1088 1099 (uintptr_t)&icb->interrupt_delay_timer);
1089 1100 while (index--) {
1090 1101 *dst++ = *src++;
1091 1102 }
1092 1103
1093 - /*
1094 - * Setup driver firmware options.
1095 - */
1096 - if (CFG_IST(ha, CFG_CTRL_8081)) {
1104 + ha->execution_throttle = 16;
1105 + ha->loop_reset_delay = nv->reset_delay;
1106 + ha->port_down_retry_count = CHAR_TO_SHORT(nv->port_down_retry_count[0],
1107 + nv->port_down_retry_count[1]);
1108 + ha->maximum_luns_per_target = CHAR_TO_SHORT(
1109 + nv->max_luns_per_target[0], nv->max_luns_per_target[1]);
1110 + if (ha->maximum_luns_per_target == 0) {
1111 + ha->maximum_luns_per_target++;
1112 + }
1113 + if (CFG_IST(ha, CFG_FCOE_SUPPORT)) {
1097 1114 dst = (caddr_t)icb->enode_mac_addr;
1098 1115 src = (caddr_t)nv->fw.isp8001.e_node_mac_addr;
1099 1116 index = sizeof (nv->fw.isp8001.e_node_mac_addr);
1100 1117 while (index--) {
1101 1118 *dst++ = *src++;
1102 1119 }
1103 1120 dst = (caddr_t)&icb->ext_blk;
1104 1121 src = (caddr_t)&nv->ext_blk;
1105 1122 index = sizeof (ql_ext_icb_8100_t);
1106 1123 while (index--) {
1107 1124 *dst++ = *src++;
1108 1125 }
1109 1126 EL(ha, "e_node_mac_addr=%02x-%02x-%02x-%02x-%02x-%02x\n",
1110 1127 icb->enode_mac_addr[0], icb->enode_mac_addr[1],
1111 1128 icb->enode_mac_addr[2], icb->enode_mac_addr[3],
1112 1129 icb->enode_mac_addr[4], icb->enode_mac_addr[5]);
1113 - } else {
1130 + }
1131 +
1132 + /* Check for adapter node name (big endian). */
1133 + for (index = 0; index < 8; index++) {
1134 + if (icb->node_name[index] != 0) {
1135 + break;
1136 + }
1137 + }
1138 +
1139 + /* Copy port name if no node name (big endian). */
1140 + if (index == 8) {
1141 + for (index = 0; index < 8; index++) {
1142 + icb->node_name[index] = icb->port_name[index];
1143 + }
1144 + icb->node_name[0] = (uint8_t)(icb->node_name[0] & ~BIT_0);
1145 + icb->port_name[0] = (uint8_t)(icb->node_name[0] | BIT_0);
1146 + }
1147 +
1148 + ADAPTER_STATE_LOCK(ha);
1149 + ha->cfg_flags &= ~(CFG_ENABLE_FULL_LIP_LOGIN | CFG_ENABLE_TARGET_RESET |
1150 + CFG_ENABLE_LIP_RESET | CFG_LOAD_FLASH_FW | CFG_FAST_TIMEOUT |
1151 + CFG_DISABLE_RISC_CODE_LOAD | CFG_ENABLE_FWEXTTRACE |
1152 + CFG_ENABLE_FWFCETRACE | CFG_SET_CACHE_LINE_SIZE_1 | CFG_LR_SUPPORT);
1153 + if (nv->host_p[1] & BIT_2) {
1154 + ha->cfg_flags |= CFG_ENABLE_FULL_LIP_LOGIN;
1155 + }
1156 + if (nv->host_p[1] & BIT_3) {
1157 + ha->cfg_flags |= CFG_ENABLE_TARGET_RESET;
1158 + }
1159 + ha->flags &= ~MULTI_CHIP_ADAPTER;
1160 + ADAPTER_STATE_UNLOCK(ha);
1161 +
1162 + /* Get driver properties. */
1163 + ql_24xx_properties(ha, icb);
1164 +
1165 + /*
1166 + * Setup driver firmware options.
1167 + */
1168 + if (!CFG_IST(ha, CFG_FCOE_SUPPORT)) {
1114 1169 icb->firmware_options_1[0] = (uint8_t)
1115 1170 (icb->firmware_options_1[0] | BIT_1);
1116 1171 icb->firmware_options_1[1] = (uint8_t)
1117 1172 (icb->firmware_options_1[1] | BIT_5 | BIT_2);
1118 1173 icb->firmware_options_3[0] = (uint8_t)
1119 1174 (icb->firmware_options_3[0] | BIT_1);
1120 1175 }
1121 1176 icb->firmware_options_1[0] = (uint8_t)(icb->firmware_options_1[0] &
1122 1177 ~(BIT_5 | BIT_4));
1123 1178 icb->firmware_options_1[1] = (uint8_t)(icb->firmware_options_1[1] |
1124 1179 BIT_6);
1125 1180 icb->firmware_options_2[0] = (uint8_t)(icb->firmware_options_2[0] &
1126 1181 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
1127 1182 if (CFG_IST(ha, CFG_ENABLE_FCP_2_SUPPORT)) {
1128 1183 icb->firmware_options_2[1] = (uint8_t)
1129 1184 (icb->firmware_options_2[1] | BIT_4);
1130 1185 } else {
1131 1186 icb->firmware_options_2[1] = (uint8_t)
1132 1187 (icb->firmware_options_2[1] & ~BIT_4);
1133 1188 }
1134 -
1135 1189 icb->firmware_options_3[0] = (uint8_t)(icb->firmware_options_3[0] &
1136 1190 ~BIT_7);
1137 1191
1138 - /* enable special N port 2 N port login behaviour */
1139 - if (CFG_IST(ha, CFG_CTRL_2425)) {
1140 - icb->firmware_options_3[1] =
1141 - (uint8_t)(icb->firmware_options_3[1] | BIT_0);
1142 - }
1143 -
1144 - icb->execution_throttle[0] = 0xff;
1145 - icb->execution_throttle[1] = 0xff;
1146 -
1147 1192 /*
1148 1193 * Set host adapter parameters
1149 1194 */
1195 + w1 = CHAR_TO_SHORT(icb->login_timeout[0], icb->login_timeout[1]);
1196 + ha->r_a_tov = (uint16_t)(w1 < R_A_TOV_DEFAULT ? R_A_TOV_DEFAULT : w1);
1197 +
1150 1198 ADAPTER_STATE_LOCK(ha);
1151 - ha->nvram_version = CHAR_TO_SHORT(nv->nvram_version[0],
1152 - nv->nvram_version[1]);
1153 - nv->host_p[1] & BIT_2 ? (ha->cfg_flags |= CFG_ENABLE_FULL_LIP_LOGIN) :
1154 - (ha->cfg_flags &= ~CFG_ENABLE_FULL_LIP_LOGIN);
1155 - nv->host_p[1] & BIT_3 ? (ha->cfg_flags |= CFG_ENABLE_TARGET_RESET) :
1156 - (ha->cfg_flags &= ~CFG_ENABLE_TARGET_RESET);
1157 - ha->cfg_flags &= ~(CFG_DISABLE_RISC_CODE_LOAD | CFG_LR_SUPPORT |
1158 - CFG_SET_CACHE_LINE_SIZE_1 | CFG_MULTI_CHIP_ADAPTER);
1159 1199 ha->cfg_flags |= CFG_ENABLE_64BIT_ADDRESSING;
1160 1200 if (CFG_IST(ha, CFG_CTRL_81XX) && nv->enhanced_features[0] & BIT_0) {
1161 1201 ha->cfg_flags |= CFG_LR_SUPPORT;
1162 1202 }
1163 1203 ADAPTER_STATE_UNLOCK(ha);
1164 1204
1165 - ha->execution_throttle = CHAR_TO_SHORT(nv->execution_throttle[0],
1166 - nv->execution_throttle[1]);
1167 - ha->loop_reset_delay = nv->reset_delay;
1168 - ha->port_down_retry_count = CHAR_TO_SHORT(nv->port_down_retry_count[0],
1169 - nv->port_down_retry_count[1]);
1170 - w1 = CHAR_TO_SHORT(icb->login_timeout[0], icb->login_timeout[1]);
1171 - ha->r_a_tov = (uint16_t)(w1 < R_A_TOV_DEFAULT ? R_A_TOV_DEFAULT : w1);
1172 - ha->maximum_luns_per_target = CHAR_TO_SHORT(
1173 - nv->max_luns_per_target[0], nv->max_luns_per_target[1]);
1174 - if (ha->maximum_luns_per_target == 0) {
1175 - ha->maximum_luns_per_target++;
1205 + /* Queue shadowing */
1206 + if (ha->flags & QUEUE_SHADOW_PTRS) {
1207 + icb->firmware_options_2[3] = (uint8_t)
1208 + (icb->firmware_options_2[3] | BIT_6 | BIT_5);
1209 + } else {
1210 + icb->firmware_options_2[3] = (uint8_t)
1211 + (icb->firmware_options_2[3] | ~(BIT_6 | BIT_5));
1176 1212 }
1177 1213
1178 1214 /* ISP2422 Serial Link Control */
1179 - if (CFG_IST(ha, CFG_CTRL_2422)) {
1215 + if (CFG_IST(ha, CFG_CTRL_24XX)) {
1180 1216 ha->serdes_param[0] = CHAR_TO_SHORT(nv->fw.isp2400.swing_opt[0],
1181 1217 nv->fw.isp2400.swing_opt[1]);
1182 1218 ha->serdes_param[1] = CHAR_TO_SHORT(nv->fw.isp2400.swing_1g[0],
1183 1219 nv->fw.isp2400.swing_1g[1]);
1184 1220 ha->serdes_param[2] = CHAR_TO_SHORT(nv->fw.isp2400.swing_2g[0],
1185 1221 nv->fw.isp2400.swing_2g[1]);
1186 1222 ha->serdes_param[3] = CHAR_TO_SHORT(nv->fw.isp2400.swing_4g[0],
1187 1223 nv->fw.isp2400.swing_4g[1]);
1188 1224 }
1189 1225
1226 + els->common_service.rx_bufsize = CHAR_TO_SHORT(
1227 + icb->max_frame_length[0], icb->max_frame_length[1]);
1228 + bcopy((void *)icb->port_name, (void *)els->nport_ww_name.raw_wwn, 8);
1229 + bcopy((void *)icb->node_name, (void *)els->node_ww_name.raw_wwn, 8);
1230 +
1231 + cmn_err(CE_CONT, "!Qlogic %s(%d) WWPN=%02x%02x%02x%02x"
1232 + "%02x%02x%02x%02x : WWNN=%02x%02x%02x%02x%02x%02x%02x%02x\n",
1233 + QL_NAME, ha->instance,
1234 + els->nport_ww_name.raw_wwn[0], els->nport_ww_name.raw_wwn[1],
1235 + els->nport_ww_name.raw_wwn[2], els->nport_ww_name.raw_wwn[3],
1236 + els->nport_ww_name.raw_wwn[4], els->nport_ww_name.raw_wwn[5],
1237 + els->nport_ww_name.raw_wwn[6], els->nport_ww_name.raw_wwn[7],
1238 + els->node_ww_name.raw_wwn[0], els->node_ww_name.raw_wwn[1],
1239 + els->node_ww_name.raw_wwn[2], els->node_ww_name.raw_wwn[3],
1240 + els->node_ww_name.raw_wwn[4], els->node_ww_name.raw_wwn[5],
1241 + els->node_ww_name.raw_wwn[6], els->node_ww_name.raw_wwn[7]);
1190 1242 /*
1191 1243 * Setup ring parameters in initialization control block
1192 1244 */
1193 - w1 = REQUEST_ENTRY_CNT;
1245 + w1 = ha->req_q[0]->req_entry_cnt;
1194 1246 icb->request_q_length[0] = LSB(w1);
1195 1247 icb->request_q_length[1] = MSB(w1);
1196 - w1 = RESPONSE_ENTRY_CNT;
1248 + w1 = ha->rsp_queues[0]->rsp_entry_cnt;
1197 1249 icb->response_q_length[0] = LSB(w1);
1198 1250 icb->response_q_length[1] = MSB(w1);
1199 1251
1200 - icb->request_q_address[0] = LSB(LSW(LSD(ha->request_dvma)));
1201 - icb->request_q_address[1] = MSB(LSW(LSD(ha->request_dvma)));
1202 - icb->request_q_address[2] = LSB(MSW(LSD(ha->request_dvma)));
1203 - icb->request_q_address[3] = MSB(MSW(LSD(ha->request_dvma)));
1204 - icb->request_q_address[4] = LSB(LSW(MSD(ha->request_dvma)));
1205 - icb->request_q_address[5] = MSB(LSW(MSD(ha->request_dvma)));
1206 - icb->request_q_address[6] = LSB(MSW(MSD(ha->request_dvma)));
1207 - icb->request_q_address[7] = MSB(MSW(MSD(ha->request_dvma)));
1252 + addr = ha->req_q[0]->req_ring.cookie.dmac_address;
1253 + icb->request_q_address[0] = LSB(LSW(addr));
1254 + icb->request_q_address[1] = MSB(LSW(addr));
1255 + icb->request_q_address[2] = LSB(MSW(addr));
1256 + icb->request_q_address[3] = MSB(MSW(addr));
1208 1257
1209 - icb->response_q_address[0] = LSB(LSW(LSD(ha->response_dvma)));
1210 - icb->response_q_address[1] = MSB(LSW(LSD(ha->response_dvma)));
1211 - icb->response_q_address[2] = LSB(MSW(LSD(ha->response_dvma)));
1212 - icb->response_q_address[3] = MSB(MSW(LSD(ha->response_dvma)));
1213 - icb->response_q_address[4] = LSB(LSW(MSD(ha->response_dvma)));
1214 - icb->response_q_address[5] = MSB(LSW(MSD(ha->response_dvma)));
1215 - icb->response_q_address[6] = LSB(MSW(MSD(ha->response_dvma)));
1216 - icb->response_q_address[7] = MSB(MSW(MSD(ha->response_dvma)));
1258 + addr = ha->req_q[0]->req_ring.cookie.dmac_notused;
1259 + icb->request_q_address[4] = LSB(LSW(addr));
1260 + icb->request_q_address[5] = MSB(LSW(addr));
1261 + icb->request_q_address[6] = LSB(MSW(addr));
1262 + icb->request_q_address[7] = MSB(MSW(addr));
1217 1263
1264 + addr = ha->rsp_queues[0]->rsp_ring.cookie.dmac_address;
1265 + icb->response_q_address[0] = LSB(LSW(addr));
1266 + icb->response_q_address[1] = MSB(LSW(addr));
1267 + icb->response_q_address[2] = LSB(MSW(addr));
1268 + icb->response_q_address[3] = MSB(MSW(addr));
1269 +
1270 + addr = ha->rsp_queues[0]->rsp_ring.cookie.dmac_notused;
1271 + icb->response_q_address[4] = LSB(LSW(addr));
1272 + icb->response_q_address[5] = MSB(LSW(addr));
1273 + icb->response_q_address[6] = LSB(MSW(addr));
1274 + icb->response_q_address[7] = MSB(MSW(addr));
1275 +
1218 1276 /*
1219 1277 * Setup IP initialization control block
1220 1278 */
1221 1279 ip_icb->version = IP_ICB_24XX_VERSION;
1222 1280
1223 1281 ip_icb->ip_firmware_options[0] = (uint8_t)
1224 1282 (ip_icb->ip_firmware_options[0] | BIT_2);
1225 1283
1226 1284 if (rval != QL_SUCCESS) {
1227 1285 EL(ha, "failed, rval = %xh\n", rval);
1228 1286 } else {
1229 1287 /*EMPTY*/
1230 - QL_PRINT_3(CE_CONT, "(%d): done\n", ha->instance);
1288 + QL_PRINT_10(ha, "done\n");
1231 1289 }
1232 1290 return (rval);
1233 1291 }
1234 1292
1235 1293 /*
1236 1294 * ql_lock_nvram
1237 1295 * Locks NVRAM access and returns starting address of NVRAM.
1238 1296 *
1239 1297 * Input:
1240 1298 * ha: adapter state pointer.
1241 1299 * addr: pointer for start address.
1242 1300 * flags: Are mutually exclusive:
1243 1301 * LNF_NVRAM_DATA --> get nvram
1244 1302 * LNF_VPD_DATA --> get vpd data (24/25xx only).
1245 1303 *
1246 1304 * Returns:
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1247 1305 * ql local function return status code.
1248 1306 *
1249 1307 * Context:
1250 1308 * Kernel context.
1251 1309 */
1252 1310 int
1253 1311 ql_lock_nvram(ql_adapter_state_t *ha, uint32_t *addr, uint32_t flags)
1254 1312 {
1255 1313 int i;
1256 1314
1315 + QL_PRINT_3(ha, "started\n");
1316 +
1257 1317 if ((flags & LNF_NVRAM_DATA) && (flags & LNF_VPD_DATA)) {
1258 1318 EL(ha, "invalid options for function");
1259 1319 return (QL_FUNCTION_FAILED);
1260 1320 }
1261 1321
1262 1322 if (ha->device_id == 0x2312 || ha->device_id == 0x2322) {
1263 1323 if ((flags & LNF_NVRAM_DATA) == 0) {
1264 1324 EL(ha, "invalid 2312/2322 option for HBA");
1265 1325 return (QL_FUNCTION_FAILED);
1266 1326 }
1267 1327
1268 1328 /* if function number is non-zero, then adjust offset */
1269 1329 *addr = ha->flash_nvram_addr;
1270 1330
1271 1331 /* Try to get resource lock. Wait for 10 seconds max */
1272 1332 for (i = 0; i < 10000; i++) {
1273 1333 /* if nvram busy bit is reset, acquire sema */
1274 1334 if ((RD16_IO_REG(ha, nvram) & 0x8000) == 0) {
1275 1335 WRT16_IO_REG(ha, host_to_host_sema, 1);
1276 1336 drv_usecwait(MILLISEC);
1277 1337 if (RD16_IO_REG(ha, host_to_host_sema) & 1) {
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1278 1338 break;
1279 1339 }
1280 1340 }
1281 1341 drv_usecwait(MILLISEC);
1282 1342 }
1283 1343 if ((RD16_IO_REG(ha, host_to_host_sema) & 1) == 0) {
1284 1344 cmn_err(CE_WARN, "%s(%d): unable to get NVRAM lock",
1285 1345 QL_NAME, ha->instance);
1286 1346 return (QL_FUNCTION_FAILED);
1287 1347 }
1288 - } else if (CFG_IST(ha, CFG_CTRL_2422)) {
1348 + } else if (CFG_IST(ha, CFG_CTRL_24XX)) {
1289 1349 if (flags & LNF_VPD_DATA) {
1290 1350 *addr = NVRAM_DATA_ADDR | ha->flash_vpd_addr;
1291 1351 } else if (flags & LNF_NVRAM_DATA) {
1292 1352 *addr = NVRAM_DATA_ADDR | ha->flash_nvram_addr;
1293 1353 } else {
1294 1354 EL(ha, "invalid 2422 option for HBA");
1295 1355 return (QL_FUNCTION_FAILED);
1296 1356 }
1297 1357
1298 1358 GLOBAL_HW_LOCK();
1299 - } else if (CFG_IST(ha, CFG_CTRL_258081)) {
1359 + } else if (CFG_IST(ha, CFG_CTRL_252780818283)) {
1300 1360 if (flags & LNF_VPD_DATA) {
1301 1361 *addr = ha->flash_data_addr | ha->flash_vpd_addr;
1302 1362 } else if (flags & LNF_NVRAM_DATA) {
1303 1363 *addr = ha->flash_data_addr | ha->flash_nvram_addr;
1304 1364 } else {
1305 1365 EL(ha, "invalid 2581 option for HBA");
1306 1366 return (QL_FUNCTION_FAILED);
1307 1367 }
1308 1368
1309 1369 GLOBAL_HW_LOCK();
1310 1370 } else {
1311 1371 if ((flags & LNF_NVRAM_DATA) == 0) {
1312 1372 EL(ha, "invalid option for HBA");
1313 1373 return (QL_FUNCTION_FAILED);
1314 1374 }
1315 1375 *addr = 0;
1316 1376 GLOBAL_HW_LOCK();
1317 1377 }
1318 1378
1379 + QL_PRINT_3(ha, "done\n");
1380 +
1319 1381 return (QL_SUCCESS);
1320 1382 }
1321 1383
1322 1384 /*
1323 1385 * ql_release_nvram
1324 1386 * Releases NVRAM access.
1325 1387 *
1326 1388 * Input:
1327 1389 * ha: adapter state pointer.
1328 1390 *
1329 1391 * Context:
1330 1392 * Kernel context.
1331 1393 */
1332 1394 void
1333 1395 ql_release_nvram(ql_adapter_state_t *ha)
1334 1396 {
1397 + QL_PRINT_3(ha, "started\n");
1398 +
1335 1399 if (ha->device_id == 0x2312 || ha->device_id == 0x2322) {
1336 1400 /* Release resource lock */
1337 1401 WRT16_IO_REG(ha, host_to_host_sema, 0);
1338 1402 } else {
1339 1403 GLOBAL_HW_UNLOCK();
1340 1404 }
1405 +
1406 + QL_PRINT_3(ha, "done\n");
1341 1407 }
1342 1408
1343 1409 /*
1344 1410 * ql_23_properties
1345 1411 * Copies driver properties to NVRAM or adapter structure.
1346 1412 *
1347 1413 * Driver properties are by design global variables and hidden
1348 1414 * completely from administrators. Knowledgeable folks can
1349 1415 * override the default values using driver.conf
1350 1416 *
1351 1417 * Input:
1352 1418 * ha: adapter state pointer.
1353 - * nv: NVRAM structure pointer.
1419 + * icb: Init control block structure pointer.
1354 1420 *
1355 1421 * Context:
1356 1422 * Kernel context.
1357 1423 */
1358 1424 static void
1359 -ql_23_properties(ql_adapter_state_t *ha, nvram_t *nv)
1425 +ql_23_properties(ql_adapter_state_t *ha, ql_init_cb_t *icb)
1360 1426 {
1361 1427 uint32_t data, cnt;
1362 1428
1363 - QL_PRINT_3(CE_CONT, "(%d): started\n", ha->instance);
1429 + QL_PRINT_3(ha, "started\n");
1364 1430
1365 1431 /* Get frame payload size. */
1366 1432 if ((data = ql_get_prop(ha, "max-frame-length")) == 0xffffffff) {
1367 1433 data = 2048;
1368 1434 }
1369 1435 if (data == 512 || data == 1024 || data == 2048) {
1370 - nv->max_frame_length[0] = LSB(data);
1371 - nv->max_frame_length[1] = MSB(data);
1436 + icb->max_frame_length[0] = LSB(data);
1437 + icb->max_frame_length[1] = MSB(data);
1372 1438 } else {
1373 1439 EL(ha, "invalid parameter value for 'max-frame-length': "
1374 1440 "%d; using nvram default of %d\n", data, CHAR_TO_SHORT(
1375 - nv->max_frame_length[0], nv->max_frame_length[1]));
1441 + icb->max_frame_length[0], icb->max_frame_length[1]));
1376 1442 }
1377 1443
1378 1444 /* Get max IOCB allocation. */
1379 - nv->max_iocb_allocation[0] = 0;
1380 - nv->max_iocb_allocation[1] = 1;
1445 + icb->max_iocb_allocation[0] = 0;
1446 + icb->max_iocb_allocation[1] = 1;
1381 1447
1382 1448 /* Get execution throttle. */
1383 1449 if ((data = ql_get_prop(ha, "execution-throttle")) == 0xffffffff) {
1384 1450 data = 32;
1385 1451 }
1386 1452 if (data != 0 && data < 65536) {
1387 - nv->execution_throttle[0] = LSB(data);
1388 - nv->execution_throttle[1] = MSB(data);
1453 + icb->execution_throttle[0] = LSB(data);
1454 + icb->execution_throttle[1] = MSB(data);
1389 1455 } else {
1390 1456 EL(ha, "invalid parameter value for 'execution-throttle': "
1391 1457 "%d; using nvram default of %d\n", data, CHAR_TO_SHORT(
1392 - nv->execution_throttle[0], nv->execution_throttle[1]));
1458 + icb->execution_throttle[0], icb->execution_throttle[1]));
1393 1459 }
1394 1460
1395 1461 /* Get Login timeout. */
1396 1462 if ((data = ql_get_prop(ha, "login-timeout")) == 0xffffffff) {
1397 1463 data = 3;
1398 1464 }
1399 1465 if (data < 256) {
1400 - nv->login_timeout = (uint8_t)data;
1466 + icb->login_timeout = (uint8_t)data;
1401 1467 } else {
1402 1468 EL(ha, "invalid parameter value for 'login-timeout': "
1403 - "%d; using nvram value of %d\n", data, nv->login_timeout);
1469 + "%d; using nvram value of %d\n", data, icb->login_timeout);
1404 1470 }
1405 1471
1406 1472 /* Get retry count. */
1407 1473 if ((data = ql_get_prop(ha, "login-retry-count")) == 0xffffffff) {
1408 1474 data = 4;
1409 1475 }
1410 1476 if (data < 256) {
1411 - nv->login_retry_count = (uint8_t)data;
1477 + icb->login_retry_count = (uint8_t)data;
1412 1478 } else {
1413 1479 EL(ha, "invalid parameter value for 'login-retry-count': "
1414 1480 "%d; using nvram value of %d\n", data,
1415 - nv->login_retry_count);
1481 + icb->login_retry_count);
1416 1482 }
1417 1483
1418 1484 /* Get adapter hard loop ID enable. */
1419 - data = ql_get_prop(ha, "enable-adapter-hard-loop-ID");
1485 + data = ql_get_prop(ha, "enable-adapter-hard-loop-ID");
1420 1486 if (data == 0) {
1421 - nv->firmware_options[0] =
1422 - (uint8_t)(nv->firmware_options[0] & ~BIT_0);
1487 + icb->firmware_options[0] =
1488 + (uint8_t)(icb->firmware_options[0] & ~BIT_0);
1423 1489 } else if (data == 1) {
1424 - nv->firmware_options[0] =
1425 - (uint8_t)(nv->firmware_options[0] | BIT_0);
1490 + icb->firmware_options[0] =
1491 + (uint8_t)(icb->firmware_options[0] | BIT_0);
1426 1492 } else if (data != 0xffffffff) {
1427 1493 EL(ha, "invalid parameter value for "
1428 1494 "'enable-adapter-hard-loop-ID': %d; using nvram value "
1429 - "of %d\n", data, nv->firmware_options[0] & BIT_0 ? 1 : 0);
1495 + "of %d\n", data, icb->firmware_options[0] & BIT_0 ? 1 : 0);
1430 1496 }
1431 1497
1432 1498 /* Get adapter hard loop ID. */
1433 - data = ql_get_prop(ha, "adapter-hard-loop-ID");
1499 + data = ql_get_prop(ha, "adapter-hard-loop-ID");
1434 1500 if (data < 126) {
1435 - nv->hard_address[0] = (uint8_t)data;
1501 + icb->hard_address[0] = (uint8_t)data;
1436 1502 } else if (data != 0xffffffff) {
1437 1503 EL(ha, "invalid parameter value for 'adapter-hard-loop-ID': "
1438 1504 "%d; using nvram value of %d\n",
1439 - data, nv->hard_address[0]);
1505 + data, icb->hard_address[0]);
1440 1506 }
1441 1507
1442 1508 /* Get LIP reset. */
1443 1509 if ((data = ql_get_prop(ha, "enable-LIP-reset-on-bus-reset")) ==
1444 1510 0xffffffff) {
1445 1511 data = 0;
1446 1512 }
1447 1513 if (data == 0) {
1448 - nv->host_p[1] = (uint8_t)(nv->host_p[1] & ~BIT_1);
1514 + ha->cfg_flags &= ~CFG_ENABLE_LIP_RESET;
1449 1515 } else if (data == 1) {
1450 - nv->host_p[1] = (uint8_t)(nv->host_p[1] | BIT_1);
1516 + ha->cfg_flags |= CFG_ENABLE_LIP_RESET;
1451 1517 } else {
1452 1518 EL(ha, "invalid parameter value for "
1453 1519 "'enable-LIP-reset-on-bus-reset': %d; using nvram value "
1454 - "of %d\n", data, nv->host_p[1] & BIT_1 ? 1 : 0);
1520 + "of %d\n", data,
1521 + CFG_IST(ha, CFG_ENABLE_LIP_RESET) ? 1 : 0);
1455 1522 }
1456 1523
1457 1524 /* Get LIP full login. */
1458 1525 if ((data = ql_get_prop(ha, "enable-LIP-full-login-on-bus-reset")) ==
1459 1526 0xffffffff) {
1460 1527 data = 1;
1461 1528 }
1462 1529 if (data == 0) {
1463 - nv->host_p[1] = (uint8_t)(nv->host_p[1] & ~BIT_2);
1530 + ha->cfg_flags &= ~CFG_ENABLE_FULL_LIP_LOGIN;
1464 1531 } else if (data == 1) {
1465 - nv->host_p[1] = (uint8_t)(nv->host_p[1] | BIT_2);
1532 + ha->cfg_flags |= CFG_ENABLE_FULL_LIP_LOGIN;
1466 1533 } else {
1467 1534 EL(ha, "invalid parameter value for "
1468 1535 "'enable-LIP-full-login-on-bus-reset': %d; using nvram "
1469 - "value of %d\n", data, nv->host_p[1] & BIT_2 ? 1 : 0);
1536 + "value of %d\n", data,
1537 + CFG_IST(ha, CFG_ENABLE_FULL_LIP_LOGIN) ? 1 : 0);
1470 1538 }
1471 1539
1472 1540 /* Get target reset. */
1473 1541 if ((data = ql_get_prop(ha, "enable-target-reset-on-bus-reset")) ==
1474 1542 0xffffffff) {
1475 1543 data = 0;
1476 1544 }
1477 1545 if (data == 0) {
1478 - nv->host_p[1] = (uint8_t)(nv->host_p[1] & ~BIT_3);
1546 + ha->cfg_flags &= ~CFG_ENABLE_TARGET_RESET;
1479 1547 } else if (data == 1) {
1480 - nv->host_p[1] = (uint8_t)(nv->host_p[1] | BIT_3);
1548 + ha->cfg_flags |= CFG_ENABLE_TARGET_RESET;
1481 1549 } else {
1482 1550 EL(ha, "invalid parameter value for "
1483 1551 "'enable-target-reset-on-bus-reset': %d; using nvram "
1484 - "value of %d", data, nv->host_p[1] & BIT_3 ? 1 : 0);
1552 + "value of %d", data,
1553 + CFG_IST(ha, CFG_ENABLE_TARGET_RESET) ? 1 : 0);
1485 1554 }
1486 1555
1487 1556 /* Get reset delay. */
1488 1557 if ((data = ql_get_prop(ha, "reset-delay")) == 0xffffffff) {
1489 1558 data = 5;
1490 1559 }
1491 1560 if (data != 0 && data < 256) {
1492 - nv->reset_delay = (uint8_t)data;
1561 + ha->loop_reset_delay = (uint8_t)data;
1493 1562 } else {
1494 1563 EL(ha, "invalid parameter value for 'reset-delay': %d; "
1495 - "using nvram value of %d", data, nv->reset_delay);
1564 + "using nvram value of %d", data, ha->loop_reset_delay);
1496 1565 }
1497 1566
1498 1567 /* Get port down retry count. */
1499 1568 if ((data = ql_get_prop(ha, "port-down-retry-count")) == 0xffffffff) {
1500 1569 data = 8;
1501 1570 }
1502 1571 if (data < 256) {
1503 - nv->port_down_retry_count = (uint8_t)data;
1572 + ha->port_down_retry_count = (uint8_t)data;
1504 1573 } else {
1505 1574 EL(ha, "invalid parameter value for 'port-down-retry-count':"
1506 1575 " %d; using nvram value of %d\n", data,
1507 - nv->port_down_retry_count);
1576 + ha->port_down_retry_count);
1508 1577 }
1509 1578
1510 1579 /* Get connection mode setting. */
1511 1580 if ((data = ql_get_prop(ha, "connection-options")) == 0xffffffff) {
1512 1581 data = 2;
1513 1582 }
1514 - cnt = CFG_IST(ha, CFG_CTRL_2200) ? 3 : 2;
1583 + cnt = CFG_IST(ha, CFG_CTRL_22XX) ? 3 : 2;
1515 1584 if (data <= cnt) {
1516 - nv->add_fw_opt[0] = (uint8_t)(nv->add_fw_opt[0] &
1585 + icb->add_fw_opt[0] = (uint8_t)(icb->add_fw_opt[0] &
1517 1586 ~(BIT_6 | BIT_5 | BIT_4));
1518 - nv->add_fw_opt[0] = (uint8_t)(nv->add_fw_opt[0] |
1587 + icb->add_fw_opt[0] = (uint8_t)(icb->add_fw_opt[0] |
1519 1588 (uint8_t)(data << 4));
1520 1589 } else {
1521 1590 EL(ha, "invalid parameter value for 'connection-options': "
1522 1591 "%d; using nvram value of %d\n", data,
1523 - (nv->add_fw_opt[0] >> 4) & 0x3);
1592 + (icb->add_fw_opt[0] >> 4) & 0x3);
1524 1593 }
1525 1594
1526 1595 /* Get data rate setting. */
1527 - if ((CFG_IST(ha, CFG_CTRL_2200)) == 0) {
1596 + if ((CFG_IST(ha, CFG_CTRL_22XX)) == 0) {
1528 1597 if ((data = ql_get_prop(ha, "fc-data-rate")) == 0xffffffff) {
1529 1598 data = 2;
1530 1599 }
1531 1600 if (data < 3) {
1532 - nv->special_options[1] = (uint8_t)
1533 - (nv->special_options[1] & 0x3f);
1534 - nv->special_options[1] = (uint8_t)
1535 - (nv->special_options[1] | (uint8_t)(data << 6));
1601 + icb->special_options[1] = (uint8_t)
1602 + (icb->special_options[1] & 0x3f);
1603 + icb->special_options[1] = (uint8_t)
1604 + (icb->special_options[1] | (uint8_t)(data << 6));
1536 1605 } else {
1537 1606 EL(ha, "invalid parameter value for 'fc-data-rate': "
1538 1607 "%d; using nvram value of %d\n", data,
1539 - (nv->special_options[1] >> 6) & 0x3);
1608 + (icb->special_options[1] >> 6) & 0x3);
1540 1609 }
1541 1610 }
1542 1611
1543 - /* Get adapter id string for Sun branded 23xx only */
1544 - if ((CFG_IST(ha, CFG_CTRL_2300)) && nv->adapInfo[0] != 0) {
1545 - (void) snprintf((int8_t *)ha->adapInfo, 16, "%s",
1546 - nv->adapInfo);
1547 - }
1548 -
1549 1612 /* Get IP FW container count. */
1550 1613 ha->ip_init_ctrl_blk.cb.cc[0] = LSB(ql_ip_buffer_count);
1551 1614 ha->ip_init_ctrl_blk.cb.cc[1] = MSB(ql_ip_buffer_count);
1552 1615
1553 1616 /* Get IP low water mark. */
1554 1617 ha->ip_init_ctrl_blk.cb.low_water_mark[0] = LSB(ql_ip_low_water);
1555 1618 ha->ip_init_ctrl_blk.cb.low_water_mark[1] = MSB(ql_ip_low_water);
1556 1619
1557 1620 /* Get IP fast register post count. */
1558 1621 ha->ip_init_ctrl_blk.cb.fast_post_reg_count[0] =
1559 1622 ql_ip_fast_post_count;
1560 1623
1561 1624 ADAPTER_STATE_LOCK(ha);
1562 1625
1563 1626 ql_common_properties(ha);
1564 1627
1565 1628 ADAPTER_STATE_UNLOCK(ha);
1566 1629
1567 - QL_PRINT_3(CE_CONT, "(%d): done\n", ha->instance);
1630 + QL_PRINT_3(ha, "done\n");
1568 1631 }
1569 1632
1570 1633 /*
1571 1634 * ql_common_properties
1572 1635 * Driver properties adapter structure.
1573 1636 *
1574 1637 * Driver properties are by design global variables and hidden
1575 1638 * completely from administrators. Knowledgeable folks can
1576 1639 * override the default values using driver.conf
1577 1640 *
1578 1641 * Input:
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1579 1642 * ha: adapter state pointer.
1580 1643 *
1581 1644 * Context:
1582 1645 * Kernel context.
1583 1646 */
1584 1647 void
1585 1648 ql_common_properties(ql_adapter_state_t *ha)
1586 1649 {
1587 1650 uint32_t data;
1588 1651
1589 - QL_PRINT_3(CE_CONT, "(%d): started\n", ha->instance);
1652 + QL_PRINT_10(ha, "started\n");
1590 1653
1591 - /* Get extended logging trace buffer size. */
1592 - if ((data = ql_get_prop(ha, "set-ext-log-buffer-size")) !=
1593 - 0xffffffff && data != 0) {
1594 - char *new_trace;
1595 - uint32_t new_size;
1596 -
1597 - if (ha->el_trace_desc->trace_buffer != NULL) {
1598 - new_size = 1024 * data;
1599 - new_trace = (char *)kmem_zalloc(new_size, KM_SLEEP);
1600 -
1601 - if (new_trace == NULL) {
1602 - cmn_err(CE_WARN, "%s(%d): can't get new"
1603 - " trace buffer",
1604 - QL_NAME, ha->instance);
1605 - } else {
1606 - /* free the previous */
1607 - kmem_free(ha->el_trace_desc->trace_buffer,
1608 - ha->el_trace_desc->trace_buffer_size);
1609 - /* Use the new one */
1610 - ha->el_trace_desc->trace_buffer = new_trace;
1611 - ha->el_trace_desc->trace_buffer_size = new_size;
1612 - }
1613 - }
1614 -
1615 - }
1616 -
1617 1654 /* Get extended logging enable. */
1618 1655 if ((data = ql_get_prop(ha, "extended-logging")) == 0xffffffff ||
1619 1656 data == 0) {
1620 1657 ha->cfg_flags &= ~CFG_ENABLE_EXTENDED_LOGGING;
1621 1658 } else if (data == 1) {
1622 1659 ha->cfg_flags |= CFG_ENABLE_EXTENDED_LOGGING;
1623 1660 } else {
1624 1661 EL(ha, "invalid parameter value for 'extended-logging': %d;"
1625 1662 " using default value of 0\n", data);
1626 1663 ha->cfg_flags &= ~CFG_ENABLE_EXTENDED_LOGGING;
1627 1664 }
1628 1665
1629 - /* Get extended logging trace disable. */
1630 - if ((data = ql_get_prop(ha, "disable-extended-logging-trace")) ==
1631 - 0xffffffff || data == 0) {
1632 - ha->cfg_flags &= ~CFG_DISABLE_EXTENDED_LOGGING_TRACE;
1633 - } else if (data == 1) {
1634 - ha->cfg_flags |= CFG_DISABLE_EXTENDED_LOGGING_TRACE;
1635 - } else {
1636 - EL(ha, "invalid parameter value for "
1637 - "'disable-extended-logging-trace': %d;"
1638 - " using default value of 0\n", data);
1639 - ha->cfg_flags &= ~CFG_DISABLE_EXTENDED_LOGGING_TRACE;
1640 - }
1641 -
1642 1666 /* Get FCP 2 Error Recovery. */
1643 1667 if ((data = ql_get_prop(ha, "enable-FCP-2-error-recovery")) ==
1644 1668 0xffffffff || data == 1) {
1645 1669 ha->cfg_flags |= CFG_ENABLE_FCP_2_SUPPORT;
1646 1670 } else if (data == 0) {
1647 1671 ha->cfg_flags &= ~CFG_ENABLE_FCP_2_SUPPORT;
1648 1672 } else {
1649 1673 EL(ha, "invalid parameter value for "
1650 1674 "'enable-FCP-2-error-recovery': %d; using nvram value of "
1651 1675 "1\n", data);
1652 1676 ha->cfg_flags |= CFG_ENABLE_FCP_2_SUPPORT;
1653 1677 }
1654 1678
1655 1679 #ifdef QL_DEBUG_LEVEL_2
1656 1680 ha->cfg_flags |= CFG_ENABLE_EXTENDED_LOGGING;
1657 1681 #endif
1658 1682
1659 1683 /* Get port down retry delay. */
1660 1684 if ((data = ql_get_prop(ha, "port-down-retry-delay")) == 0xffffffff) {
1661 1685 ha->port_down_retry_delay = PORT_RETRY_TIME;
1662 1686 } else if (data < 256) {
1663 1687 ha->port_down_retry_delay = (uint8_t)data;
1664 1688 } else {
1665 1689 EL(ha, "invalid parameter value for 'port-down-retry-delay':"
1666 1690 " %d; using default value of %d", data, PORT_RETRY_TIME);
1667 1691 ha->port_down_retry_delay = PORT_RETRY_TIME;
1668 1692 }
1669 1693
1670 1694 /* Get queue full retry count. */
1671 1695 if ((data = ql_get_prop(ha, "queue-full-retry-count")) == 0xffffffff) {
1672 1696 ha->qfull_retry_count = 16;
1673 1697 } else if (data < 256) {
1674 1698 ha->qfull_retry_count = (uint8_t)data;
1675 1699 } else {
1676 1700 EL(ha, "invalid parameter value for 'queue-full-retry-count':"
1677 1701 " %d; using default value of 16", data);
1678 1702 ha->qfull_retry_count = 16;
1679 1703 }
1680 1704
1681 1705 /* Get queue full retry delay. */
1682 1706 if ((data = ql_get_prop(ha, "queue-full-retry-delay")) == 0xffffffff) {
1683 1707 ha->qfull_retry_delay = PORT_RETRY_TIME;
1684 1708 } else if (data < 256) {
1685 1709 ha->qfull_retry_delay = (uint8_t)data;
1686 1710 } else {
1687 1711 EL(ha, "invalid parameter value for 'queue-full-retry-delay':"
1688 1712 " %d; using default value of %d", data, PORT_RETRY_TIME);
1689 1713 ha->qfull_retry_delay = PORT_RETRY_TIME;
1690 1714 }
1691 1715
1692 1716 /* Get loop down timeout. */
1693 1717 if ((data = ql_get_prop(ha, "link-down-timeout")) == 0xffffffff) {
1694 1718 data = 0;
1695 1719 } else if (data > 255) {
1696 1720 EL(ha, "invalid parameter value for 'link-down-timeout': %d;"
1697 1721 " using nvram value of 0\n", data);
1698 1722 data = 0;
1699 1723 }
1700 1724 ha->loop_down_abort_time = (uint8_t)(LOOP_DOWN_TIMER_START - data);
1701 1725 if (ha->loop_down_abort_time == LOOP_DOWN_TIMER_START) {
1702 1726 ha->loop_down_abort_time--;
1703 1727 } else if (ha->loop_down_abort_time <= LOOP_DOWN_TIMER_END) {
1704 1728 ha->loop_down_abort_time = LOOP_DOWN_TIMER_END + 1;
1705 1729 }
1706 1730
1707 1731 /* Get link down error enable. */
1708 1732 if ((data = ql_get_prop(ha, "enable-link-down-error")) == 0xffffffff ||
1709 1733 data == 1) {
1710 1734 ha->cfg_flags |= CFG_ENABLE_LINK_DOWN_REPORTING;
1711 1735 } else if (data == 0) {
1712 1736 ha->cfg_flags &= ~CFG_ENABLE_LINK_DOWN_REPORTING;
1713 1737 } else {
1714 1738 EL(ha, "invalid parameter value for 'link-down-error': %d;"
1715 1739 " using default value of 1\n", data);
1716 1740 }
1717 1741
1718 1742 /*
1719 1743 * Get firmware dump flags.
1720 1744 * TAKE_FW_DUMP_ON_MAILBOX_TIMEOUT BIT_0
1721 1745 * TAKE_FW_DUMP_ON_ISP_SYSTEM_ERROR BIT_1
1722 1746 * TAKE_FW_DUMP_ON_DRIVER_COMMAND_TIMEOUT BIT_2
1723 1747 * TAKE_FW_DUMP_ON_LOOP_OFFLINE_TIMEOUT BIT_3
1724 1748 */
1725 1749 ha->cfg_flags &= ~(CFG_DUMP_MAILBOX_TIMEOUT |
1726 1750 CFG_DUMP_ISP_SYSTEM_ERROR | CFG_DUMP_DRIVER_COMMAND_TIMEOUT |
1727 1751 CFG_DUMP_LOOP_OFFLINE_TIMEOUT);
1728 1752 if ((data = ql_get_prop(ha, "firmware-dump-flags")) != 0xffffffff) {
1729 1753 if (data & BIT_0) {
1730 1754 ha->cfg_flags |= CFG_DUMP_MAILBOX_TIMEOUT;
1731 1755 }
1732 1756 if (data & BIT_1) {
1733 1757 ha->cfg_flags |= CFG_DUMP_ISP_SYSTEM_ERROR;
1734 1758 }
1735 1759 if (data & BIT_2) {
1736 1760 ha->cfg_flags |= CFG_DUMP_DRIVER_COMMAND_TIMEOUT;
1737 1761 }
1738 1762 if (data & BIT_3) {
1739 1763 ha->cfg_flags |= CFG_DUMP_LOOP_OFFLINE_TIMEOUT;
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1740 1764 }
1741 1765 }
1742 1766
1743 1767 /* Get the PCI max read request size override. */
1744 1768 ha->pci_max_read_req = 0;
1745 1769 if ((data = ql_get_prop(ha, "pci-max-read-request")) != 0xffffffff &&
1746 1770 data != 0) {
1747 1771 ha->pci_max_read_req = (uint16_t)(data);
1748 1772 }
1749 1773
1774 + /* Get the plogi retry params overrides. */
1775 + if ((data = ql_get_prop(ha, "plogi_params_retry_count")) !=
1776 + 0xffffffff && data != 0) {
1777 + ha->plogi_params->retry_cnt = (uint32_t)(data);
1778 + }
1779 + if ((data = ql_get_prop(ha, "plogi_params_retry_delay")) !=
1780 + 0xffffffff && data != 0) {
1781 + ha->plogi_params->retry_dly_usec = (uint32_t)(data);
1782 + }
1783 +
1750 1784 /*
1751 1785 * Set default fw wait, adjusted for slow FCF's.
1752 1786 * Revisit when FCF's as fast as FC switches.
1753 1787 */
1754 - ha->fwwait = (uint8_t)(CFG_IST(ha, CFG_CTRL_8081) ? 45 : 10);
1788 + ha->fwwait = (uint8_t)(CFG_IST(ha, CFG_FCOE_SUPPORT) ? 45 : 10);
1755 1789 /* Get the attach fw_ready override value. */
1756 1790 if ((data = ql_get_prop(ha, "init-loop-sync-wait")) != 0xffffffff) {
1757 1791 if (data > 0 && data <= 240) {
1758 1792 ha->fwwait = (uint8_t)data;
1759 1793 } else {
1760 1794 EL(ha, "invalid parameter value for "
1761 1795 "'init-loop-sync-wait': %d; using default "
1762 1796 "value of %d\n", data, ha->fwwait);
1763 1797 }
1764 1798 }
1765 1799
1766 - QL_PRINT_3(CE_CONT, "(%d): done\n", ha->instance);
1800 + /* Get fm-capable property */
1801 + ha->fm_capabilities = DDI_FM_NOT_CAPABLE;
1802 + if ((data = ql_get_prop(ha, "fm-capable")) != 0xffffffff) {
1803 + if (data == 0) {
1804 + ha->fm_capabilities = DDI_FM_NOT_CAPABLE;
1805 + } else if (data > 0xf) {
1806 + ha->fm_capabilities = 0xf;
1807 +
1808 + } else {
1809 + ha->fm_capabilities = (int)(data);
1810 + }
1811 + } else {
1812 + ha->fm_capabilities = (int)(DDI_FM_EREPORT_CAPABLE
1813 + | DDI_FM_ERRCB_CAPABLE);
1814 + }
1815 +
1816 + if ((data = ql_get_prop(ha, "msix-vectors")) == 0xffffffff) {
1817 + ha->mq_msix_vectors = 0;
1818 + } else if (data < 256) {
1819 + ha->mq_msix_vectors = (uint8_t)data;
1820 + } else {
1821 + EL(ha, "invalid parameter value for 'msix-vectors': "
1822 + "%d; using value of %d\n", data, 0);
1823 + ha->mq_msix_vectors = 0;
1824 + }
1825 +
1826 + /* Get number of completion threads. */
1827 + if ((data = ql_get_prop(ha, "completion-threads")) == 0xffffffff) {
1828 + ha->completion_thds = 4;
1829 + } else if (data < 256 && data >= 1) {
1830 + ha->completion_thds = (uint8_t)data;
1831 + } else {
1832 + EL(ha, "invalid parameter value for 'completion-threads':"
1833 + " %d; using default value of %d", data, 4);
1834 + ha->completion_thds = 4;
1835 + }
1836 +
1837 + QL_PRINT_3(ha, "done\n");
1767 1838 }
1768 1839
1769 1840 /*
1770 1841 * ql_24xx_properties
1771 1842 * Copies driver properties to NVRAM or adapter structure.
1772 1843 *
1773 1844 * Driver properties are by design global variables and hidden
1774 1845 * completely from administrators. Knowledgeable folks can
1775 1846 * override the default values using /etc/system.
1776 1847 *
1777 1848 * Input:
1778 1849 * ha: adapter state pointer.
1779 - * nv: NVRAM structure pointer.
1850 + * icb: Init control block structure pointer.
1780 1851 *
1781 1852 * Context:
1782 1853 * Kernel context.
1783 1854 */
1784 1855 static void
1785 -ql_24xx_properties(ql_adapter_state_t *ha, nvram_24xx_t *nv)
1856 +ql_24xx_properties(ql_adapter_state_t *ha, ql_init_24xx_cb_t *icb)
1786 1857 {
1787 1858 uint32_t data;
1788 1859
1789 - QL_PRINT_3(CE_CONT, "(%d): started\n", ha->instance);
1860 + QL_PRINT_10(ha, "started\n");
1790 1861
1791 1862 /* Get frame size */
1792 1863 if ((data = ql_get_prop(ha, "max-frame-length")) == 0xffffffff) {
1793 1864 data = 2048;
1794 1865 }
1795 1866 if (data == 512 || data == 1024 || data == 2048 || data == 2112) {
1796 - nv->max_frame_length[0] = LSB(data);
1797 - nv->max_frame_length[1] = MSB(data);
1867 + icb->max_frame_length[0] = LSB(data);
1868 + icb->max_frame_length[1] = MSB(data);
1798 1869 } else {
1799 1870 EL(ha, "invalid parameter value for 'max-frame-length': %d;"
1800 1871 " using nvram default of %d\n", data, CHAR_TO_SHORT(
1801 - nv->max_frame_length[0], nv->max_frame_length[1]));
1872 + icb->max_frame_length[0], icb->max_frame_length[1]));
1802 1873 }
1803 1874
1804 1875 /* Get execution throttle. */
1805 1876 if ((data = ql_get_prop(ha, "execution-throttle")) == 0xffffffff) {
1806 1877 data = 32;
1807 1878 }
1808 1879 if (data != 0 && data < 65536) {
1809 - nv->execution_throttle[0] = LSB(data);
1810 - nv->execution_throttle[1] = MSB(data);
1880 + icb->execution_throttle[0] = LSB(data);
1881 + icb->execution_throttle[1] = MSB(data);
1811 1882 } else {
1812 1883 EL(ha, "invalid parameter value for 'execution-throttle':"
1813 1884 " %d; using nvram default of %d\n", data, CHAR_TO_SHORT(
1814 - nv->execution_throttle[0], nv->execution_throttle[1]));
1885 + icb->execution_throttle[0], icb->execution_throttle[1]));
1815 1886 }
1816 1887
1817 1888 /* Get Login timeout. */
1818 1889 if ((data = ql_get_prop(ha, "login-timeout")) == 0xffffffff) {
1819 1890 data = 3;
1820 1891 }
1821 1892 if (data < 65536) {
1822 - nv->login_timeout[0] = LSB(data);
1823 - nv->login_timeout[1] = MSB(data);
1893 + icb->login_timeout[0] = LSB(data);
1894 + icb->login_timeout[1] = MSB(data);
1824 1895 } else {
1825 1896 EL(ha, "invalid parameter value for 'login-timeout': %d; "
1826 1897 "using nvram value of %d\n", data, CHAR_TO_SHORT(
1827 - nv->login_timeout[0], nv->login_timeout[1]));
1898 + icb->login_timeout[0], icb->login_timeout[1]));
1828 1899 }
1829 1900
1830 1901 /* Get retry count. */
1831 1902 if ((data = ql_get_prop(ha, "login-retry-count")) == 0xffffffff) {
1832 1903 data = 4;
1833 1904 }
1834 1905 if (data < 65536) {
1835 - nv->login_retry_count[0] = LSB(data);
1836 - nv->login_retry_count[1] = MSB(data);
1906 + icb->login_retry_count[0] = LSB(data);
1907 + icb->login_retry_count[1] = MSB(data);
1837 1908 } else {
1838 1909 EL(ha, "invalid parameter value for 'login-retry-count': "
1839 1910 "%d; using nvram value of %d\n", data, CHAR_TO_SHORT(
1840 - nv->login_retry_count[0], nv->login_retry_count[1]));
1911 + icb->login_retry_count[0], icb->login_retry_count[1]));
1841 1912 }
1842 1913
1843 1914 /* Get adapter hard loop ID enable. */
1844 - data = ql_get_prop(ha, "enable-adapter-hard-loop-ID");
1915 + data = ql_get_prop(ha, "enable-adapter-hard-loop-ID");
1845 1916 if (data == 0) {
1846 - nv->firmware_options_1[0] =
1847 - (uint8_t)(nv->firmware_options_1[0] & ~BIT_0);
1917 + icb->firmware_options_1[0] =
1918 + (uint8_t)(icb->firmware_options_1[0] & ~BIT_0);
1848 1919 } else if (data == 1) {
1849 - nv->firmware_options_1[0] =
1850 - (uint8_t)(nv->firmware_options_1[0] | BIT_0);
1920 + icb->firmware_options_1[0] =
1921 + (uint8_t)(icb->firmware_options_1[0] | BIT_0);
1851 1922 } else if (data != 0xffffffff) {
1852 1923 EL(ha, "invalid parameter value for "
1853 1924 "'enable-adapter-hard-loop-ID': %d; using nvram value "
1854 1925 "of %d\n", data,
1855 - nv->firmware_options_1[0] & BIT_0 ? 1 : 0);
1926 + icb->firmware_options_1[0] & BIT_0 ? 1 : 0);
1856 1927 }
1857 1928
1858 1929 /* Get adapter hard loop ID. */
1859 - data = ql_get_prop(ha, "adapter-hard-loop-ID");
1930 + data = ql_get_prop(ha, "adapter-hard-loop-ID");
1860 1931 if (data < 126) {
1861 - nv->hard_address[0] = LSB(data);
1862 - nv->hard_address[1] = MSB(data);
1932 + icb->hard_address[0] = LSB(data);
1933 + icb->hard_address[1] = MSB(data);
1863 1934 } else if (data != 0xffffffff) {
1864 1935 EL(ha, "invalid parameter value for 'adapter-hard-loop-ID':"
1865 1936 " %d; using nvram value of %d\n", data, CHAR_TO_SHORT(
1866 - nv->hard_address[0], nv->hard_address[1]));
1937 + icb->hard_address[0], icb->hard_address[1]));
1867 1938 }
1868 1939
1869 1940 /* Get LIP reset. */
1870 1941 if ((data = ql_get_prop(ha, "enable-LIP-reset-on-bus-reset")) ==
1871 1942 0xffffffff) {
1872 1943 data = 0;
1873 1944 }
1874 1945 if (data == 0) {
1875 1946 ha->cfg_flags &= ~CFG_ENABLE_LIP_RESET;
1876 1947 } else if (data == 1) {
1877 1948 ha->cfg_flags |= CFG_ENABLE_LIP_RESET;
1878 1949 } else {
1879 1950 EL(ha, "invalid parameter value for "
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1880 1951 "'enable-LIP-reset-on-bus-reset': %d; using value of 0\n",
1881 1952 data);
1882 1953 }
1883 1954
1884 1955 /* Get LIP full login. */
1885 1956 if ((data = ql_get_prop(ha, "enable-LIP-full-login-on-bus-reset")) ==
1886 1957 0xffffffff) {
1887 1958 data = 1;
1888 1959 }
1889 1960 if (data == 0) {
1890 - nv->host_p[1] = (uint8_t)(nv->host_p[1] & ~BIT_2);
1961 + ha->cfg_flags &= ~CFG_ENABLE_FULL_LIP_LOGIN;
1891 1962 } else if (data == 1) {
1892 - nv->host_p[1] = (uint8_t)(nv->host_p[1] | BIT_2);
1963 + ha->cfg_flags |= CFG_ENABLE_FULL_LIP_LOGIN;
1893 1964 } else {
1894 1965 EL(ha, "invalid parameter value for "
1895 1966 "'enable-LIP-full-login-on-bus-reset': %d; using nvram "
1896 - "value of %d\n", data, nv->host_p[1] & BIT_2 ? 1 : 0);
1967 + "value of %d\n", data,
1968 + ha->cfg_flags & CFG_ENABLE_FULL_LIP_LOGIN ? 1 : 0);
1897 1969 }
1898 1970
1899 1971 /* Get target reset. */
1900 1972 if ((data = ql_get_prop(ha, "enable-target-reset-on-bus-reset")) ==
1901 1973 0xffffffff) {
1902 1974 data = 0;
1903 1975 }
1904 1976 if (data == 0) {
1905 - nv->host_p[1] = (uint8_t)(nv->host_p[1] & ~BIT_3);
1977 + ha->cfg_flags &= ~CFG_ENABLE_TARGET_RESET;
1906 1978 } else if (data == 1) {
1907 - nv->host_p[1] = (uint8_t)(nv->host_p[1] | BIT_3);
1979 + ha->cfg_flags |= CFG_ENABLE_TARGET_RESET;
1908 1980 } else {
1909 1981 EL(ha, "invalid parameter value for "
1910 1982 "'enable-target-reset-on-bus-reset': %d; using nvram "
1911 - "value of %d", data, nv->host_p[1] & BIT_3 ? 1 : 0);
1983 + "value of %d", data,
1984 + ha->cfg_flags & CFG_ENABLE_TARGET_RESET ? 1 : 0);
1912 1985 }
1913 1986
1914 1987 /* Get reset delay. */
1915 1988 if ((data = ql_get_prop(ha, "reset-delay")) == 0xffffffff) {
1916 1989 data = 5;
1917 1990 }
1918 1991 if (data != 0 && data < 256) {
1919 - nv->reset_delay = (uint8_t)data;
1992 + ha->loop_reset_delay = (uint8_t)data;
1920 1993 } else {
1921 1994 EL(ha, "invalid parameter value for 'reset-delay': %d; "
1922 - "using nvram value of %d", data, nv->reset_delay);
1995 + "using nvram value of %d", data, ha->loop_reset_delay);
1923 1996 }
1924 1997
1925 1998 /* Get port down retry count. */
1926 1999 if ((data = ql_get_prop(ha, "port-down-retry-count")) == 0xffffffff) {
1927 2000 data = 8;
1928 2001 }
1929 2002 if (data < 256) {
1930 - nv->port_down_retry_count[0] = LSB(data);
1931 - nv->port_down_retry_count[1] = MSB(data);
2003 + ha->port_down_retry_count = (uint16_t)data;
1932 2004 } else {
1933 2005 EL(ha, "invalid parameter value for 'port-down-retry-count':"
1934 - " %d; using nvram value of %d\n", data, CHAR_TO_SHORT(
1935 - nv->port_down_retry_count[0],
1936 - nv->port_down_retry_count[1]));
2006 + " %d; using nvram value of %d\n", data,
2007 + ha->port_down_retry_count);
1937 2008 }
1938 2009
1939 - if (!(CFG_IST(ha, CFG_CTRL_8081))) {
2010 + if (!(CFG_IST(ha, CFG_FCOE_SUPPORT))) {
2011 + uint32_t conn;
2012 +
1940 2013 /* Get connection mode setting. */
1941 - if ((data = ql_get_prop(ha, "connection-options")) ==
2014 + if ((conn = ql_get_prop(ha, "connection-options")) ==
1942 2015 0xffffffff) {
1943 - data = 2;
2016 + conn = 2;
1944 2017 }
1945 - if (data <= 2) {
1946 - nv->firmware_options_2[0] = (uint8_t)
1947 - (nv->firmware_options_2[0] &
2018 + if (conn <= 2) {
2019 + icb->firmware_options_2[0] = (uint8_t)
2020 + (icb->firmware_options_2[0] &
1948 2021 ~(BIT_6 | BIT_5 | BIT_4));
1949 - nv->firmware_options_2[0] = (uint8_t)
1950 - (nv->firmware_options_2[0] | (uint8_t)(data << 4));
2022 + icb->firmware_options_2[0] = (uint8_t)
2023 + (icb->firmware_options_2[0] | (uint8_t)(conn << 4));
1951 2024 } else {
1952 2025 EL(ha, "invalid parameter value for 'connection-"
1953 - "options': %d; using nvram value of %d\n", data,
1954 - (nv->firmware_options_2[0] >> 4) & 0x3);
2026 + "options': %d; using nvram value of %d\n", conn,
2027 + (icb->firmware_options_2[0] >> 4) & 0x3);
1955 2028 }
2029 + conn = icb->firmware_options_2[0] >> 4 & 0x3;
2030 + if (conn == 0 && ha->max_vports > 125) {
2031 + ha->max_vports = 125;
2032 + }
1956 2033
1957 2034 /* Get data rate setting. */
1958 2035 if ((data = ql_get_prop(ha, "fc-data-rate")) == 0xffffffff) {
1959 2036 data = 2;
1960 2037 }
1961 - if ((CFG_IST(ha, CFG_CTRL_2422) && data < 4) ||
1962 - (CFG_IST(ha, CFG_CTRL_258081) && data < 5)) {
1963 - nv->firmware_options_3[1] = (uint8_t)
1964 - (nv->firmware_options_3[1] & 0x1f);
1965 - nv->firmware_options_3[1] = (uint8_t)
1966 - (nv->firmware_options_3[1] | (uint8_t)(data << 5));
2038 + if ((CFG_IST(ha, CFG_CTRL_24XX) && data < 4) ||
2039 + (CFG_IST(ha, CFG_CTRL_25XX) && data < 5) ||
2040 + (CFG_IST(ha, CFG_CTRL_2783) && data < 6)) {
2041 + if (CFG_IST(ha, CFG_CTRL_2783) && data == 5 &&
2042 + conn == 0) {
2043 + EL(ha, "invalid parameter value for 'fc-data-"
2044 + "rate': %d; using nvram value of %d\n",
2045 + data, 2);
2046 + data = 2;
2047 + }
2048 + icb->firmware_options_3[1] = (uint8_t)
2049 + (icb->firmware_options_3[1] & 0x1f);
2050 + icb->firmware_options_3[1] = (uint8_t)
2051 + (icb->firmware_options_3[1] | (uint8_t)(data << 5));
1967 2052 } else {
1968 2053 EL(ha, "invalid parameter value for 'fc-data-rate': "
1969 2054 "%d; using nvram value of %d\n", data,
1970 - (nv->firmware_options_3[1] >> 5) & 0x7);
2055 + (icb->firmware_options_3[1] >> 5) & 0x7);
1971 2056 }
1972 2057 }
1973 2058
1974 2059 /* Get IP FW container count. */
1975 2060 ha->ip_init_ctrl_blk.cb24.cc[0] = LSB(ql_ip_buffer_count);
1976 2061 ha->ip_init_ctrl_blk.cb24.cc[1] = MSB(ql_ip_buffer_count);
1977 2062
1978 2063 /* Get IP low water mark. */
1979 2064 ha->ip_init_ctrl_blk.cb24.low_water_mark[0] = LSB(ql_ip_low_water);
1980 2065 ha->ip_init_ctrl_blk.cb24.low_water_mark[1] = MSB(ql_ip_low_water);
1981 2066
1982 2067 ADAPTER_STATE_LOCK(ha);
1983 2068
1984 2069 /* Get enable flash load. */
1985 2070 if ((data = ql_get_prop(ha, "enable-flash-load")) == 0xffffffff ||
1986 2071 data == 0) {
1987 2072 ha->cfg_flags &= ~CFG_LOAD_FLASH_FW;
1988 2073 } else if (data == 1) {
1989 2074 ha->cfg_flags |= CFG_LOAD_FLASH_FW;
1990 2075 } else {
1991 2076 EL(ha, "invalid parameter value for 'enable-flash-load': "
1992 2077 "%d; using default value of 0\n", data);
1993 2078 }
1994 2079
1995 2080 /* Enable firmware extended tracing */
1996 2081 if ((data = ql_get_prop(ha, "enable-fwexttrace")) != 0xffffffff) {
1997 2082 if (data != 0) {
1998 2083 ha->cfg_flags |= CFG_ENABLE_FWEXTTRACE;
1999 2084 }
2000 2085 }
2001 2086
2002 2087 /* Enable firmware fc tracing */
2003 2088 if ((data = ql_get_prop(ha, "enable-fwfcetrace")) != 0xffffffff) {
2004 2089 ha->cfg_flags |= CFG_ENABLE_FWFCETRACE;
2005 2090 ha->fwfcetraceopt = data;
2006 2091 }
2007 2092
2008 2093 /* Enable fast timeout */
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2009 2094 if ((data = ql_get_prop(ha, "enable-fasttimeout")) != 0xffffffff) {
2010 2095 if (data != 0) {
2011 2096 ha->cfg_flags |= CFG_FAST_TIMEOUT;
2012 2097 }
2013 2098 }
2014 2099
2015 2100 ql_common_properties(ha);
2016 2101
2017 2102 ADAPTER_STATE_UNLOCK(ha);
2018 2103
2019 - QL_PRINT_3(CE_CONT, "(%d): done\n", ha->instance);
2104 + QL_PRINT_3(ha, "done\n");
2020 2105 }
2021 2106
2022 2107 /*
2023 2108 * ql_get_prop
2024 2109 * Get property value from configuration file.
2025 2110 *
2026 2111 * Input:
2027 2112 * ha= adapter state pointer.
2028 2113 * string = property string pointer.
2029 2114 *
2030 2115 * Returns:
2031 2116 * 0xFFFFFFFF = no property else property value.
2032 2117 *
2033 2118 * Context:
2034 2119 * Kernel context.
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2035 2120 */
2036 2121 uint32_t
2037 2122 ql_get_prop(ql_adapter_state_t *ha, char *string)
2038 2123 {
2039 2124 char buf[256];
2040 2125 uint32_t data = 0xffffffff;
2041 2126
2042 2127 /*
2043 2128 * Look for a adapter instance NPIV (virtual port) specific parameter
2044 2129 */
2045 - if (CFG_IST(ha, CFG_CTRL_24258081)) {
2130 + if (CFG_IST(ha, CFG_ISP_FW_TYPE_2)) {
2046 2131 (void) sprintf(buf, "hba%d-vp%d-%s", ha->instance,
2047 2132 ha->vp_index, string);
2048 2133 /*LINTED [Solaris DDI_DEV_T_ANY Lint warning]*/
2049 2134 data = (uint32_t)ddi_prop_get_int(DDI_DEV_T_ANY, ha->dip, 0,
2050 2135 buf, (int)0xffffffff);
2051 2136 }
2052 2137
2053 2138 /*
2054 2139 * Get adapter instance parameter if a vp specific one isn't found.
2055 2140 */
2056 2141 if (data == 0xffffffff) {
2057 2142 (void) sprintf(buf, "hba%d-%s", ha->instance, string);
2058 2143 /*LINTED [Solaris DDI_DEV_T_ANY Lint warning]*/
2059 2144 data = (uint32_t)ddi_prop_get_int(DDI_DEV_T_ANY, ha->dip,
2060 2145 0, buf, (int)0xffffffff);
2061 2146 }
2062 2147
2063 2148 /* Adapter instance parameter found? */
2064 2149 if (data == 0xffffffff) {
2065 2150 /* No, get default parameter. */
2066 2151 /*LINTED [Solaris DDI_DEV_T_ANY Lint warning]*/
2067 2152 data = (uint32_t)ddi_prop_get_int(DDI_DEV_T_ANY, ha->dip, 0,
2068 2153 string, (int)0xffffffff);
2069 2154 }
2070 2155
2071 2156 return (data);
2072 2157 }
2073 2158
2074 2159 /*
2075 2160 * ql_check_isp_firmware
2076 2161 * Checks if using already loaded RISC code or drivers copy.
2077 2162 * If using already loaded code, save a copy of it.
2078 2163 *
2079 2164 * Input:
2080 2165 * ha = adapter state pointer.
2081 2166 *
2082 2167 * Returns:
2083 2168 * ql local function return status code.
2084 2169 *
2085 2170 * Context:
2086 2171 * Kernel context.
2087 2172 */
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2088 2173 static int
2089 2174 ql_check_isp_firmware(ql_adapter_state_t *ha)
2090 2175 {
2091 2176 int rval;
2092 2177 uint16_t word_count;
2093 2178 uint32_t byte_count;
2094 2179 uint32_t fw_size, *lptr;
2095 2180 caddr_t bufp;
2096 2181 uint16_t risc_address = (uint16_t)ha->risc_fw[0].addr;
2097 2182
2098 - QL_PRINT_3(CE_CONT, "(%d): started\n", ha->instance);
2183 + QL_PRINT_10(ha, "started\n");
2099 2184
2100 2185 /* Test for firmware running. */
2101 - if (CFG_IST(ha, CFG_CTRL_8021)) {
2102 - if (ql_8021_idc_handler(ha) != NX_DEV_READY) {
2186 + if (CFG_IST(ha, CFG_CTRL_82XX)) {
2187 + if ((rval = ql_8021_fw_chk(ha)) == QL_SUCCESS) {
2188 + rval = ql_start_firmware(ha);
2189 + }
2190 + } else if (CFG_IST(ha, CFG_CTRL_278083)) {
2191 + ha->dev_state = NX_DEV_READY;
2192 + if (ha->rom_status == MBS_ROM_FW_RUNNING) {
2193 + EL(ha, "ISP ROM Status = MBS_ROM_FW_RUNNING\n");
2194 + rval = QL_SUCCESS;
2195 + } else if (ha->rom_status == MBS_ROM_IDLE) {
2196 + EL(ha, "ISP ROM Status = MBS_ROM_IDLE\n");
2103 2197 rval = QL_FUNCTION_FAILED;
2104 2198 } else {
2105 - rval = ql_start_firmware(ha);
2199 + EL(ha, "ISP ROM Status, mbx0=%xh\n", ha->rom_status);
2200 + rval = QL_FUNCTION_FAILED;
2106 2201 }
2107 2202 } else if (CFG_IST(ha, CFG_DISABLE_RISC_CODE_LOAD)) {
2203 + ha->dev_state = NX_DEV_READY;
2108 2204 if (ha->risc_code != NULL) {
2109 2205 kmem_free(ha->risc_code, ha->risc_code_size);
2110 2206 ha->risc_code = NULL;
2111 2207 ha->risc_code_size = 0;
2112 2208 }
2113 2209
2114 2210 /* Get RISC code length. */
2115 - rval = ql_rd_risc_ram(ha, risc_address + 3, ha->request_dvma,
2116 - 1);
2211 + rval = ql_rd_risc_ram(ha, risc_address + 3,
2212 + ha->req_q[0]->req_ring.cookie.dmac_laddress, 1);
2117 2213 if (rval == QL_SUCCESS) {
2118 - lptr = (uint32_t *)ha->request_ring_bp;
2214 + lptr = (uint32_t *)ha->req_q[0]->req_ring.bp;
2119 2215 fw_size = *lptr << 1;
2120 2216
2121 2217 if ((bufp = kmem_alloc(fw_size, KM_SLEEP)) != NULL) {
2122 2218 ha->risc_code_size = fw_size;
2123 2219 ha->risc_code = bufp;
2124 2220 ha->fw_transfer_size = 128;
2125 2221
2126 2222 /* Dump RISC code. */
2127 2223 do {
2128 2224 if (fw_size > ha->fw_transfer_size) {
2129 2225 byte_count =
2130 2226 ha->fw_transfer_size;
2131 2227 } else {
2132 2228 byte_count = fw_size;
2133 2229 }
2134 2230
2135 2231 word_count =
2136 2232 (uint16_t)(byte_count >> 1);
2137 2233
2138 2234 rval = ql_rd_risc_ram(ha, risc_address,
2139 - ha->request_dvma, word_count);
2235 + ha->req_q[0]->req_ring.cookie.
2236 + dmac_laddress, word_count);
2140 2237 if (rval != QL_SUCCESS) {
2141 2238 kmem_free(ha->risc_code,
2142 2239 ha->risc_code_size);
2143 2240 ha->risc_code = NULL;
2144 2241 ha->risc_code_size = 0;
2145 2242 break;
2146 2243 }
2147 2244
2148 2245 (void) ddi_dma_sync(
2149 - ha->hba_buf.dma_handle,
2150 - REQUEST_Q_BUFFER_OFFSET,
2151 - byte_count,
2246 + ha->req_q[0]->req_ring.dma_handle,
2247 + 0, byte_count,
2152 2248 DDI_DMA_SYNC_FORKERNEL);
2153 - ddi_rep_get16(ha->hba_buf.acc_handle,
2154 - (uint16_t *)bufp,
2155 - (uint16_t *)ha->request_ring_bp,
2249 + ddi_rep_get16(
2250 + ha->req_q[0]->req_ring.acc_handle,
2251 + (uint16_t *)bufp, (uint16_t *)
2252 + ha->req_q[0]->req_ring.bp,
2156 2253 word_count, DDI_DEV_AUTOINCR);
2157 2254
2158 2255 risc_address += word_count;
2159 2256 fw_size -= byte_count;
2160 2257 bufp += byte_count;
2161 2258 } while (fw_size != 0);
2162 2259 }
2163 2260 rval = QL_FUNCTION_FAILED;
2164 2261 }
2165 2262 } else {
2263 + ha->dev_state = NX_DEV_READY;
2166 2264 rval = QL_FUNCTION_FAILED;
2167 2265 }
2168 2266
2169 2267 if (rval != QL_SUCCESS) {
2170 2268 EL(ha, "Load RISC code\n");
2171 2269 } else {
2172 2270 /*EMPTY*/
2173 - QL_PRINT_3(CE_CONT, "(%d): done\n", ha->instance);
2271 + QL_PRINT_10(ha, "done\n");
2174 2272 }
2175 2273 return (rval);
2176 2274 }
2177 2275
2178 2276 /*
2179 - * Chip diagnostics
2180 - * Test chip for proper operation.
2181 - *
2182 - * Input:
2183 - * ha = adapter state pointer.
2184 - *
2185 - * Returns:
2186 - * ql local function return status code.
2187 - *
2188 - * Context:
2189 - * Kernel context.
2190 - */
2191 -static int
2192 -ql_chip_diag(ql_adapter_state_t *ha)
2193 -{
2194 - ql_mbx_data_t mr;
2195 - int rval;
2196 - int32_t retries = 4;
2197 - uint16_t id;
2198 -
2199 - QL_PRINT_3(CE_CONT, "(%d): started\n", ha->instance);
2200 -
2201 - do {
2202 - /* Reset ISP chip. */
2203 - TASK_DAEMON_LOCK(ha);
2204 - ha->task_daemon_flags &= ~ISP_ABORT_NEEDED;
2205 - TASK_DAEMON_UNLOCK(ha);
2206 -
2207 - /* For ISP2200A reduce firmware load size. */
2208 - if (CFG_IST(ha, CFG_CTRL_2200) &&
2209 - RD16_IO_REG(ha, mailbox_out[7]) == 4) {
2210 - ha->fw_transfer_size = 128;
2211 - } else {
2212 - ha->fw_transfer_size = REQUEST_QUEUE_SIZE;
2213 - }
2214 -
2215 - rval = QL_SUCCESS;
2216 - if (!(CFG_IST(ha, CFG_CTRL_8021))) {
2217 - ql_reset_chip(ha);
2218 -
2219 - /* Check product ID of chip */
2220 - mr.mb[1] = RD16_IO_REG(ha, mailbox_out[1]);
2221 - mr.mb[2] = RD16_IO_REG(ha, mailbox_out[2]);
2222 - mr.mb[3] = RD16_IO_REG(ha, mailbox_out[3]);
2223 -
2224 - if (ha->device_id == 0x5432 ||
2225 - ha->device_id == 0x8432) {
2226 - id = 0x2432;
2227 - } else if (ha->device_id == 0x5422 ||
2228 - ha->device_id == 0x8422) {
2229 - id = 0x2422;
2230 - } else {
2231 - id = ha->device_id;
2232 - }
2233 -
2234 - if (mr.mb[1] == PROD_ID_1 &&
2235 - (mr.mb[2] == PROD_ID_2 || mr.mb[2] == PROD_ID_2a) &&
2236 - (mr.mb[3] == PROD_ID_3 || mr.mb[3] == id)) {
2237 - ha->adapter_stats->revlvl.isp2200 =
2238 - RD16_IO_REG(ha, mailbox_out[4]);
2239 - ha->adapter_stats->revlvl.risc =
2240 - RD16_IO_REG(ha, mailbox_out[5]);
2241 - ha->adapter_stats->revlvl.frmbfr =
2242 - RD16_IO_REG(ha, mailbox_out[6]);
2243 - ha->adapter_stats->revlvl.riscrom =
2244 - RD16_IO_REG(ha, mailbox_out[7]);
2245 - } else {
2246 - cmn_err(CE_WARN, "%s(%d) - prod id failed!, "
2247 - "mb1=%xh, mb2=%xh, mb3=%xh", QL_NAME,
2248 - ha->instance, mr.mb[1], mr.mb[2], mr.mb[3]);
2249 - rval = QL_FUNCTION_FAILED;
2250 - }
2251 - } else if (!(ha->task_daemon_flags & FIRMWARE_LOADED)) {
2252 - break;
2253 - }
2254 -
2255 - if (rval == QL_SUCCESS) {
2256 - /* Wrap Incoming Mailboxes Test. */
2257 - mr.mb[1] = 0xAAAA;
2258 - mr.mb[2] = 0x5555;
2259 - mr.mb[3] = 0xAA55;
2260 - mr.mb[4] = 0x55AA;
2261 - mr.mb[5] = 0xA5A5;
2262 - mr.mb[6] = 0x5A5A;
2263 - mr.mb[7] = 0x2525;
2264 - rval = ql_mbx_wrap_test(ha, &mr);
2265 - if (rval == QL_SUCCESS) {
2266 - if (mr.mb[1] != 0xAAAA ||
2267 - mr.mb[2] != 0x5555 ||
2268 - mr.mb[3] != 0xAA55 ||
2269 - mr.mb[4] != 0x55AA ||
2270 - mr.mb[5] != 0xA5A5 ||
2271 - mr.mb[6] != 0x5A5A ||
2272 - mr.mb[7] != 0x2525) {
2273 - rval = QL_FUNCTION_FAILED;
2274 - (void) ql_flash_errlog(ha,
2275 - FLASH_ERRLOG_ISP_ERR, 0,
2276 - RD16_IO_REG(ha, hccr),
2277 - RD16_IO_REG(ha, istatus));
2278 - }
2279 - } else {
2280 - cmn_err(CE_WARN, "%s(%d) - reg test failed="
2281 - "%xh!", QL_NAME, ha->instance, rval);
2282 - }
2283 - }
2284 - } while ((retries-- != 0) && (rval != QL_SUCCESS));
2285 -
2286 - if (rval != QL_SUCCESS) {
2287 - EL(ha, "failed, rval = %xh\n", rval);
2288 - } else {
2289 - /*EMPTY*/
2290 - QL_PRINT_3(CE_CONT, "(%d): done\n", ha->instance);
2291 - }
2292 - return (rval);
2293 -}
2294 -
2295 -/*
2296 2277 * ql_load_isp_firmware
2297 2278 * Load and start RISC firmware.
2298 2279 * Uses request ring for DMA buffer.
2299 2280 *
2300 2281 * Input:
2301 2282 * ha = adapter state pointer.
2302 2283 *
2303 2284 * Returns:
2304 2285 * ql local function return status code.
2305 2286 *
2306 2287 * Context:
2307 2288 * Kernel context.
2308 2289 */
2309 2290 int
2310 2291 ql_load_isp_firmware(ql_adapter_state_t *vha)
2311 2292 {
2312 2293 caddr_t risc_code_address;
2313 2294 uint32_t risc_address, risc_code_size;
2314 - int rval;
2295 + int rval = QL_FUNCTION_FAILED;
2315 2296 uint32_t word_count, cnt;
2316 2297 size_t byte_count;
2317 2298 ql_adapter_state_t *ha = vha->pha;
2318 2299
2319 - if (CFG_IST(ha, CFG_CTRL_8021)) {
2320 - rval = ql_8021_load_risc(ha);
2300 + QL_PRINT_10(ha, "started\n");
2301 +
2302 + if (CFG_IST(ha, CFG_CTRL_82XX)) {
2303 + rval = ql_8021_reset_fw(ha) == NX_DEV_READY ?
2304 + QL_SUCCESS : QL_FUNCTION_FAILED;
2321 2305 } else {
2322 2306 if (CFG_IST(ha, CFG_CTRL_81XX)) {
2323 2307 ql_mps_reset(ha);
2324 2308 }
2325 2309
2326 2310 if (CFG_IST(ha, CFG_LOAD_FLASH_FW)) {
2311 + QL_PRINT_10(ha, "CFG_LOAD_FLASH_FW exit\n");
2327 2312 return (ql_load_flash_fw(ha));
2328 2313 }
2329 2314
2330 - QL_PRINT_3(CE_CONT, "(%d): started\n", ha->instance);
2315 + if (CFG_IST(ha, CFG_CTRL_27XX)) {
2316 + (void) ql_2700_get_module_dmp_template(ha);
2317 + }
2331 2318
2332 2319 /* Load firmware segments */
2333 2320 for (cnt = 0; cnt < MAX_RISC_CODE_SEGMENTS &&
2334 2321 ha->risc_fw[cnt].code != NULL; cnt++) {
2335 2322
2336 2323 risc_code_address = ha->risc_fw[cnt].code;
2337 2324 risc_address = ha->risc_fw[cnt].addr;
2325 + if ((risc_address = ha->risc_fw[cnt].addr) == 0) {
2326 + continue;
2327 + }
2338 2328 risc_code_size = ha->risc_fw[cnt].length;
2339 2329
2340 2330 while (risc_code_size) {
2341 - if (CFG_IST(ha, CFG_CTRL_242581)) {
2331 + if (CFG_IST(ha, CFG_ISP_FW_TYPE_2)) {
2342 2332 word_count = ha->fw_transfer_size >> 2;
2343 2333 if (word_count > risc_code_size) {
2344 2334 word_count = risc_code_size;
2345 2335 }
2346 2336 byte_count = word_count << 2;
2347 2337
2348 - ddi_rep_put32(ha->hba_buf.acc_handle,
2338 + ddi_rep_put32(
2339 + ha->req_q[0]->req_ring.acc_handle,
2349 2340 (uint32_t *)risc_code_address,
2350 - (uint32_t *)ha->request_ring_bp,
2341 + (uint32_t *)
2342 + ha->req_q[0]->req_ring.bp,
2351 2343 word_count, DDI_DEV_AUTOINCR);
2352 2344 } else {
2353 2345 word_count = ha->fw_transfer_size >> 1;
2354 2346 if (word_count > risc_code_size) {
2355 2347 word_count = risc_code_size;
2356 2348 }
2357 2349 byte_count = word_count << 1;
2358 2350
2359 - ddi_rep_put16(ha->hba_buf.acc_handle,
2351 + ddi_rep_put16(
2352 + ha->req_q[0]->req_ring.acc_handle,
2360 2353 (uint16_t *)risc_code_address,
2361 - (uint16_t *)ha->request_ring_bp,
2354 + (uint16_t *)
2355 + ha->req_q[0]->req_ring.bp,
2362 2356 word_count, DDI_DEV_AUTOINCR);
2363 2357 }
2364 2358
2365 - (void) ddi_dma_sync(ha->hba_buf.dma_handle,
2366 - REQUEST_Q_BUFFER_OFFSET, byte_count,
2367 - DDI_DMA_SYNC_FORDEV);
2359 + (void) ddi_dma_sync(
2360 + ha->req_q[0]->req_ring.dma_handle,
2361 + 0, byte_count, DDI_DMA_SYNC_FORDEV);
2368 2362
2369 2363 rval = ql_wrt_risc_ram(ha, risc_address,
2370 - ha->request_dvma, word_count);
2364 + ha->req_q[0]->req_ring.cookie.dmac_laddress,
2365 + word_count);
2371 2366 if (rval != QL_SUCCESS) {
2372 2367 EL(ha, "failed, load=%xh\n", rval);
2373 2368 cnt = MAX_RISC_CODE_SEGMENTS;
2374 2369 break;
2375 2370 }
2376 2371
2377 2372 risc_address += word_count;
2378 2373 risc_code_size -= word_count;
2379 2374 risc_code_address += byte_count;
2380 2375 }
2381 2376 }
2382 2377 }
2378 + bzero(ha->req_q[0]->req_ring.bp, ha->fw_transfer_size);
2383 2379
2384 2380 /* Start firmware. */
2385 2381 if (rval == QL_SUCCESS) {
2386 2382 rval = ql_start_firmware(ha);
2387 2383 }
2388 2384
2389 2385 if (rval != QL_SUCCESS) {
2390 2386 EL(ha, "failed, rval = %xh\n", rval);
2391 2387 } else {
2392 2388 /*EMPTY*/
2393 - QL_PRINT_3(CE_CONT, "(%d): done\n", ha->instance);
2389 + QL_PRINT_10(ha, "done\n");
2394 2390 }
2395 2391
2396 2392 return (rval);
2397 2393 }
2398 2394
2399 2395 /*
2400 2396 * ql_load_flash_fw
2401 2397 * Gets ISP24xx firmware from flash and loads ISP.
2402 2398 *
2403 2399 * Input:
2404 2400 * ha: adapter state pointer.
2405 2401 *
2406 2402 * Returns:
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2407 2403 * ql local function return status code.
2408 2404 */
2409 2405 static int
2410 2406 ql_load_flash_fw(ql_adapter_state_t *ha)
2411 2407 {
2412 2408 int rval;
2413 2409 uint8_t seg_cnt;
2414 2410 uint32_t risc_address, xfer_size, count, *bp, faddr;
2415 2411 uint32_t risc_code_size = 0;
2416 2412
2417 - QL_PRINT_3(CE_CONT, "(%d): started\n", ha->instance);
2413 + QL_PRINT_10(ha, "started\n");
2418 2414
2419 - faddr = ha->flash_data_addr | ha->flash_fw_addr;
2415 + if (CFG_IST(ha, CFG_CTRL_278083)) {
2416 + if ((rval = ql_load_flash_image(ha)) != QL_SUCCESS) {
2417 + EL(ha, "load_flash_image status=%xh\n", rval);
2418 + } else if (CFG_IST(ha, CFG_CTRL_27XX) &&
2419 + (rval = ql_2700_get_flash_dmp_template(ha)) !=
2420 + QL_SUCCESS) {
2421 + EL(ha, "get_flash_dmp_template status=%xh\n", rval);
2422 + }
2423 + } else {
2424 + faddr = ha->flash_data_addr | ha->flash_fw_addr;
2420 2425
2421 - for (seg_cnt = 0; seg_cnt < 2; seg_cnt++) {
2422 - xfer_size = ha->fw_transfer_size >> 2;
2423 - do {
2424 - GLOBAL_HW_LOCK();
2426 + for (seg_cnt = 0; seg_cnt < 2; seg_cnt++) {
2427 + xfer_size = ha->fw_transfer_size >> 2;
2428 + do {
2429 + GLOBAL_HW_LOCK();
2425 2430
2426 - /* Read data from flash. */
2427 - bp = (uint32_t *)ha->request_ring_bp;
2428 - for (count = 0; count < xfer_size; count++) {
2429 - rval = ql_24xx_read_flash(ha, faddr++, bp);
2431 + /* Read data from flash. */
2432 + bp = (uint32_t *)ha->req_q[0]->req_ring.bp;
2433 + for (count = 0; count < xfer_size; count++) {
2434 + rval = ql_24xx_read_flash(ha, faddr++,
2435 + bp);
2436 + if (rval != QL_SUCCESS) {
2437 + break;
2438 + }
2439 + ql_chg_endian((uint8_t *)bp++, 4);
2440 + }
2441 +
2442 + GLOBAL_HW_UNLOCK();
2443 +
2430 2444 if (rval != QL_SUCCESS) {
2445 + EL(ha, "24xx_read_flash failed=%xh\n",
2446 + rval);
2431 2447 break;
2432 2448 }
2433 - ql_chg_endian((uint8_t *)bp++, 4);
2434 - }
2435 2449
2436 - GLOBAL_HW_UNLOCK();
2450 + if (risc_code_size == 0) {
2451 + bp = (uint32_t *)
2452 + ha->req_q[0]->req_ring.bp;
2453 + risc_address = bp[2];
2454 + risc_code_size = bp[3];
2455 + ha->risc_fw[seg_cnt].addr =
2456 + risc_address;
2457 + }
2437 2458
2438 - if (rval != QL_SUCCESS) {
2439 - EL(ha, "24xx_read_flash failed=%xh\n", rval);
2440 - break;
2441 - }
2459 + if (risc_code_size < xfer_size) {
2460 + faddr -= xfer_size - risc_code_size;
2461 + xfer_size = risc_code_size;
2462 + }
2442 2463
2443 - if (risc_code_size == 0) {
2444 - bp = (uint32_t *)ha->request_ring_bp;
2445 - risc_address = bp[2];
2446 - risc_code_size = bp[3];
2447 - ha->risc_fw[seg_cnt].addr = risc_address;
2448 - }
2464 + (void) ddi_dma_sync(
2465 + ha->req_q[0]->req_ring.dma_handle,
2466 + 0, xfer_size << 2, DDI_DMA_SYNC_FORDEV);
2449 2467
2450 - if (risc_code_size < xfer_size) {
2451 - faddr -= xfer_size - risc_code_size;
2452 - xfer_size = risc_code_size;
2453 - }
2468 + rval = ql_wrt_risc_ram(ha, risc_address,
2469 + ha->req_q[0]->req_ring.cookie.dmac_laddress,
2470 + xfer_size);
2471 + if (rval != QL_SUCCESS) {
2472 + EL(ha, "ql_wrt_risc_ram failed=%xh\n",
2473 + rval);
2474 + break;
2475 + }
2454 2476
2455 - (void) ddi_dma_sync(ha->hba_buf.dma_handle,
2456 - REQUEST_Q_BUFFER_OFFSET, xfer_size << 2,
2457 - DDI_DMA_SYNC_FORDEV);
2477 + risc_address += xfer_size;
2478 + risc_code_size -= xfer_size;
2479 + } while (risc_code_size);
2458 2480
2459 - rval = ql_wrt_risc_ram(ha, risc_address,
2460 - ha->request_dvma, xfer_size);
2461 2481 if (rval != QL_SUCCESS) {
2462 - EL(ha, "ql_wrt_risc_ram failed=%xh\n", rval);
2463 2482 break;
2464 2483 }
2465 -
2466 - risc_address += xfer_size;
2467 - risc_code_size -= xfer_size;
2468 - } while (risc_code_size);
2469 -
2470 - if (rval != QL_SUCCESS) {
2471 - break;
2472 2484 }
2473 2485 }
2474 2486
2475 2487 /* Start firmware. */
2476 2488 if (rval == QL_SUCCESS) {
2477 2489 rval = ql_start_firmware(ha);
2478 2490 }
2479 2491
2480 2492 if (rval != QL_SUCCESS) {
2481 2493 EL(ha, "failed, rval = %xh\n", rval);
2482 2494 } else {
2483 2495 /*EMPTY*/
2484 - QL_PRINT_3(CE_CONT, "(%d): done\n", ha->instance);
2496 + QL_PRINT_10(ha, "done\n");
2485 2497 }
2486 2498 return (rval);
2487 2499 }
2488 2500
2489 2501 /*
2490 2502 * ql_start_firmware
2491 2503 * Starts RISC code.
2492 2504 *
2493 2505 * Input:
2494 2506 * ha = adapter state pointer.
2495 2507 *
2496 2508 * Returns:
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2497 2509 * ql local function return status code.
2498 2510 *
2499 2511 * Context:
2500 2512 * Kernel context.
2501 2513 */
2502 2514 int
2503 2515 ql_start_firmware(ql_adapter_state_t *vha)
2504 2516 {
2505 2517 int rval, rval2;
2506 2518 uint32_t data;
2507 - ql_mbx_data_t mr;
2519 + ql_mbx_data_t mr = {0};
2508 2520 ql_adapter_state_t *ha = vha->pha;
2521 + ql_init_24xx_cb_t *icb =
2522 + (ql_init_24xx_cb_t *)&ha->init_ctrl_blk.cb24;
2509 2523
2510 - QL_PRINT_3(CE_CONT, "(%d): started\n", ha->instance);
2524 + QL_PRINT_10(ha, "started\n");
2511 2525
2512 - if (CFG_IST(ha, CFG_CTRL_8021)) {
2526 + if (CFG_IST(ha, CFG_CTRL_82XX)) {
2513 2527 /* Save firmware version. */
2514 2528 rval = ql_get_fw_version(ha, &mr, MAILBOX_TOV);
2515 2529 ha->fw_major_version = mr.mb[1];
2516 2530 ha->fw_minor_version = mr.mb[2];
2517 2531 ha->fw_subminor_version = mr.mb[3];
2518 2532 ha->fw_attributes = mr.mb[6];
2519 2533 } else if ((rval = ql_verify_checksum(ha)) == QL_SUCCESS) {
2520 2534 /* Verify checksum of loaded RISC code. */
2521 2535 /* Start firmware execution. */
2522 2536 (void) ql_execute_fw(ha);
2523 2537
2524 2538 /* Save firmware version. */
2525 2539 (void) ql_get_fw_version(ha, &mr, MAILBOX_TOV);
2526 2540 ha->fw_major_version = mr.mb[1];
2527 2541 ha->fw_minor_version = mr.mb[2];
2528 2542 ha->fw_subminor_version = mr.mb[3];
2529 - ha->fw_ext_memory_size = ((SHORT_TO_LONG(mr.mb[4], mr.mb[5]) -
2543 + ha->fw_ext_memory_end = SHORT_TO_LONG(mr.mb[4], mr.mb[5]);
2544 + ha->fw_ext_memory_size = ((ha->fw_ext_memory_end -
2530 2545 0x100000) + 1) * 4;
2531 - ha->fw_attributes = mr.mb[6];
2532 -
2533 - if (CFG_IST(ha, CFG_CTRL_81XX)) {
2546 + if (CFG_IST(ha, CFG_CTRL_278083)) {
2547 + ha->fw_attributes = SHORT_TO_LONG(mr.mb[6], mr.mb[15]);
2548 + ha->phy_fw_major_version = LSB(mr.mb[13]);
2549 + ha->phy_fw_minor_version = MSB(mr.mb[14]);
2550 + ha->phy_fw_subminor_version = LSB(mr.mb[14]);
2551 + ha->fw_ext_attributes = SHORT_TO_LONG(mr.mb[16],
2552 + mr.mb[17]);
2553 + } else {
2554 + ha->fw_attributes = mr.mb[6];
2534 2555 ha->phy_fw_major_version = LSB(mr.mb[8]);
2535 2556 ha->phy_fw_minor_version = MSB(mr.mb[9]);
2536 2557 ha->phy_fw_subminor_version = LSB(mr.mb[9]);
2537 - ha->mpi_fw_major_version = LSB(mr.mb[10]);
2538 - ha->mpi_fw_minor_version = MSB(mr.mb[11]);
2539 - ha->mpi_fw_subminor_version = LSB(mr.mb[11]);
2540 - ha->mpi_capability_list = SHORT_TO_LONG(mr.mb[13],
2541 - mr.mb[12]);
2558 + ha->mpi_capability_list =
2559 + SHORT_TO_LONG(mr.mb[13], mr.mb[12]);
2560 + }
2561 + ha->mpi_fw_major_version = LSB(mr.mb[10]);
2562 + ha->mpi_fw_minor_version = MSB(mr.mb[11]);
2563 + ha->mpi_fw_subminor_version = LSB(mr.mb[11]);
2564 + if (CFG_IST(ha, CFG_CTRL_27XX)) {
2565 + ha->fw_shared_ram_start =
2566 + SHORT_TO_LONG(mr.mb[18], mr.mb[19]);
2567 + ha->fw_shared_ram_end =
2568 + SHORT_TO_LONG(mr.mb[20], mr.mb[21]);
2569 + ha->fw_ddr_ram_start =
2570 + SHORT_TO_LONG(mr.mb[22], mr.mb[23]);
2571 + ha->fw_ddr_ram_end =
2572 + SHORT_TO_LONG(mr.mb[24], mr.mb[25]);
2573 + }
2574 + if (CFG_IST(ha, CFG_FLASH_ACC_SUPPORT)) {
2542 2575 if ((rval2 = ql_flash_access(ha, FAC_GET_SECTOR_SIZE,
2543 2576 0, 0, &data)) == QL_SUCCESS) {
2544 2577 ha->xioctl->fdesc.block_size = data << 2;
2545 - QL_PRINT_10(CE_CONT, "(%d): fdesc.block_size="
2546 - "%xh\n", ha->instance,
2578 + QL_PRINT_10(ha, "fdesc.block_size="
2579 + "%xh\n",
2547 2580 ha->xioctl->fdesc.block_size);
2548 2581 } else {
2549 2582 EL(ha, "flash_access status=%xh\n", rval2);
2550 2583 }
2551 2584 }
2552 2585
2553 2586 /* Set Serdes Transmit Parameters. */
2554 - if (CFG_IST(ha, CFG_CTRL_2422) && ha->serdes_param[0] & BIT_0) {
2587 + if (CFG_IST(ha, CFG_CTRL_24XX) && ha->serdes_param[0] & BIT_0) {
2555 2588 mr.mb[1] = ha->serdes_param[0];
2556 2589 mr.mb[2] = ha->serdes_param[1];
2557 2590 mr.mb[3] = ha->serdes_param[2];
2558 2591 mr.mb[4] = ha->serdes_param[3];
2559 2592 (void) ql_serdes_param(ha, &mr);
2560 2593 }
2561 2594 }
2562 2595 /* ETS workaround */
2563 2596 if (CFG_IST(ha, CFG_CTRL_81XX) && ql_enable_ets) {
2564 2597 if (ql_get_firmware_option(ha, &mr) == QL_SUCCESS) {
2565 2598 mr.mb[2] = (uint16_t)
2566 2599 (mr.mb[2] | FO2_FCOE_512_MAX_MEM_WR_BURST);
2567 2600 (void) ql_set_firmware_option(ha, &mr);
2568 2601 }
2569 2602 }
2603 +
2604 + if (ha->flags & MULTI_QUEUE) {
2605 + QL_PRINT_10(ha, "MULTI_QUEUE\n");
2606 + icb->msi_x_vector[0] = LSB(ha->rsp_queues[0]->msi_x_vector);
2607 + icb->msi_x_vector[1] = MSB(ha->rsp_queues[0]->msi_x_vector);
2608 + if (ha->iflags & IFLG_INTR_MSIX &&
2609 + CFG_IST(ha, CFG_NO_INTR_HSHAKE_SUP)) {
2610 + QL_PRINT_10(ha, "NO_INTR_HANDSHAKE\n");
2611 + ADAPTER_STATE_LOCK(ha);
2612 + ha->flags |= NO_INTR_HANDSHAKE;
2613 + ADAPTER_STATE_UNLOCK(ha);
2614 + icb->firmware_options_2[2] = (uint8_t)
2615 + (icb->firmware_options_2[2] & ~(BIT_6 | BIT_5));
2616 + icb->firmware_options_2[2] = (uint8_t)
2617 + (icb->firmware_options_2[2] | BIT_7);
2618 + } else {
2619 + icb->firmware_options_2[2] = (uint8_t)
2620 + (icb->firmware_options_2[2] & ~BIT_5);
2621 + icb->firmware_options_2[2] = (uint8_t)
2622 + (icb->firmware_options_2[2] | BIT_7 | BIT_6);
2623 + }
2624 + } else {
2625 + icb->firmware_options_2[2] = (uint8_t)
2626 + (icb->firmware_options_2[2] & ~(BIT_7 | BIT_5));
2627 + icb->firmware_options_2[2] = (uint8_t)
2628 + (icb->firmware_options_2[2] | BIT_6);
2629 + }
2630 + icb->firmware_options_2[3] = (uint8_t)
2631 + (icb->firmware_options_2[3] & ~(BIT_1 | BIT_0));
2632 +
2633 + /* Set fw execution throttle. */
2634 + if (CFG_IST(ha, CFG_CTRL_22XX) ||
2635 + ql_get_resource_cnts(ha, &mr) != QL_SUCCESS) {
2636 + icb->execution_throttle[0] = 0xff;
2637 + icb->execution_throttle[1] = 0xff;
2638 + } else {
2639 + icb->execution_throttle[0] = LSB(mr.mb[6]);
2640 + icb->execution_throttle[1] = MSB(mr.mb[6]);
2641 + }
2642 + EL(ha, "icb->execution_throttle %d\n",
2643 + CHAR_TO_SHORT(icb->execution_throttle[0],
2644 + icb->execution_throttle[1]));
2645 +
2570 2646 if (rval != QL_SUCCESS) {
2571 2647 ha->task_daemon_flags &= ~FIRMWARE_LOADED;
2572 2648 EL(ha, "failed, rval = %xh\n", rval);
2573 2649 } else {
2574 2650 ha->task_daemon_flags |= FIRMWARE_LOADED;
2575 - QL_PRINT_3(CE_CONT, "(%d): done\n", ha->instance);
2651 + QL_PRINT_10(ha, "done\n");
2576 2652 }
2577 2653 return (rval);
2578 2654 }
2579 2655
2580 2656 /*
2581 2657 * ql_set_cache_line
2582 2658 * Sets PCI cache line parameter.
2583 2659 *
2584 2660 * Input:
2585 2661 * ha = adapter state pointer.
2586 2662 *
2587 2663 * Returns:
2588 2664 * ql local function return status code.
2589 2665 *
2590 2666 * Context:
2591 2667 * Kernel context.
2592 2668 */
2593 2669 int
2594 2670 ql_set_cache_line(ql_adapter_state_t *ha)
2595 2671 {
2596 - QL_PRINT_3(CE_CONT, "(%d): started\n", ha->instance);
2672 + QL_PRINT_3(ha, "started\n");
2597 2673
2598 2674 /* Set the cache line. */
2599 2675 if (CFG_IST(ha->pha, CFG_SET_CACHE_LINE_SIZE_1)) {
2600 2676 /* Set cache line register. */
2601 2677 ql_pci_config_put8(ha->pha, PCI_CONF_CACHE_LINESZ, 1);
2602 2678 }
2603 2679
2604 - QL_PRINT_3(CE_CONT, "(%d): done\n", ha->instance);
2680 + QL_PRINT_3(ha, "done\n");
2605 2681
2606 2682 return (QL_SUCCESS);
2607 2683 }
2608 2684
2609 2685 /*
2610 2686 * ql_init_rings
2611 2687 * Initializes firmware and ring pointers.
2612 2688 *
2613 2689 * Beginning of response ring has initialization control block
2614 2690 * already built by nvram config routine.
2615 2691 *
2616 2692 * Input:
2617 - * ha = adapter state pointer.
2618 - * ha->hba_buf = request and response rings
2619 - * ha->init_ctrl_blk = initialization control block
2693 + * ha = adapter state pointer.
2694 + * ha->req_q = request rings
2695 + * ha->rsp_queues = response rings
2696 + * ha->init_ctrl_blk = initialization control block
2620 2697 *
2621 2698 * Returns:
2622 2699 * ql local function return status code.
2623 2700 *
2624 2701 * Context:
2625 2702 * Kernel context.
2626 2703 */
2627 2704 int
2628 2705 ql_init_rings(ql_adapter_state_t *vha2)
2629 2706 {
2630 2707 int rval, rval2;
2631 2708 uint16_t index;
2632 2709 ql_mbx_data_t mr;
2633 2710 ql_adapter_state_t *ha = vha2->pha;
2634 2711
2635 - QL_PRINT_3(CE_CONT, "(%d): started\n", ha->instance);
2712 + QL_PRINT_3(ha, "started\n");
2636 2713
2637 2714 /* Clear outstanding commands array. */
2638 - for (index = 0; index < MAX_OUTSTANDING_COMMANDS; index++) {
2715 + for (index = 0; index < ha->osc_max_cnt; index++) {
2639 2716 ha->outstanding_cmds[index] = NULL;
2640 2717 }
2641 2718 ha->osc_index = 1;
2642 2719
2643 2720 ha->pending_cmds.first = NULL;
2644 2721 ha->pending_cmds.last = NULL;
2645 2722
2646 2723 /* Initialize firmware. */
2647 - ha->request_ring_ptr = ha->request_ring_bp;
2648 - ha->req_ring_index = 0;
2649 - ha->req_q_cnt = REQUEST_ENTRY_CNT - 1;
2650 - ha->response_ring_ptr = ha->response_ring_bp;
2651 - ha->rsp_ring_index = 0;
2724 + ha->req_q[0]->req_ring_ptr = ha->req_q[0]->req_ring.bp;
2725 + ha->req_q[0]->req_ring_index = 0;
2726 + ha->req_q[0]->req_q_cnt = REQUEST_ENTRY_CNT - 1;
2727 + ha->rsp_queues[0]->rsp_ring_ptr = ha->rsp_queues[0]->rsp_ring.bp;
2728 + ha->rsp_queues[0]->rsp_ring_index = 0;
2652 2729
2653 2730 if (ha->flags & VP_ENABLED) {
2654 2731 ql_adapter_state_t *vha;
2655 - uint16_t cnt;
2656 - uint32_t max_vports;
2657 2732 ql_init_24xx_cb_t *icb = &ha->init_ctrl_blk.cb24;
2658 2733
2659 - max_vports = (CFG_IST(ha, CFG_CTRL_2422) ?
2660 - MAX_24_VIRTUAL_PORTS : MAX_25_VIRTUAL_PORTS);
2661 2734 bzero(icb->vp_count,
2662 2735 ((uintptr_t)icb + sizeof (ql_init_24xx_cb_t)) -
2663 2736 (uintptr_t)icb->vp_count);
2664 - icb->vp_count[0] = (uint8_t)max_vports;
2737 + icb->vp_count[0] = ha->max_vports - 1;
2665 2738
2666 2739 /* Allow connection option 2. */
2667 2740 icb->global_vp_option[0] = BIT_1;
2668 2741
2669 - for (cnt = 0, vha = ha->vp_next; cnt < max_vports &&
2670 - vha != NULL; vha = vha->vp_next, cnt++) {
2742 + /* Setup default options for all ports. */
2743 + for (index = 0; index < ha->max_vports; index++) {
2744 + icb->vpc[index].options = VPO_TARGET_MODE_DISABLED |
2745 + VPO_INITIATOR_MODE_ENABLED;
2746 + }
2747 + /* Setup enabled ports. */
2748 + for (vha = ha->vp_next; vha != NULL; vha = vha->vp_next) {
2749 + if (vha->vp_index == 0 ||
2750 + vha->vp_index >= ha->max_vports) {
2751 + continue;
2752 + }
2671 2753
2672 2754 index = (uint8_t)(vha->vp_index - 1);
2673 2755 bcopy(vha->loginparams.node_ww_name.raw_wwn,
2674 2756 icb->vpc[index].node_name, 8);
2675 2757 bcopy(vha->loginparams.nport_ww_name.raw_wwn,
2676 2758 icb->vpc[index].port_name, 8);
2677 2759
2678 - icb->vpc[index].options = VPO_TARGET_MODE_DISABLED |
2679 - VPO_INITIATOR_MODE_ENABLED;
2680 2760 if (vha->flags & VP_ENABLED) {
2681 2761 icb->vpc[index].options = (uint8_t)
2682 2762 (icb->vpc[index].options | VPO_ENABLED);
2683 2763 }
2684 2764 }
2685 2765 }
2686 2766
2687 2767 for (index = 0; index < 2; index++) {
2688 2768 rval = ql_init_firmware(ha);
2689 2769 if (rval == QL_COMMAND_ERROR) {
2690 2770 EL(ha, "stopping firmware\n");
2691 2771 (void) ql_stop_firmware(ha);
2692 2772 } else {
2693 2773 break;
2694 2774 }
2695 2775 }
2696 2776
2697 - if (rval == QL_SUCCESS && (CFG_IST(ha, CFG_CTRL_24258081)) == 0) {
2777 + if (rval == QL_SUCCESS && CFG_IST(ha, CFG_ISP_FW_TYPE_1)) {
2698 2778 /* Tell firmware to enable MBA_PORT_BYPASS_CHANGED event */
2699 2779 rval = ql_get_firmware_option(ha, &mr);
2700 2780 if (rval == QL_SUCCESS) {
2701 2781 mr.mb[1] = (uint16_t)(mr.mb[1] | BIT_9);
2702 2782 mr.mb[2] = 0;
2703 2783 mr.mb[3] = BIT_10;
2704 2784 rval = ql_set_firmware_option(ha, &mr);
2705 2785 }
2706 2786 }
2707 2787
2708 2788 if ((rval == QL_SUCCESS) && (CFG_IST(ha, CFG_ENABLE_FWFCETRACE))) {
2709 2789 /* Firmware Fibre Channel Event Trace Buffer */
2710 2790 if ((rval2 = ql_get_dma_mem(ha, &ha->fwfcetracebuf, FWFCESIZE,
2711 2791 LITTLE_ENDIAN_DMA, QL_DMA_RING_ALIGN)) != QL_SUCCESS) {
2712 2792 EL(ha, "fcetrace buffer alloc failed: %xh\n", rval2);
2713 2793 } else {
2714 2794 if ((rval2 = ql_fw_etrace(ha, &ha->fwfcetracebuf,
2715 - FTO_FCE_TRACE_ENABLE)) != QL_SUCCESS) {
2795 + FTO_FCE_TRACE_ENABLE, NULL)) != QL_SUCCESS) {
2716 2796 EL(ha, "fcetrace enable failed: %xh\n", rval2);
2717 2797 ql_free_phys(ha, &ha->fwfcetracebuf);
2718 2798 }
2719 2799 }
2720 2800 }
2721 2801
2722 2802 if ((rval == QL_SUCCESS) && (CFG_IST(ha, CFG_ENABLE_FWEXTTRACE))) {
2723 2803 /* Firmware Extended Trace Buffer */
2724 2804 if ((rval2 = ql_get_dma_mem(ha, &ha->fwexttracebuf, FWEXTSIZE,
2725 2805 LITTLE_ENDIAN_DMA, QL_DMA_RING_ALIGN)) != QL_SUCCESS) {
2726 2806 EL(ha, "exttrace buffer alloc failed: %xh\n", rval2);
2727 2807 } else {
2728 2808 if ((rval2 = ql_fw_etrace(ha, &ha->fwexttracebuf,
2729 - FTO_EXT_TRACE_ENABLE)) != QL_SUCCESS) {
2809 + FTO_EXT_TRACE_ENABLE, NULL)) != QL_SUCCESS) {
2730 2810 EL(ha, "exttrace enable failed: %xh\n", rval2);
2731 2811 ql_free_phys(ha, &ha->fwexttracebuf);
2732 2812 }
2733 2813 }
2734 2814 }
2735 2815
2736 2816 if (rval == QL_SUCCESS && CFG_IST(ha, CFG_CTRL_MENLO)) {
2737 2817 ql_mbx_iocb_t *pkt;
2738 2818 clock_t timer;
2739 2819
2740 2820 /* Wait for firmware login of menlo. */
2741 2821 for (timer = 3000; timer; timer--) {
2742 2822 if (ha->flags & MENLO_LOGIN_OPERATIONAL) {
2743 2823 break;
2744 2824 }
2745 2825
2746 2826 if (!(ha->flags & INTERRUPTS_ENABLED) ||
2747 2827 ddi_in_panic()) {
2748 2828 if (INTERRUPT_PENDING(ha)) {
2749 2829 (void) ql_isr((caddr_t)ha);
2750 2830 INTR_LOCK(ha);
2751 2831 ha->intr_claimed = B_TRUE;
2752 2832 INTR_UNLOCK(ha);
2753 2833 }
2754 2834 }
2755 2835
2756 2836 /* Delay for 1 tick (10 milliseconds). */
2757 2837 ql_delay(ha, 10000);
2758 2838 }
2759 2839
2760 2840 if (timer == 0) {
2761 2841 rval = QL_FUNCTION_TIMEOUT;
2762 2842 } else {
2763 2843 pkt = kmem_zalloc(sizeof (ql_mbx_iocb_t), KM_SLEEP);
2764 2844 if (pkt == NULL) {
2765 2845 EL(ha, "failed, kmem_zalloc\n");
2766 2846 rval = QL_MEMORY_ALLOC_FAILED;
2767 2847 } else {
2768 2848 pkt->mvfy.entry_type = VERIFY_MENLO_TYPE;
2769 2849 pkt->mvfy.entry_count = 1;
2770 2850 pkt->mvfy.options_status =
2771 2851 LE_16(VMF_DO_NOT_UPDATE_FW);
2772 2852
2773 2853 rval = ql_issue_mbx_iocb(ha, (caddr_t)pkt,
2774 2854 sizeof (ql_mbx_iocb_t));
2775 2855 LITTLE_ENDIAN_16(&pkt->mvfy.options_status);
2776 2856 LITTLE_ENDIAN_16(&pkt->mvfy.failure_code);
2777 2857
2778 2858 if (rval != QL_SUCCESS ||
2779 2859 (pkt->mvfy.entry_status & 0x3c) != 0 ||
2780 2860 pkt->mvfy.options_status != CS_COMPLETE) {
2781 2861 EL(ha, "failed, status=%xh, es=%xh, "
2782 2862 "cs=%xh, fc=%xh\n", rval,
2783 2863 pkt->mvfy.entry_status & 0x3c,
2784 2864 pkt->mvfy.options_status,
2785 2865 pkt->mvfy.failure_code);
2786 2866 if (rval == QL_SUCCESS) {
2787 2867 rval = QL_FUNCTION_FAILED;
2788 2868 }
2789 2869 }
2790 2870
2791 2871 kmem_free(pkt, sizeof (ql_mbx_iocb_t));
2792 2872 }
2793 2873 }
2794 2874 }
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2795 2875
2796 2876 if (rval != QL_SUCCESS) {
2797 2877 TASK_DAEMON_LOCK(ha);
2798 2878 ha->task_daemon_flags &= ~FIRMWARE_UP;
2799 2879 TASK_DAEMON_UNLOCK(ha);
2800 2880 EL(ha, "failed, rval = %xh\n", rval);
2801 2881 } else {
2802 2882 TASK_DAEMON_LOCK(ha);
2803 2883 ha->task_daemon_flags |= FIRMWARE_UP;
2804 2884 TASK_DAEMON_UNLOCK(ha);
2805 - QL_PRINT_3(CE_CONT, "(%d): done\n", ha->instance);
2885 + QL_PRINT_3(ha, "done\n");
2806 2886 }
2807 2887 return (rval);
2808 2888 }
2809 2889
2810 2890 /*
2811 2891 * ql_fw_ready
2812 2892 * Waits for firmware ready. If firmware becomes ready
2813 2893 * device queues and RISC code are synchronized.
2814 2894 *
2815 2895 * Input:
2816 2896 * ha = adapter state pointer.
2817 2897 * secs = max wait time, in seconds (0-255).
2818 2898 *
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2819 2899 * Returns:
2820 2900 * ql local function return status code.
2821 2901 *
2822 2902 * Context:
2823 2903 * Kernel context.
2824 2904 */
2825 2905 int
2826 2906 ql_fw_ready(ql_adapter_state_t *ha, uint8_t secs)
2827 2907 {
2828 2908 ql_mbx_data_t mr;
2829 - clock_t timer;
2909 + clock_t timer, login_wait, wait;
2830 2910 clock_t dly = 250000;
2831 2911 clock_t sec_delay = MICROSEC / dly;
2832 - clock_t wait = secs * sec_delay;
2833 2912 int rval = QL_FUNCTION_FAILED;
2834 - uint16_t state = 0xffff;
2913 + uint16_t state[6] = {0};
2835 2914
2836 - QL_PRINT_3(CE_CONT, "(%d): started\n", ha->instance);
2915 + QL_PRINT_3(ha, "started\n");
2837 2916
2838 - timer = ha->r_a_tov < secs ? secs : ha->r_a_tov;
2839 - timer = (timer + 2) * sec_delay;
2917 + login_wait = ha->r_a_tov * 2 * sec_delay;
2918 + timer = wait = secs * sec_delay;
2919 + state[0] = 0xffff;
2840 2920
2841 2921 /* Wait for ISP to finish LIP */
2842 - while (timer != 0 && wait != 0 &&
2843 - !(ha->task_daemon_flags & ISP_ABORT_NEEDED)) {
2922 + while (login_wait != 0 && wait != 0 &&
2923 + !(ha->task_daemon_flags & ISP_ABORT_NEEDED) &&
2924 + !(ha->flags & MPI_RESET_NEEDED)) {
2844 2925
2845 2926 rval = ql_get_firmware_state(ha, &mr);
2846 2927 if (rval == QL_SUCCESS) {
2847 - if (ha->task_daemon_flags & (ISP_ABORT_NEEDED |
2848 - LOOP_DOWN)) {
2849 - wait--;
2850 - } else if (mr.mb[1] != FSTATE_READY) {
2928 + if (mr.mb[1] != FSTATE_READY) {
2929 + if (mr.mb[1] == FSTATE_LOSS_SYNC &&
2930 + mr.mb[4] == FSTATE_MPI_NIC_ERROR &&
2931 + CFG_IST(ha, CFG_FCOE_SUPPORT)) {
2932 + EL(ha, "mpi_nic_error, "
2933 + "isp_abort_needed\n");
2934 + ADAPTER_STATE_LOCK(ha);
2935 + ha->flags |= MPI_RESET_NEEDED;
2936 + ADAPTER_STATE_UNLOCK(ha);
2937 + if (!(ha->task_daemon_flags &
2938 + ABORT_ISP_ACTIVE)) {
2939 + TASK_DAEMON_LOCK(ha);
2940 + ha->task_daemon_flags |=
2941 + ISP_ABORT_NEEDED;
2942 + TASK_DAEMON_UNLOCK(ha);
2943 + }
2944 + }
2851 2945 if (mr.mb[1] != FSTATE_WAIT_LOGIN) {
2852 - wait--;
2946 + timer = --wait;
2947 + } else {
2948 + timer = --login_wait;
2853 2949 }
2854 2950 rval = QL_FUNCTION_FAILED;
2855 2951 } else {
2856 2952 /* Firmware is ready. Get 2 * R_A_TOV. */
2857 2953 rval = ql_get_timeout_parameters(ha,
2858 2954 &ha->r_a_tov);
2859 2955 if (rval != QL_SUCCESS) {
2860 2956 EL(ha, "failed, get_timeout_param"
2861 2957 "=%xh\n", rval);
2862 2958 }
2863 2959
2864 2960 /* Configure loop. */
2865 2961 rval = ql_configure_loop(ha);
2866 2962 (void) ql_marker(ha, 0, 0, MK_SYNC_ALL);
2867 2963
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2868 2964 if (ha->task_daemon_flags &
2869 2965 LOOP_RESYNC_NEEDED) {
2870 2966 wait--;
2871 2967 EL(ha, "loop trans; tdf=%xh\n",
2872 2968 ha->task_daemon_flags);
2873 2969 } else {
2874 2970 break;
2875 2971 }
2876 2972 }
2877 2973 } else {
2878 - wait--;
2974 + break;
2879 2975 }
2880 2976
2881 - if (state != mr.mb[1]) {
2882 - EL(ha, "mailbox_reg[1] = %xh\n", mr.mb[1]);
2883 - state = mr.mb[1];
2977 + if (state[0] != mr.mb[1] || state[1] != mr.mb[2] ||
2978 + state[2] != mr.mb[3] || state[3] != mr.mb[4] ||
2979 + state[4] != mr.mb[5] || state[5] != mr.mb[6]) {
2980 + EL(ha, "mbx1=%xh, mbx2=%xh, mbx3=%xh, mbx4=%xh, "
2981 + "mbx5=%xh, mbx6=%xh\n", mr.mb[1], mr.mb[2],
2982 + mr.mb[3], mr.mb[4], mr.mb[5], mr.mb[6]);
2983 + state[0] = mr.mb[1];
2984 + state[1] = mr.mb[2];
2985 + state[2] = mr.mb[3];
2986 + state[3] = mr.mb[4];
2987 + state[4] = mr.mb[5];
2988 + state[5] = mr.mb[6];
2884 2989 }
2885 2990
2886 2991 /* Delay for a tick if waiting. */
2887 - if (timer-- != 0 && wait != 0) {
2992 + if (timer != 0) {
2888 2993 if (timer % 4 == 0) {
2889 2994 delay(drv_usectohz(dly));
2890 2995 } else {
2891 2996 drv_usecwait(dly);
2892 2997 }
2893 2998 } else {
2894 2999 rval = QL_FUNCTION_TIMEOUT;
2895 3000 }
2896 3001 }
2897 3002
2898 3003 if (rval != QL_SUCCESS) {
3004 + if ((ha->task_daemon_flags & ISP_ABORT_NEEDED ||
3005 + ha->flags & MPI_RESET_NEEDED) &&
3006 + ha->task_daemon_flags & LOOP_RESYNC_NEEDED) {
3007 + TASK_DAEMON_LOCK(ha);
3008 + ha->task_daemon_flags &= ~LOOP_RESYNC_NEEDED;
3009 + TASK_DAEMON_UNLOCK(ha);
3010 + }
2899 3011 EL(ha, "failed, rval = %xh\n", rval);
2900 3012 } else {
2901 3013 /*EMPTY*/
2902 - QL_PRINT_3(CE_CONT, "(%d): done\n", ha->instance);
3014 + QL_PRINT_3(ha, "done\n");
2903 3015 }
2904 3016 return (rval);
2905 3017 }
2906 3018
2907 3019 /*
2908 3020 * ql_configure_loop
2909 3021 * Setup configurations based on loop.
2910 3022 *
2911 3023 * Input:
2912 3024 * ha = adapter state pointer.
2913 3025 *
2914 3026 * Returns:
2915 3027 * ql local function return status code.
2916 3028 *
2917 3029 * Context:
2918 3030 * Kernel context.
2919 3031 */
2920 3032 static int
2921 3033 ql_configure_loop(ql_adapter_state_t *ha)
2922 3034 {
2923 - int rval;
3035 + int rval = QL_SUCCESS;
2924 3036 ql_adapter_state_t *vha;
2925 3037
2926 - QL_PRINT_3(CE_CONT, "(%d): started\n", ha->instance);
3038 + QL_PRINT_10(ha, "started\n");
2927 3039
2928 3040 for (vha = ha; vha != NULL; vha = vha->vp_next) {
2929 3041 TASK_DAEMON_LOCK(ha);
2930 3042 if (!(vha->task_daemon_flags & LOOP_RESYNC_NEEDED) &&
2931 - vha->vp_index != 0 && !(vha->flags & VP_ENABLED)) {
3043 + vha->vp_index != 0 &&
3044 + (!(vha->flags & VP_ENABLED) ||
3045 + vha->flags & VP_ID_NOT_ACQUIRED)) {
2932 3046 TASK_DAEMON_UNLOCK(ha);
2933 3047 continue;
2934 3048 }
2935 3049 vha->task_daemon_flags &= ~LOOP_RESYNC_NEEDED;
2936 3050 TASK_DAEMON_UNLOCK(ha);
2937 3051
2938 3052 rval = ql_configure_hba(vha);
2939 3053 if (rval == QL_SUCCESS && !(ha->task_daemon_flags &
2940 3054 (LOOP_RESYNC_NEEDED | LOOP_DOWN))) {
2941 3055 rval = ql_configure_device_d_id(vha);
2942 3056 if (rval == QL_SUCCESS && !(ha->task_daemon_flags &
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2943 3057 (LOOP_RESYNC_NEEDED | LOOP_DOWN))) {
2944 3058 (void) ql_configure_fabric(vha);
2945 3059 }
2946 3060 }
2947 3061 }
2948 3062
2949 3063 if (rval != QL_SUCCESS) {
2950 3064 EL(ha, "failed, rval = %xh\n", rval);
2951 3065 } else {
2952 3066 /*EMPTY*/
2953 - QL_PRINT_3(CE_CONT, "(%d): done\n", ha->instance);
3067 + QL_PRINT_10(ha, "done\n");
2954 3068 }
2955 3069 return (rval);
2956 3070 }
2957 3071
2958 3072 /*
2959 3073 * ql_configure_n_port_info
2960 3074 * Setup configurations based on N port 2 N port topology.
2961 3075 *
2962 3076 * Input:
2963 3077 * ha = adapter state pointer.
2964 3078 *
2965 3079 * Returns:
2966 3080 * ql local function return status code.
2967 3081 *
2968 3082 * Context:
2969 3083 * Kernel context.
3084 + * ADAPTER_STATE_LOCK must be already obtained
2970 3085 */
2971 3086 static void
2972 3087 ql_configure_n_port_info(ql_adapter_state_t *ha)
2973 3088 {
2974 - ql_tgt_t tmp_tq;
2975 - ql_tgt_t *tq;
2976 - uint8_t *cb_port_name;
2977 - ql_link_t *link;
2978 - int index, rval;
3089 + ql_tgt_t tmp_tq;
3090 + ql_tgt_t *tq;
3091 + uint8_t *cb_port_name;
3092 + ql_link_t *link;
3093 + int index, rval;
3094 + uint16_t loop_id = 0;
3095 + uint32_t found = 0;
3096 + ql_dev_id_list_t *list;
3097 + uint32_t list_size;
3098 + ql_mbx_data_t mr;
3099 + port_id_t d_id = {0, 0, 0, 0};
2979 3100
2980 - tq = &tmp_tq;
3101 + QL_PRINT_10(ha, "started\n");
2981 3102
2982 3103 /* Free existing target queues. */
2983 3104 for (index = 0; index < DEVICE_HEAD_LIST_SIZE; index++) {
2984 3105 link = ha->dev[index].first;
2985 3106 while (link != NULL) {
2986 3107 tq = link->base_address;
2987 3108 link = link->next;
2988 - ql_remove_link(&ha->dev[index], &tq->device);
2989 - ql_dev_free(ha, tq);
3109 +
3110 + /* workaround FW issue, do implicit logout */
3111 + /* Never logo to the reused loopid!! */
3112 + if ((tq->loop_id != 0x7ff) &&
3113 + (tq->loop_id != 0x7fe)) {
3114 + if (found == 0) {
3115 + rval = ql_get_port_database(ha,
3116 + tq, PDF_NONE);
3117 + if ((rval == QL_SUCCESS) &&
3118 + (tq->master_state ==
3119 + PD_STATE_PORT_LOGGED_IN)) {
3120 + EL(ha, "nport id (%xh) "
3121 + "loop_id=%xh "
3122 + "reappeared\n",
3123 + tq->d_id.b24,
3124 + tq->loop_id);
3125 + bcopy((void *)&tq->port_name[0],
3126 + (void *)&ha->n_port->
3127 + port_name[0],
3128 + 8);
3129 + bcopy((void *)&tq->node_name[0],
3130 + (void *)&ha->n_port->
3131 + node_name[0],
3132 + 8);
3133 + ha->n_port->d_id.b24 =
3134 + tq->d_id.b24;
3135 + found = 1;
3136 + continue;
3137 + }
3138 + }
3139 + (void) ql_logout_fabric_port(ha, tq);
3140 + }
3141 +
3142 + tq->loop_id = PORT_NO_LOOP_ID;
2990 3143 }
2991 3144 }
2992 3145
3146 + if (found == 1) {
3147 + QL_PRINT_10(ha, "done found\n");
3148 + return;
3149 + }
3150 +
3151 + tq = &tmp_tq;
3152 +
2993 3153 /*
2994 3154 * If the N_Port's WWPN is larger than our's then it has the
2995 3155 * N_Port login initiative. It will have determined that and
2996 3156 * logged in with the firmware. This results in a device
2997 3157 * database entry. In this situation we will later send up a PLOGI
2998 3158 * by proxy for the N_Port to get things going.
2999 3159 *
3000 3160 * If the N_Ports WWPN is smaller then the firmware has the
3001 3161 * N_Port login initiative and does a FLOGI in order to obtain the
3002 3162 * N_Ports WWNN and WWPN. These names are required later
3003 3163 * during Leadvilles FLOGI. No PLOGI is done by the firmware in
3004 3164 * anticipation of a PLOGI via the driver from the upper layers.
3005 3165 * Upon reciept of said PLOGI the driver issues an ELS PLOGI
3006 3166 * pass-through command and the firmware assumes the s_id
3007 3167 * and the N_Port assumes the d_id and Bob's your uncle.
3008 3168 */
3009 3169
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3010 3170 /*
3011 3171 * In N port 2 N port topology the FW provides a port database entry at
3012 3172 * loop_id 0x7fe which allows us to acquire the Ports WWPN.
3013 3173 */
3014 3174 tq->d_id.b.al_pa = 0;
3015 3175 tq->d_id.b.area = 0;
3016 3176 tq->d_id.b.domain = 0;
3017 3177 tq->loop_id = 0x7fe;
3018 3178
3019 3179 rval = ql_get_port_database(ha, tq, PDF_NONE);
3020 - if (rval == QL_SUCCESS || rval == QL_NOT_LOGGED_IN) {
3021 - ql_dev_id_list_t *list;
3022 - uint32_t list_size;
3023 - ql_mbx_data_t mr;
3024 - port_id_t d_id = {0, 0, 0, 0};
3025 - uint16_t loop_id = 0;
3026 3180
3027 - cb_port_name = (uint8_t *)(CFG_IST(ha, CFG_CTRL_24258081) ?
3028 - &ha->init_ctrl_blk.cb24.port_name[0] :
3029 - &ha->init_ctrl_blk.cb.port_name[0]);
3181 + /*
3182 + * Only collect the P2P remote port information in the case of
3183 + * QL_SUCCESS. FW should have always logged in (flogi) to remote
3184 + * port at this point.
3185 + */
3186 + if (rval == QL_SUCCESS) {
3187 + cb_port_name = &ha->loginparams.nport_ww_name.raw_wwn[0];
3030 3188
3031 3189 if ((ql_wwn_cmp(ha, (la_wwn_t *)&tq->port_name[0],
3032 3190 (la_wwn_t *)cb_port_name) == 1)) {
3033 3191 EL(ha, "target port has N_Port login initiative\n");
3034 3192 } else {
3035 3193 EL(ha, "host port has N_Port login initiative\n");
3036 3194 }
3037 3195
3038 3196 /* Capture the N Ports WWPN */
3039 3197
3040 3198 bcopy((void *)&tq->port_name[0],
3041 3199 (void *)&ha->n_port->port_name[0], 8);
3042 3200 bcopy((void *)&tq->node_name[0],
3043 3201 (void *)&ha->n_port->node_name[0], 8);
3044 3202
3045 3203 /* Resolve an n_port_handle */
3046 3204 ha->n_port->n_port_handle = 0x7fe;
3047 3205
3048 - list_size = sizeof (ql_dev_id_list_t) * DEVICE_LIST_ENTRIES;
3049 - list = (ql_dev_id_list_t *)kmem_zalloc(list_size, KM_SLEEP);
3206 + }
3050 3207
3051 - if (list != NULL &&
3052 - ql_get_id_list(ha, (caddr_t)list, list_size, &mr) ==
3053 - QL_SUCCESS) {
3054 - if (mr.mb[1]) {
3055 - EL(ha, "id list entries = %d\n", mr.mb[1]);
3056 - for (index = 0; index < mr.mb[1]; index++) {
3057 - ql_dev_list(ha, list, index,
3058 - &d_id, &loop_id);
3059 - ha->n_port->n_port_handle = loop_id;
3060 - }
3208 + list_size = sizeof (ql_dev_id_list_t) * DEVICE_LIST_ENTRIES;
3209 + list = (ql_dev_id_list_t *)kmem_zalloc(list_size, KM_SLEEP);
3210 +
3211 + if (ql_get_id_list(ha, (caddr_t)list, list_size, &mr) ==
3212 + QL_SUCCESS) {
3213 + /* For the p2p mr.mb[1] must be 1 */
3214 + if (mr.mb[1] == 1) {
3215 + index = 0;
3216 + ql_dev_list(ha, list, index,
3217 + &d_id, &loop_id);
3218 + ha->n_port->n_port_handle = loop_id;
3219 +
3220 + tq->loop_id = loop_id;
3221 + tq->d_id.b24 = d_id.b24;
3222 + ha->n_port->d_id.b24 = d_id.b24;
3061 3223 } else {
3062 3224 for (index = 0; index <= LAST_LOCAL_LOOP_ID;
3063 3225 index++) {
3064 3226 /* resuse tq */
3065 3227 tq->loop_id = (uint16_t)index;
3066 3228 rval = ql_get_port_database(ha, tq,
3067 3229 PDF_NONE);
3068 3230 if (rval == QL_NOT_LOGGED_IN) {
3069 3231 if (tq->master_state ==
3070 3232 PD_STATE_PLOGI_PENDING) {
3071 3233 ha->n_port->
3072 3234 n_port_handle =
3073 3235 tq->loop_id;
3236 + ha->n_port->d_id.b24 =
3237 + tq->hard_addr.b24;
3074 3238 break;
3075 3239 }
3076 - } else {
3240 + } else if (rval == QL_SUCCESS) {
3077 3241 ha->n_port->n_port_handle =
3078 3242 tq->loop_id;
3243 + ha->n_port->d_id.b24 =
3244 + tq->hard_addr.b24;
3245 +
3079 3246 break;
3080 3247 }
3081 3248 }
3249 + if (index > LAST_LOCAL_LOOP_ID) {
3250 + EL(ha, "P2P:exceeded last id, "
3251 + "n_port_handle = %xh\n",
3252 + ha->n_port->n_port_handle);
3253 +
3254 + ha->n_port->n_port_handle = 0;
3255 + tq->loop_id = 0;
3256 + }
3082 3257 }
3083 3258 } else {
3084 - cmn_err(CE_WARN, "!%s(%d) didn't get list for %xh",
3085 - QL_NAME, ha->instance, d_id.b24);
3086 - }
3087 - if (list != NULL) {
3088 3259 kmem_free(list, list_size);
3260 + EL(ha, "ql_get_dev_list unsuccessful\n");
3261 + return;
3089 3262 }
3090 - }
3263 +
3264 + /* with the tq->loop_id to get the port database */
3265 +
3266 + rval = ql_get_port_database(ha, tq, PDF_NONE);
3267 +
3268 + if (rval == QL_NOT_LOGGED_IN) {
3269 + if (tq->master_state == PD_STATE_PLOGI_PENDING) {
3270 + bcopy((void *)&tq->port_name[0],
3271 + (void *)&ha->n_port->port_name[0], 8);
3272 + bcopy((void *)&tq->node_name[0],
3273 + (void *)&ha->n_port->node_name[0], 8);
3274 + bcopy((void *)&tq->hard_addr,
3275 + (void *)&ha->n_port->d_id,
3276 + sizeof (port_id_t));
3277 + ha->n_port->d_id.b24 = d_id.b24;
3278 + }
3279 + } else if (rval == QL_SUCCESS) {
3280 + bcopy((void *)&tq->port_name[0],
3281 + (void *)&ha->n_port->port_name[0], 8);
3282 + bcopy((void *)&tq->node_name[0],
3283 + (void *)&ha->n_port->node_name[0], 8);
3284 + bcopy((void *)&tq->hard_addr,
3285 + (void *)&ha->n_port->d_id, sizeof (port_id_t));
3286 + ha->n_port->d_id.b24 = d_id.b24;
3287 +
3288 + }
3289 +
3290 + kmem_free(list, list_size);
3291 +
3292 + EL(ha, "d_id = %xh, nport_handle = %xh, tq->loop_id = %xh",
3293 + tq->d_id.b24, ha->n_port->n_port_handle, tq->loop_id);
3091 3294 }
3092 3295
3093 3296
3094 3297 /*
3095 3298 * ql_configure_hba
3096 3299 * Setup adapter context.
3097 3300 *
3098 3301 * Input:
3099 3302 * ha = adapter state pointer.
3100 3303 *
3101 3304 * Returns:
3102 3305 * ql local function return status code.
3103 3306 *
3104 3307 * Context:
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3105 3308 * Kernel context.
3106 3309 */
3107 3310 static int
3108 3311 ql_configure_hba(ql_adapter_state_t *ha)
3109 3312 {
3110 3313 uint8_t *bp;
3111 3314 int rval;
3112 3315 uint32_t state;
3113 3316 ql_mbx_data_t mr;
3114 3317
3115 - QL_PRINT_3(CE_CONT, "(%d): started\n", ha->instance);
3318 + QL_PRINT_10(ha, "started\n");
3116 3319
3117 3320 /* Get host addresses. */
3118 3321 rval = ql_get_adapter_id(ha, &mr);
3119 3322 if (rval == QL_SUCCESS) {
3120 3323 ha->topology = (uint8_t)(ha->topology &
3121 3324 ~(QL_N_PORT | QL_NL_PORT | QL_F_PORT | QL_FL_PORT));
3122 3325
3123 3326 /* Save Host d_id, alpa, loop ID. */
3124 3327 ha->loop_id = mr.mb[1];
3125 3328 ha->d_id.b.al_pa = LSB(mr.mb[2]);
3126 3329 ha->d_id.b.area = MSB(mr.mb[2]);
3127 3330 ha->d_id.b.domain = LSB(mr.mb[3]);
3331 + ha->bbcr_initial = LSB(mr.mb[15]);
3332 + ha->bbcr_runtime = MSB(mr.mb[15]);
3128 3333
3129 3334 ADAPTER_STATE_LOCK(ha);
3130 3335 ha->flags &= ~FDISC_ENABLED;
3336 + ADAPTER_STATE_UNLOCK(ha);
3131 3337
3132 3338 /* Get loop topology. */
3133 3339 switch (mr.mb[6]) {
3134 - case CNX_LOOP_NO_FABRIC:
3340 + case GID_TOP_NL_PORT:
3135 3341 ha->topology = (uint8_t)(ha->topology | QL_NL_PORT);
3342 + ha->loop_id = mr.mb[1];
3136 3343 break;
3137 - case CNX_FLPORT_IN_LOOP:
3344 + case GID_TOP_FL_PORT:
3138 3345 ha->topology = (uint8_t)(ha->topology | QL_FL_PORT);
3346 + ha->loop_id = mr.mb[1];
3139 3347 break;
3140 - case CNX_NPORT_2_NPORT_P2P:
3141 - case CNX_NPORT_2_NPORT_NO_TGT_RSP:
3348 + case GID_TOP_N_PORT:
3349 + case GID_TOP_N_PORT_NO_TGT:
3142 3350 ha->flags |= POINT_TO_POINT;
3143 3351 ha->topology = (uint8_t)(ha->topology | QL_N_PORT);
3144 - if (CFG_IST(ha, CFG_CTRL_2425)) {
3352 + ha->loop_id = 0xffff;
3353 + if (CFG_IST(ha, CFG_N2N_SUPPORT)) {
3145 3354 ql_configure_n_port_info(ha);
3146 3355 }
3147 3356 break;
3148 - case CNX_FLPORT_P2P:
3357 + case GID_TOP_F_PORT:
3149 3358 ha->flags |= POINT_TO_POINT;
3150 3359 ha->topology = (uint8_t)(ha->topology | QL_F_PORT);
3360 + ha->loop_id = 0xffff;
3151 3361
3152 3362 /* Get supported option. */
3153 - if (CFG_IST(ha, CFG_CTRL_24258081) &&
3363 + if (CFG_IST(ha, CFG_ISP_FW_TYPE_2) &&
3154 3364 mr.mb[7] & GID_FP_NPIV_SUPPORT) {
3365 + ADAPTER_STATE_LOCK(ha);
3155 3366 ha->flags |= FDISC_ENABLED;
3367 + ADAPTER_STATE_UNLOCK(ha);
3156 3368 }
3157 3369 /* Get VLAN ID, mac address */
3158 - if (CFG_IST(ha, CFG_CTRL_8081)) {
3370 + if (CFG_IST(ha, CFG_FCOE_SUPPORT)) {
3371 + ha->flags |= FDISC_ENABLED;
3159 3372 ha->fabric_params = mr.mb[7];
3160 3373 ha->fcoe_vlan_id = (uint16_t)(mr.mb[9] & 0xfff);
3161 3374 ha->fcoe_fcf_idx = mr.mb[10];
3162 - ha->fcoe_vnport_mac[0] = MSB(mr.mb[11]);
3163 - ha->fcoe_vnport_mac[1] = LSB(mr.mb[11]);
3164 - ha->fcoe_vnport_mac[2] = MSB(mr.mb[12]);
3165 - ha->fcoe_vnport_mac[3] = LSB(mr.mb[12]);
3166 - ha->fcoe_vnport_mac[4] = MSB(mr.mb[13]);
3167 - ha->fcoe_vnport_mac[5] = LSB(mr.mb[13]);
3375 + ha->fcoe_vnport_mac[5] = MSB(mr.mb[11]);
3376 + ha->fcoe_vnport_mac[4] = LSB(mr.mb[11]);
3377 + ha->fcoe_vnport_mac[3] = MSB(mr.mb[12]);
3378 + ha->fcoe_vnport_mac[2] = LSB(mr.mb[12]);
3379 + ha->fcoe_vnport_mac[1] = MSB(mr.mb[13]);
3380 + ha->fcoe_vnport_mac[0] = LSB(mr.mb[13]);
3168 3381 }
3169 3382 break;
3170 3383 default:
3171 - QL_PRINT_2(CE_CONT, "(%d,%d): UNKNOWN topology=%xh, "
3172 - "d_id=%xh\n", ha->instance, ha->vp_index, mr.mb[6],
3173 - ha->d_id.b24);
3384 + QL_PRINT_2(ha, "UNKNOWN topology=%xh, d_id=%xh\n",
3385 + mr.mb[6], ha->d_id.b24);
3174 3386 rval = QL_FUNCTION_FAILED;
3175 3387 break;
3176 3388 }
3177 - ADAPTER_STATE_UNLOCK(ha);
3178 3389
3179 - if (CFG_IST(ha, (CFG_CTRL_2300 | CFG_CTRL_6322 |
3180 - CFG_CTRL_24258081))) {
3390 + if (CFG_IST(ha, CFG_CTRL_2363 | CFG_ISP_FW_TYPE_2)) {
3181 3391 mr.mb[1] = 0;
3182 3392 mr.mb[2] = 0;
3183 3393 rval = ql_data_rate(ha, &mr);
3184 3394 if (rval != QL_SUCCESS) {
3185 3395 EL(ha, "data_rate status=%xh\n", rval);
3186 3396 state = FC_STATE_FULL_SPEED;
3187 3397 } else {
3188 3398 ha->iidma_rate = mr.mb[1];
3189 3399 if (mr.mb[1] == IIDMA_RATE_1GB) {
3190 3400 state = FC_STATE_1GBIT_SPEED;
3191 3401 } else if (mr.mb[1] == IIDMA_RATE_2GB) {
3192 3402 state = FC_STATE_2GBIT_SPEED;
3193 3403 } else if (mr.mb[1] == IIDMA_RATE_4GB) {
3194 3404 state = FC_STATE_4GBIT_SPEED;
3195 3405 } else if (mr.mb[1] == IIDMA_RATE_8GB) {
3196 3406 state = FC_STATE_8GBIT_SPEED;
3197 3407 } else if (mr.mb[1] == IIDMA_RATE_10GB) {
3198 3408 state = FC_STATE_10GBIT_SPEED;
3409 + } else if (mr.mb[1] == IIDMA_RATE_16GB) {
3410 + state = FC_STATE_16GBIT_SPEED;
3411 + } else if (mr.mb[1] == IIDMA_RATE_32GB) {
3412 + state = FC_STATE_32GBIT_SPEED;
3199 3413 } else {
3200 3414 state = 0;
3201 3415 }
3202 3416 }
3203 3417 } else {
3204 3418 ha->iidma_rate = IIDMA_RATE_1GB;
3205 3419 state = FC_STATE_FULL_SPEED;
3206 3420 }
3207 3421 ha->state = FC_PORT_STATE_MASK(ha->state) | state;
3208 3422 } else if (rval == MBS_COMMAND_ERROR) {
3209 3423 EL(ha, "mbox cmd error, rval = %xh, mr.mb[1]=%hx\n",
3210 3424 rval, mr.mb[1]);
3211 3425 }
3212 3426
3213 3427 if (rval != QL_SUCCESS) {
3214 3428 EL(ha, "failed, rval = %xh\n", rval);
3215 3429 } else {
3216 3430 bp = ha->loginparams.nport_ww_name.raw_wwn;
3217 - EL(ha, "topology=%xh, d_id=%xh, "
3431 + EL(ha, "topology=%xh, hba port id=%xh, "
3218 3432 "wwpn=%02x%02x%02x%02x%02x%02x%02x%02xh\n",
3219 3433 ha->topology, ha->d_id.b24, bp[0], bp[1],
3220 3434 bp[2], bp[3], bp[4], bp[5], bp[6], bp[7]);
3221 3435 }
3222 3436 return (rval);
3223 3437 }
3224 3438
3225 3439 /*
3226 3440 * ql_configure_device_d_id
3227 3441 * Updates device loop ID.
3228 3442 * Also adds to device queue any new devices found on private loop.
3229 3443 *
3230 3444 * Input:
3231 3445 * ha = adapter state pointer.
3232 3446 *
3233 3447 * Returns:
3234 3448 * ql local function return status code.
3235 3449 *
3236 3450 * Context:
3237 3451 * Kernel context.
3238 3452 */
3239 3453 static int
3240 3454 ql_configure_device_d_id(ql_adapter_state_t *ha)
3241 3455 {
3242 3456 port_id_t d_id;
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3243 3457 ql_link_t *link;
3244 3458 int rval;
3245 3459 int loop;
3246 3460 ql_tgt_t *tq;
3247 3461 ql_dev_id_list_t *list;
3248 3462 uint32_t list_size;
3249 3463 uint16_t index, loop_id;
3250 3464 ql_mbx_data_t mr;
3251 3465 uint8_t retries = MAX_DEVICE_LOST_RETRY;
3252 3466
3253 - QL_PRINT_3(CE_CONT, "(%d): started\n", ha->instance);
3467 + QL_PRINT_10(ha, "started\n");
3254 3468
3255 3469 list_size = sizeof (ql_dev_id_list_t) * DEVICE_LIST_ENTRIES;
3256 3470 list = kmem_zalloc(list_size, KM_SLEEP);
3257 3471 if (list == NULL) {
3258 3472 rval = QL_MEMORY_ALLOC_FAILED;
3259 3473 EL(ha, "failed, rval = %xh\n", rval);
3260 3474 return (rval);
3261 3475 }
3262 3476
3263 3477 do {
3264 3478 /*
3265 3479 * Get data from RISC code d_id list to init each device queue.
3266 3480 */
3267 3481 rval = ql_get_id_list(ha, (caddr_t)list, list_size, &mr);
3268 3482 if (rval != QL_SUCCESS) {
3269 3483 kmem_free(list, list_size);
3270 3484 EL(ha, "failed, rval = %xh\n", rval);
3271 3485 return (rval);
3272 3486 }
3273 3487
3274 - /* Acquire adapter state lock. */
3275 - ADAPTER_STATE_LOCK(ha);
3276 -
3277 - /* Mark all queues as unusable. */
3488 + /*
3489 + * Mark queues as unusable selectively.
3490 + * If the current topology is AL, only fabric tgt queues
3491 + * are marked as unusable and eventually removed.
3492 + * If the current topology is P2P, all fabric tgt queues
3493 + * are processed in ql_configure_n_port_info().
3494 + * If the current topology is Fabric, all previous created
3495 + * non-fabric device should be marked as lost and eventually
3496 + * should be removed.
3497 + */
3278 3498 for (index = 0; index < DEVICE_HEAD_LIST_SIZE; index++) {
3279 3499 for (link = ha->dev[index].first; link != NULL;
3280 3500 link = link->next) {
3281 3501 tq = link->base_address;
3282 - DEVICE_QUEUE_LOCK(tq);
3283 - if (!(tq->flags & TQF_PLOGI_PROGRS) &&
3284 - !(ha->topology & QL_N_PORT)) {
3285 - tq->loop_id = (uint16_t)
3286 - (tq->loop_id | PORT_LOST_ID);
3502 +
3503 + if (VALID_DEVICE_ID(ha, tq->loop_id)) {
3504 + DEVICE_QUEUE_LOCK(tq);
3505 + if (!(tq->flags & TQF_PLOGI_PROGRS) &&
3506 + !(ha->topology & QL_N_PORT)) {
3507 + tq->loop_id = (uint16_t)
3508 + (tq->loop_id |
3509 + PORT_LOST_ID);
3510 + }
3511 + if ((ha->topology & QL_NL_PORT) &&
3512 + (tq->flags & TQF_FABRIC_DEVICE)) {
3513 + tq->loop_id = (uint16_t)
3514 + (tq->loop_id |
3515 + PORT_LOST_ID);
3516 + }
3517 + DEVICE_QUEUE_UNLOCK(tq);
3287 3518 }
3288 - DEVICE_QUEUE_UNLOCK(tq);
3289 3519 }
3290 3520 }
3291 3521
3292 3522 /* If device not in queues add new queue. */
3293 3523 for (index = 0; index < mr.mb[1]; index++) {
3294 3524 ql_dev_list(ha, list, index, &d_id, &loop_id);
3295 3525
3296 3526 if (VALID_DEVICE_ID(ha, loop_id)) {
3527 + ADAPTER_STATE_LOCK(ha);
3297 3528 tq = ql_dev_init(ha, d_id, loop_id);
3529 + ADAPTER_STATE_UNLOCK(ha);
3298 3530 if (tq != NULL) {
3299 3531 tq->loop_id = loop_id;
3300 3532
3301 3533 /* Test for fabric device. */
3302 - if (d_id.b.domain !=
3534 + if (ha->topology & QL_F_PORT ||
3535 + d_id.b.domain !=
3303 3536 ha->d_id.b.domain ||
3304 3537 d_id.b.area != ha->d_id.b.area) {
3305 3538 tq->flags |= TQF_FABRIC_DEVICE;
3306 3539 }
3307 3540
3308 - ADAPTER_STATE_UNLOCK(ha);
3309 3541 if (ql_get_port_database(ha, tq,
3310 3542 PDF_NONE) == QL_SUCCESS) {
3311 - ADAPTER_STATE_LOCK(ha);
3312 3543 tq->loop_id = (uint16_t)
3313 3544 (tq->loop_id &
3314 3545 ~PORT_LOST_ID);
3315 - } else {
3316 - ADAPTER_STATE_LOCK(ha);
3317 3546 }
3318 3547 }
3319 3548 }
3320 3549 }
3321 3550
3322 3551 /* 24xx does not report switch devices in ID list. */
3323 - if ((CFG_IST(ha, CFG_CTRL_24258081)) &&
3324 - ha->topology & (QL_F_PORT | QL_FL_PORT)) {
3325 - d_id.b24 = 0xfffffe;
3552 + if (CFG_IST(ha, CFG_ISP_FW_TYPE_2) &&
3553 + ha->topology & QL_FABRIC_CONNECTION) {
3554 + d_id.b24 = FS_FABRIC_F_PORT;
3555 + ADAPTER_STATE_LOCK(ha);
3326 3556 tq = ql_dev_init(ha, d_id, FL_PORT_24XX_HDL);
3557 + ADAPTER_STATE_UNLOCK(ha);
3327 3558 if (tq != NULL) {
3328 3559 tq->flags |= TQF_FABRIC_DEVICE;
3329 - ADAPTER_STATE_UNLOCK(ha);
3330 3560 (void) ql_get_port_database(ha, tq, PDF_NONE);
3331 - ADAPTER_STATE_LOCK(ha);
3332 3561 }
3333 - d_id.b24 = 0xfffffc;
3562 +
3563 + d_id.b24 = FS_NAME_SERVER;
3564 + ADAPTER_STATE_LOCK(ha);
3334 3565 tq = ql_dev_init(ha, d_id, SNS_24XX_HDL);
3566 + ADAPTER_STATE_UNLOCK(ha);
3335 3567 if (tq != NULL) {
3336 3568 tq->flags |= TQF_FABRIC_DEVICE;
3337 - ADAPTER_STATE_UNLOCK(ha);
3338 3569 if (ha->vp_index != 0) {
3339 3570 (void) ql_login_fport(ha, tq,
3340 3571 SNS_24XX_HDL, LFF_NONE, NULL);
3341 3572 }
3342 3573 (void) ql_get_port_database(ha, tq, PDF_NONE);
3343 - ADAPTER_STATE_LOCK(ha);
3344 3574 }
3345 3575 }
3346 3576
3347 - /* If F_port exists, allocate queue for FL_Port. */
3348 - index = ql_alpa_to_index[0xfe];
3349 - d_id.b24 = 0;
3350 - if (ha->dev[index].first != NULL) {
3351 - tq = ql_dev_init(ha, d_id, (uint16_t)
3352 - (CFG_IST(ha, CFG_CTRL_24258081) ?
3353 - FL_PORT_24XX_HDL : FL_PORT_LOOP_ID));
3354 - if (tq != NULL) {
3355 - tq->flags |= TQF_FABRIC_DEVICE;
3356 - ADAPTER_STATE_UNLOCK(ha);
3357 - (void) ql_get_port_database(ha, tq, PDF_NONE);
3358 - ADAPTER_STATE_LOCK(ha);
3359 - }
3360 - }
3361 -
3362 3577 /* Allocate queue for broadcast. */
3363 - d_id.b24 = 0xffffff;
3578 + d_id.b24 = FS_BROADCAST;
3579 + ADAPTER_STATE_LOCK(ha);
3364 3580 (void) ql_dev_init(ha, d_id, (uint16_t)
3365 - (CFG_IST(ha, CFG_CTRL_24258081) ? BROADCAST_24XX_HDL :
3581 + (CFG_IST(ha, CFG_ISP_FW_TYPE_2) ? BROADCAST_24XX_HDL :
3366 3582 IP_BROADCAST_LOOP_ID));
3583 + ADAPTER_STATE_UNLOCK(ha);
3367 3584
3368 - /* Check for any devices lost. */
3585 + /*
3586 + * Topology change (fabric<->p2p),(fabric<->al)
3587 + * (al<->p2p) have to be taken care of.
3588 + */
3369 3589 loop = FALSE;
3370 3590 for (index = 0; index < DEVICE_HEAD_LIST_SIZE; index++) {
3371 - for (link = ha->dev[index].first; link != NULL;
3372 - link = link->next) {
3373 - tq = link->base_address;
3591 + ql_update_dev(ha, index);
3592 + }
3374 3593
3375 - if ((tq->loop_id & PORT_LOST_ID) &&
3376 - !(tq->flags & (TQF_INITIATOR_DEVICE |
3377 - TQF_FABRIC_DEVICE))) {
3378 - loop = TRUE;
3379 - }
3380 - }
3594 + if ((ha->topology & QL_NL_PORT) && (mr.mb[1] != 0)) {
3595 + loop = FALSE;
3596 + } else if (mr.mb[1] == 0 && !(ha->topology & QL_F_PORT)) {
3597 + loop = TRUE;
3381 3598 }
3382 3599
3383 - /* Release adapter state lock. */
3384 - ADAPTER_STATE_UNLOCK(ha);
3385 -
3386 3600 /* Give devices time to recover. */
3387 3601 if (loop == TRUE) {
3388 3602 drv_usecwait(1000000);
3389 3603 }
3390 3604 } while (retries-- && loop == TRUE &&
3391 3605 !(ha->pha->task_daemon_flags & LOOP_RESYNC_NEEDED));
3392 3606
3393 3607 kmem_free(list, list_size);
3394 3608
3395 3609 if (rval != QL_SUCCESS) {
3396 3610 EL(ha, "failed=%xh\n", rval);
3397 3611 } else {
3398 3612 /*EMPTY*/
3399 - QL_PRINT_3(CE_CONT, "(%d): done\n", ha->instance);
3613 + QL_PRINT_10(ha, "done\n");
3400 3614 }
3401 3615
3402 3616 return (rval);
3403 3617 }
3404 3618
3405 3619 /*
3406 3620 * ql_dev_list
3407 3621 * Gets device d_id and loop ID from firmware device list.
3408 3622 *
3409 3623 * Input:
3410 3624 * ha: adapter state pointer.
3411 3625 * list device list pointer.
3412 3626 * index: list index of device data.
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3413 3627 * d_id: pointer for d_id data.
3414 3628 * id: pointer for loop ID.
3415 3629 *
3416 3630 * Context:
3417 3631 * Kernel context.
3418 3632 */
3419 3633 void
3420 3634 ql_dev_list(ql_adapter_state_t *ha, union ql_dev_id_list *list,
3421 3635 uint32_t index, port_id_t *d_id, uint16_t *id)
3422 3636 {
3423 - if (CFG_IST(ha, CFG_CTRL_24258081)) {
3637 + if (CFG_IST(ha, CFG_ISP_FW_TYPE_2)) {
3424 3638 struct ql_24_dev_id *list24 = (struct ql_24_dev_id *)list;
3425 3639
3426 3640 d_id->b.al_pa = list24[index].al_pa;
3427 3641 d_id->b.area = list24[index].area;
3428 3642 d_id->b.domain = list24[index].domain;
3429 3643 *id = CHAR_TO_SHORT(list24[index].n_port_hdl_l,
3430 3644 list24[index].n_port_hdl_h);
3431 3645
3432 3646 } else if (CFG_IST(ha, CFG_EXT_FW_INTERFACE)) {
3433 3647 struct ql_ex_dev_id *list23 = (struct ql_ex_dev_id *)list;
3434 3648
3435 3649 d_id->b.al_pa = list23[index].al_pa;
3436 3650 d_id->b.area = list23[index].area;
3437 3651 d_id->b.domain = list23[index].domain;
3438 3652 *id = CHAR_TO_SHORT(list23[index].loop_id_l,
3439 3653 list23[index].loop_id_h);
3440 3654
3441 3655 } else {
3442 3656 struct ql_dev_id *list22 = (struct ql_dev_id *)list;
3443 3657
3444 3658 d_id->b.al_pa = list22[index].al_pa;
3445 3659 d_id->b.area = list22[index].area;
3446 3660 d_id->b.domain = list22[index].domain;
3447 3661 *id = (uint16_t)list22[index].loop_id;
3448 3662 }
3449 3663 }
3450 3664
3451 3665 /*
3452 3666 * ql_configure_fabric
3453 3667 * Setup fabric context.
3454 3668 *
3455 3669 * Input:
3456 3670 * ha = adapter state pointer.
3457 3671 *
3458 3672 * Returns:
3459 3673 * ql local function return status code.
3460 3674 *
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3461 3675 * Context:
3462 3676 * Kernel context.
3463 3677 */
3464 3678 static int
3465 3679 ql_configure_fabric(ql_adapter_state_t *ha)
3466 3680 {
3467 3681 port_id_t d_id;
3468 3682 ql_tgt_t *tq;
3469 3683 int rval = QL_FUNCTION_FAILED;
3470 3684
3471 - QL_PRINT_3(CE_CONT, "(%d): started\n", ha->instance);
3685 + QL_PRINT_10(ha, "started\n");
3472 3686
3473 - ha->topology = (uint8_t)(ha->topology & ~QL_SNS_CONNECTION);
3474 -
3475 - /* Test switch fabric controller present. */
3476 - d_id.b24 = FS_FABRIC_F_PORT;
3477 - tq = ql_d_id_to_queue(ha, d_id);
3478 - if (tq != NULL) {
3479 - /* Get port/node names of F_Port. */
3480 - (void) ql_get_port_database(ha, tq, PDF_NONE);
3481 -
3482 - d_id.b24 = FS_NAME_SERVER;
3687 + if (ha->topology & QL_FABRIC_CONNECTION) {
3688 + /* Test switch fabric controller present. */
3689 + d_id.b24 = FS_FABRIC_F_PORT;
3483 3690 tq = ql_d_id_to_queue(ha, d_id);
3484 3691 if (tq != NULL) {
3692 + /* Get port/node names of F_Port. */
3485 3693 (void) ql_get_port_database(ha, tq, PDF_NONE);
3486 - ha->topology = (uint8_t)
3487 - (ha->topology | QL_SNS_CONNECTION);
3488 - rval = QL_SUCCESS;
3694 +
3695 + d_id.b24 = FS_NAME_SERVER;
3696 + tq = ql_d_id_to_queue(ha, d_id);
3697 + if (tq != NULL) {
3698 + (void) ql_get_port_database(ha, tq, PDF_NONE);
3699 + rval = QL_SUCCESS;
3700 + }
3489 3701 }
3490 3702 }
3491 3703
3492 3704 if (rval != QL_SUCCESS) {
3493 3705 EL(ha, "failed=%xh\n", rval);
3494 3706 } else {
3495 3707 /*EMPTY*/
3496 - QL_PRINT_3(CE_CONT, "(%d): done\n", ha->instance);
3708 + QL_PRINT_10(ha, "done\n");
3497 3709 }
3498 3710 return (rval);
3499 3711 }
3500 3712
3501 3713 /*
3502 3714 * ql_reset_chip
3503 3715 * Reset ISP chip.
3504 3716 *
3505 3717 * Input:
3506 3718 * ha = adapter block pointer.
3507 3719 * All activity on chip must be already stopped.
3508 3720 * ADAPTER_STATE_LOCK must be released.
3509 3721 *
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3510 3722 * Context:
3511 3723 * Interrupt or Kernel context, no mailbox commands allowed.
3512 3724 */
3513 3725 void
3514 3726 ql_reset_chip(ql_adapter_state_t *vha)
3515 3727 {
3516 3728 uint32_t cnt;
3517 3729 uint16_t cmd;
3518 3730 ql_adapter_state_t *ha = vha->pha;
3519 3731
3520 - QL_PRINT_3(CE_CONT, "(%d): started\n", ha->instance);
3732 + QL_PRINT_10(ha, "started\n");
3521 3733
3522 3734 /*
3523 3735 * accessing pci space while not powered can cause panic's
3524 3736 * on some platforms (i.e. Sunblade 1000's)
3525 3737 */
3526 3738 if (ha->power_level == PM_LEVEL_D3) {
3527 - QL_PRINT_2(CE_CONT, "(%d): Low Power exit\n", ha->instance);
3739 + QL_PRINT_2(ha, "Low Power exit\n");
3528 3740 return;
3529 3741 }
3530 3742
3743 + /* Disable ISP interrupts. */
3744 + ql_disable_intr(ha);
3745 +
3531 3746 /* Reset all outbound mailbox registers */
3532 3747 for (cnt = 0; cnt < ha->reg_off->mbox_cnt; cnt++) {
3533 3748 WRT16_IO_REG(ha, mailbox_in[cnt], (uint16_t)0);
3534 3749 }
3535 3750
3536 - if (CFG_IST(ha, CFG_CTRL_8021)) {
3751 + if (CFG_IST(ha, CFG_CTRL_82XX)) {
3537 3752 ha->timeout_cnt = 0;
3538 3753 ql_8021_reset_chip(ha);
3539 - QL_PRINT_3(CE_CONT, "(%d): 8021 exit\n", ha->instance);
3754 + QL_PRINT_10(ha, "8021 exit\n");
3540 3755 return;
3541 3756 }
3542 3757
3543 - /* Disable ISP interrupts. */
3544 - WRT16_IO_REG(ha, ictrl, 0);
3545 - ADAPTER_STATE_LOCK(ha);
3546 - ha->flags &= ~INTERRUPTS_ENABLED;
3547 - ADAPTER_STATE_UNLOCK(ha);
3548 -
3549 - if (CFG_IST(ha, CFG_CTRL_242581)) {
3550 - RD32_IO_REG(ha, ictrl);
3758 + if (CFG_IST(ha, CFG_ISP_FW_TYPE_2)) {
3551 3759 ql_reset_24xx_chip(ha);
3552 - QL_PRINT_3(CE_CONT, "(%d): 24xx exit\n", ha->instance);
3760 + QL_PRINT_10(ha, "24xx exit\n");
3553 3761 return;
3554 3762 }
3763 + QL_PRINT_10(ha, "CFG_ISP_FW_TYPE_1 reset\n");
3555 3764
3556 3765 /*
3557 3766 * We are going to reset the chip in case of 2300. That might cause
3558 3767 * a PBM ERR if a DMA transaction is in progress. One way of
3559 3768 * avoiding it is to disable Bus Master operation before we start
3560 3769 * the reset activity.
3561 3770 */
3562 3771 cmd = (uint16_t)ql_pci_config_get16(ha, PCI_CONF_COMM);
3563 3772 cmd = (uint16_t)(cmd & ~PCI_COMM_ME);
3564 3773 ql_pci_config_put16(ha, PCI_CONF_COMM, cmd);
3565 3774
3566 3775 /* Pause RISC. */
3567 3776 WRT16_IO_REG(ha, hccr, HC_PAUSE_RISC);
3568 3777 for (cnt = 0; cnt < 30000; cnt++) {
3569 3778 if ((RD16_IO_REG(ha, hccr) & HC_RISC_PAUSE) != 0) {
3570 3779 break;
3571 3780 }
3572 3781 drv_usecwait(MILLISEC);
3573 3782 }
3574 3783
3575 3784 /*
3576 3785 * A call to ql_isr() can still happen through
3577 3786 * ql_mailbox_command(). So Mark that we are/(will-be)
3578 3787 * running from rom code now.
3579 3788 */
3580 3789 TASK_DAEMON_LOCK(ha);
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3581 3790 ha->task_daemon_flags &= ~(FIRMWARE_UP | FIRMWARE_LOADED);
3582 3791 TASK_DAEMON_UNLOCK(ha);
3583 3792
3584 3793 /* Select FPM registers. */
3585 3794 WRT16_IO_REG(ha, ctrl_status, 0x20);
3586 3795
3587 3796 /* FPM Soft Reset. */
3588 3797 WRT16_IO_REG(ha, fpm_diag_config, 0x100);
3589 3798
3590 3799 /* Toggle FPM reset for 2300 */
3591 - if (CFG_IST(ha, (CFG_CTRL_2300 | CFG_CTRL_6322))) {
3800 + if (CFG_IST(ha, CFG_CTRL_2363)) {
3592 3801 WRT16_IO_REG(ha, fpm_diag_config, 0);
3593 3802 }
3594 3803
3595 3804 /* Select frame buffer registers. */
3596 3805 WRT16_IO_REG(ha, ctrl_status, 0x10);
3597 3806
3598 3807 /* Reset frame buffer FIFOs. */
3599 - if (CFG_IST(ha, (CFG_CTRL_2300 | CFG_CTRL_6322))) {
3808 + if (CFG_IST(ha, CFG_CTRL_2363)) {
3600 3809 WRT16_IO_REG(ha, fb_cmd, 0x00fc);
3601 3810 /* read back fb_cmd until zero or 3 seconds max */
3602 3811 for (cnt = 0; cnt < 300000; cnt++) {
3603 3812 if ((RD16_IO_REG(ha, fb_cmd) & 0xff) == 0) {
3604 3813 break;
3605 3814 }
3606 3815 drv_usecwait(10);
3607 3816 }
3608 - } else {
3817 + } else {
3609 3818 WRT16_IO_REG(ha, fb_cmd, 0xa000);
3610 3819 }
3611 3820
3612 3821 /* Select RISC module registers. */
3613 3822 WRT16_IO_REG(ha, ctrl_status, 0);
3614 3823
3615 3824 /* Reset RISC module. */
3616 3825 WRT16_IO_REG(ha, hccr, HC_RESET_RISC);
3617 3826
3618 3827 /* Reset ISP semaphore. */
3619 3828 WRT16_IO_REG(ha, semaphore, 0);
3620 3829
3621 3830 /* Release RISC module. */
3622 3831 WRT16_IO_REG(ha, hccr, HC_RELEASE_RISC);
3623 3832
3624 3833 /* Insure mailbox registers are free. */
3625 3834 WRT16_IO_REG(ha, hccr, HC_CLR_RISC_INT);
3626 3835 WRT16_IO_REG(ha, hccr, HC_CLR_HOST_INT);
3627 3836
3628 3837 /* clear the mailbox command pointer. */
3629 - ql_clear_mcp(ha);
3838 + INTR_LOCK(ha);
3839 + ha->mcp = NULL;
3840 + INTR_UNLOCK(ha);
3630 3841
3842 + MBX_REGISTER_LOCK(ha);
3631 3843 ha->mailbox_flags = (uint8_t)(ha->mailbox_flags &
3632 3844 ~(MBX_BUSY_FLG | MBX_WANT_FLG | MBX_ABORT | MBX_INTERRUPT));
3845 + MBX_REGISTER_UNLOCK(ha);
3633 3846
3634 3847 /* Bus Master is disabled so chip reset is safe. */
3635 - if (CFG_IST(ha, (CFG_CTRL_2300 | CFG_CTRL_6322))) {
3848 + if (CFG_IST(ha, CFG_CTRL_2363)) {
3636 3849 WRT16_IO_REG(ha, ctrl_status, ISP_RESET);
3637 3850 drv_usecwait(MILLISEC);
3638 3851
3639 3852 /* Wait for reset to finish. */
3640 3853 for (cnt = 0; cnt < 30000; cnt++) {
3641 3854 if ((RD16_IO_REG(ha, ctrl_status) & ISP_RESET) == 0) {
3642 3855 break;
3643 3856 }
3644 3857 drv_usecwait(MILLISEC);
3645 3858 }
3646 3859 }
3647 3860
3648 3861 /* Wait for RISC to recover from reset. */
3649 3862 for (cnt = 0; cnt < 30000; cnt++) {
3650 - if (RD16_IO_REG(ha, mailbox_out[0]) != MBS_BUSY) {
3863 + if (RD16_IO_REG(ha, mailbox_out[0]) != MBS_ROM_BUSY) {
3651 3864 break;
3652 3865 }
3653 3866 drv_usecwait(MILLISEC);
3654 3867 }
3655 3868
3656 3869 /* restore bus master */
3657 3870 cmd = (uint16_t)ql_pci_config_get16(ha, PCI_CONF_COMM);
3658 3871 cmd = (uint16_t)(cmd | PCI_COMM_ME);
3659 3872 ql_pci_config_put16(ha, PCI_CONF_COMM, cmd);
3660 3873
3661 3874 /* Disable RISC pause on FPM parity error. */
3662 3875 WRT16_IO_REG(ha, hccr, HC_DISABLE_PARITY_PAUSE);
3663 3876
3877 + if (CFG_IST(ha, CFG_CTRL_22XX) &&
3878 + RD16_IO_REG(ha, mailbox_out[7]) == 4) {
3879 + ha->fw_transfer_size = 128;
3880 + }
3881 +
3664 3882 /* Initialize probe registers */
3665 3883 if (CFG_IST(ha, CFG_SBUS_CARD)) {
3666 3884 /* Pause RISC. */
3667 3885 WRT16_IO_REG(ha, hccr, HC_PAUSE_RISC);
3668 3886 for (cnt = 0; cnt < 30000; cnt++) {
3669 3887 if ((RD16_IO_REG(ha, hccr) & HC_RISC_PAUSE) != 0) {
3670 3888 break;
3671 3889 } else {
3672 3890 drv_usecwait(MILLISEC);
3673 3891 }
3674 3892 }
3675 3893
3676 3894 /* Select FPM registers. */
3677 3895 WRT16_IO_REG(ha, ctrl_status, 0x30);
3678 3896
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3679 3897 /* Set probe register */
3680 3898 WRT16_IO_REG(ha, mailbox_in[23], 0x204c);
3681 3899
3682 3900 /* Select RISC module registers. */
3683 3901 WRT16_IO_REG(ha, ctrl_status, 0);
3684 3902
3685 3903 /* Release RISC module. */
3686 3904 WRT16_IO_REG(ha, hccr, HC_RELEASE_RISC);
3687 3905 }
3688 3906
3689 - QL_PRINT_3(CE_CONT, "(%d): done\n", ha->instance);
3907 + QL_PRINT_10(ha, "done\n");
3690 3908 }
3691 3909
3692 3910 /*
3693 3911 * ql_reset_24xx_chip
3694 3912 * Reset ISP24xx chip.
3695 3913 *
3696 3914 * Input:
3697 3915 * ha = adapter block pointer.
3698 3916 * All activity on chip must be already stopped.
3699 3917 *
3700 3918 * Context:
3701 3919 * Interrupt or Kernel context, no mailbox commands allowed.
3702 3920 */
3703 -void
3921 +static void
3704 3922 ql_reset_24xx_chip(ql_adapter_state_t *ha)
3705 3923 {
3706 3924 uint32_t timer, stat;
3707 3925
3926 + QL_PRINT_10(ha, "started\n");
3927 +
3708 3928 /* Shutdown DMA. */
3709 - WRT32_IO_REG(ha, ctrl_status, DMA_SHUTDOWN | MWB_4096_BYTES);
3929 + if (CFG_IST(ha, CFG_MWB_4096_SUPPORT)) {
3930 + WRT32_IO_REG(ha, ctrl_status, DMA_SHUTDOWN | MWB_4096_BYTES);
3931 + } else {
3932 + WRT32_IO_REG(ha, ctrl_status, DMA_SHUTDOWN);
3933 + }
3710 3934
3711 3935 /* Wait for DMA to stop. */
3712 3936 for (timer = 0; timer < 30000; timer++) {
3713 3937 if ((RD32_IO_REG(ha, ctrl_status) & DMA_ACTIVE) == 0) {
3714 3938 break;
3715 3939 }
3716 3940 drv_usecwait(100);
3717 3941 }
3718 3942
3719 3943 /* Stop the firmware. */
3720 3944 WRT32_IO_REG(ha, hccr, HC24_CLR_RISC_INT);
3721 3945 WRT16_IO_REG(ha, mailbox_in[0], MBC_STOP_FIRMWARE);
3946 + WRT16_IO_REG(ha, mailbox_in[1], 0);
3947 + WRT16_IO_REG(ha, mailbox_in[2], 0);
3948 + WRT16_IO_REG(ha, mailbox_in[3], 0);
3949 + WRT16_IO_REG(ha, mailbox_in[4], 0);
3950 + WRT16_IO_REG(ha, mailbox_in[5], 0);
3951 + WRT16_IO_REG(ha, mailbox_in[6], 0);
3952 + WRT16_IO_REG(ha, mailbox_in[7], 0);
3953 + WRT16_IO_REG(ha, mailbox_in[8], 0);
3722 3954 WRT32_IO_REG(ha, hccr, HC24_SET_HOST_INT);
3723 3955 for (timer = 0; timer < 30000; timer++) {
3724 3956 stat = RD32_IO_REG(ha, risc2host);
3725 3957 if (stat & BIT_15) {
3726 3958 if ((stat & 0xff) < 0x12) {
3727 3959 WRT32_IO_REG(ha, hccr, HC24_CLR_RISC_INT);
3728 3960 break;
3729 3961 }
3730 3962 WRT32_IO_REG(ha, hccr, HC24_CLR_RISC_INT);
3731 3963 }
3732 3964 drv_usecwait(100);
3733 3965 }
3734 3966
3735 3967 /* Reset the chip. */
3736 - WRT32_IO_REG(ha, ctrl_status, ISP_RESET | DMA_SHUTDOWN |
3737 - MWB_4096_BYTES);
3968 + WRT32_IO_REG(ha, ctrl_status, ISP_RESET);
3738 3969 drv_usecwait(100);
3739 3970
3740 - /* Wait for idle status from ROM firmware. */
3741 - for (timer = 0; timer < 30000; timer++) {
3742 - if (RD16_IO_REG(ha, mailbox_out[0]) == 0) {
3743 - break;
3971 + /* Wait for RISC to recover from reset. */
3972 + for (timer = 30000; timer; timer--) {
3973 + ha->rom_status = RD16_IO_REG(ha, mailbox_out[0]);
3974 + if (CFG_IST(ha, CFG_CTRL_278083)) {
3975 + /* Wait for RISC to recover from reset. */
3976 + if ((ha->rom_status & MBS_ROM_STATUS_MASK) !=
3977 + MBS_ROM_BUSY) {
3978 + break;
3979 + }
3980 + } else {
3981 + /* Wait for idle status from ROM firmware. */
3982 + if (ha->rom_status == MBS_ROM_IDLE) {
3983 + break;
3984 + }
3744 3985 }
3745 3986 drv_usecwait(100);
3746 3987 }
3747 3988
3748 3989 /* Wait for reset to finish. */
3749 3990 for (timer = 0; timer < 30000; timer++) {
3750 3991 if ((RD32_IO_REG(ha, ctrl_status) & ISP_RESET) == 0) {
3751 3992 break;
3752 3993 }
3753 3994 drv_usecwait(100);
3754 3995 }
3755 3996
3997 + ha->adapter_stats->revlvl.isp2200 = RD16_IO_REG(ha, mailbox_out[4]);
3998 + ha->adapter_stats->revlvl.risc = RD16_IO_REG(ha, mailbox_out[5]);
3999 + ha->adapter_stats->revlvl.frmbfr = RD16_IO_REG(ha, mailbox_out[6]);
4000 + ha->adapter_stats->revlvl.riscrom = RD16_IO_REG(ha, mailbox_out[8]);
4001 +
4002 + /* Insure mailbox registers are free. */
4003 + WRT32_IO_REG(ha, hccr, HC24_CLR_RISC_INT);
4004 + WRT32_IO_REG(ha, hccr, HC24_CLR_HOST_INT);
4005 +
3756 4006 /* clear the mailbox command pointer. */
3757 - ql_clear_mcp(ha);
4007 + INTR_LOCK(ha);
4008 + ha->mcp = NULL;
4009 + INTR_UNLOCK(ha);
3758 4010
3759 4011 /* Insure mailbox registers are free. */
4012 + MBX_REGISTER_LOCK(ha);
3760 4013 ha->mailbox_flags = (uint8_t)(ha->mailbox_flags &
3761 4014 ~(MBX_BUSY_FLG | MBX_WANT_FLG | MBX_ABORT | MBX_INTERRUPT));
4015 + MBX_REGISTER_UNLOCK(ha);
3762 4016
3763 4017 if (ha->flags & MPI_RESET_NEEDED) {
3764 4018 WRT32_IO_REG(ha, hccr, HC24_CLR_RISC_INT);
3765 4019 WRT16_IO_REG(ha, mailbox_in[0], MBC_RESTART_MPI);
3766 4020 WRT32_IO_REG(ha, hccr, HC24_SET_HOST_INT);
3767 4021 for (timer = 0; timer < 30000; timer++) {
3768 4022 stat = RD32_IO_REG(ha, risc2host);
3769 4023 if (stat & BIT_15) {
3770 4024 if ((stat & 0xff) < 0x12) {
3771 4025 WRT32_IO_REG(ha, hccr,
3772 4026 HC24_CLR_RISC_INT);
3773 4027 break;
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3774 4028 }
3775 4029 WRT32_IO_REG(ha, hccr, HC24_CLR_RISC_INT);
3776 4030 }
3777 4031 drv_usecwait(100);
3778 4032 }
3779 4033 ADAPTER_STATE_LOCK(ha);
3780 4034 ha->flags &= ~MPI_RESET_NEEDED;
3781 4035 ADAPTER_STATE_UNLOCK(ha);
3782 4036 }
3783 4037
3784 - /*
3785 - * Set flash write-protection.
3786 - */
3787 - if ((ha->flags & ONLINE) == 0) {
3788 - ql_24xx_protect_flash(ha);
3789 - }
4038 + QL_PRINT_10(ha, "done\n");
3790 4039 }
3791 4040
3792 4041 /*
3793 - * ql_clear_mcp
3794 - * Carefully clear the mailbox command pointer in the ha struct.
3795 - *
3796 - * Input:
3797 - * ha = adapter block pointer.
3798 - *
3799 - * Context:
3800 - * Interrupt or Kernel context, no mailbox commands allowed.
3801 - */
3802 -
3803 -static void
3804 -ql_clear_mcp(ql_adapter_state_t *ha)
3805 -{
3806 - uint32_t cnt;
3807 -
3808 - /* Don't null ha->mcp without the lock, but don't hang either. */
3809 - if (MBX_REGISTER_LOCK_OWNER(ha) == curthread) {
3810 - ha->mcp = NULL;
3811 - } else {
3812 - for (cnt = 0; cnt < 300000; cnt++) {
3813 - if (TRY_MBX_REGISTER_LOCK(ha) != 0) {
3814 - ha->mcp = NULL;
3815 - MBX_REGISTER_UNLOCK(ha);
3816 - break;
3817 - } else {
3818 - drv_usecwait(10);
3819 - }
3820 - }
3821 - }
3822 -}
3823 -
3824 -
3825 -/*
3826 4042 * ql_abort_isp
3827 4043 * Resets ISP and aborts all outstanding commands.
3828 4044 *
3829 4045 * Input:
3830 4046 * ha = adapter state pointer.
3831 4047 * DEVICE_QUEUE_LOCK must be released.
3832 4048 *
3833 4049 * Returns:
3834 4050 * ql local function return status code.
3835 4051 *
3836 4052 * Context:
3837 4053 * Kernel context.
3838 4054 */
3839 4055 int
3840 4056 ql_abort_isp(ql_adapter_state_t *vha)
3841 4057 {
3842 4058 ql_link_t *link, *link2;
3843 - ddi_devstate_t state;
3844 4059 uint16_t index;
3845 4060 ql_tgt_t *tq;
3846 4061 ql_lun_t *lq;
3847 - ql_srb_t *sp;
3848 4062 int rval = QL_SUCCESS;
3849 4063 ql_adapter_state_t *ha = vha->pha;
4064 + boolean_t abort_loop_down = B_FALSE;
3850 4065
3851 - QL_PRINT_2(CE_CONT, "(%d,%d): started\n", ha->instance, ha->vp_index);
4066 + QL_PRINT_2(ha, "started\n");
3852 4067
3853 4068 TASK_DAEMON_LOCK(ha);
3854 4069 ha->task_daemon_flags &= ~ISP_ABORT_NEEDED;
3855 4070 if (ha->task_daemon_flags & ABORT_ISP_ACTIVE ||
3856 4071 (ha->flags & ONLINE) == 0 || ha->flags & ADAPTER_SUSPENDED) {
3857 4072 TASK_DAEMON_UNLOCK(ha);
4073 + QL_PRINT_2(ha, "already active or suspended tdf=0x%llx, "
4074 + "flgs=0x%llx\n", ha->task_daemon_flags, ha->flags);
3858 4075 return (rval);
3859 4076 }
3860 4077
3861 4078 ha->task_daemon_flags |= ABORT_ISP_ACTIVE;
3862 - ha->task_daemon_flags &= ~(RESET_MARKER_NEEDED | FIRMWARE_UP |
4079 + ha->task_daemon_flags &= ~(MARKER_NEEDED | FIRMWARE_UP |
3863 4080 FIRMWARE_LOADED);
3864 4081 for (vha = ha; vha != NULL; vha = vha->vp_next) {
3865 - vha->task_daemon_flags |= LOOP_DOWN;
3866 4082 vha->task_daemon_flags &= ~(COMMAND_WAIT_NEEDED |
3867 4083 LOOP_RESYNC_NEEDED);
4084 + vha->task_daemon_flags |= LOOP_DOWN;
4085 + if (vha->loop_down_timer == LOOP_DOWN_TIMER_OFF) {
4086 + abort_loop_down = B_TRUE;
4087 + vha->loop_down_timer = LOOP_DOWN_TIMER_START;
4088 + }
3868 4089 }
3869 4090
3870 4091 TASK_DAEMON_UNLOCK(ha);
3871 4092
4093 + ql_port_state(ha, FC_STATE_OFFLINE, FC_STATE_CHANGE);
4094 +
3872 4095 if (ha->mailbox_flags & MBX_BUSY_FLG) {
3873 4096 /* Acquire mailbox register lock. */
3874 4097 MBX_REGISTER_LOCK(ha);
3875 4098
3876 4099 /* Wake up mailbox box routine. */
3877 4100 ha->mailbox_flags = (uint8_t)(ha->mailbox_flags | MBX_ABORT);
3878 4101 cv_broadcast(&ha->cv_mbx_intr);
3879 4102
3880 4103 /* Release mailbox register lock. */
3881 4104 MBX_REGISTER_UNLOCK(ha);
3882 4105
3883 4106 /* Wait for mailbox. */
3884 4107 for (index = 100; index &&
3885 4108 ha->mailbox_flags & MBX_ABORT; index--) {
3886 - drv_usecwait(50000);
4109 + delay(1);
3887 4110 }
3888 4111 }
3889 4112
3890 4113 /* Wait for commands to end gracefully if not in panic. */
3891 4114 if (ha->flags & PARITY_ERROR) {
3892 4115 ADAPTER_STATE_LOCK(ha);
3893 4116 ha->flags &= ~PARITY_ERROR;
3894 4117 ADAPTER_STATE_UNLOCK(ha);
3895 4118 } else if (ddi_in_panic() == 0) {
3896 4119 ql_cmd_wait(ha);
3897 4120 }
3898 4121
4122 + rval = QL_ABORTED;
4123 + if (ha->flags & FW_DUMP_NEEDED) {
4124 + rval = ql_binary_fw_dump(ha, TRUE);
4125 + }
4126 +
3899 4127 /* Shutdown IP. */
3900 4128 if (ha->flags & IP_INITIALIZED) {
3901 4129 (void) ql_shutdown_ip(ha);
3902 4130 }
3903 4131
4132 + if (ha->task_daemon_flags & ISP_ABORT_NEEDED) {
4133 + TASK_DAEMON_LOCK(ha);
4134 + ha->task_daemon_flags &= ~ISP_ABORT_NEEDED;
4135 + TASK_DAEMON_UNLOCK(ha);
4136 + }
4137 +
3904 4138 /* Reset the chip. */
3905 - ql_reset_chip(ha);
4139 + if (rval != QL_SUCCESS) {
4140 + rval = QL_SUCCESS;
4141 + ql_reset_chip(ha);
4142 + }
3906 4143
3907 4144 /*
3908 4145 * Even though we have waited for outstanding commands to complete,
3909 4146 * except for ones marked SRB_COMMAND_TIMEOUT, and reset the ISP,
3910 4147 * there could still be an interrupt thread active. The interrupt
3911 4148 * lock will prevent us from getting an sp from the outstanding
3912 4149 * cmds array that the ISR may be using.
3913 4150 */
3914 4151
3915 4152 /* Place all commands in outstanding cmd list on device queue. */
3916 - for (index = 1; index < MAX_OUTSTANDING_COMMANDS; index++) {
3917 - REQUEST_RING_LOCK(ha);
3918 - INTR_LOCK(ha);
3919 - if ((link = ha->pending_cmds.first) != NULL) {
3920 - sp = link->base_address;
3921 - ql_remove_link(&ha->pending_cmds, &sp->cmd);
4153 + ql_requeue_all_cmds(ha);
3922 4154
3923 - REQUEST_RING_UNLOCK(ha);
3924 - index = 0;
3925 - } else {
3926 - REQUEST_RING_UNLOCK(ha);
3927 - if ((sp = ha->outstanding_cmds[index]) == NULL) {
3928 - INTR_UNLOCK(ha);
3929 - continue;
3930 - }
3931 - }
3932 -
3933 - /*
3934 - * It's not obvious but the index for commands pulled from
3935 - * pending will be zero and that entry in the outstanding array
3936 - * is not used so nulling it is "no harm, no foul".
3937 - */
3938 -
3939 - ha->outstanding_cmds[index] = NULL;
3940 - sp->handle = 0;
3941 - sp->flags &= ~SRB_IN_TOKEN_ARRAY;
3942 -
3943 - INTR_UNLOCK(ha);
3944 -
3945 - /* If command timeout. */
3946 - if (sp->flags & SRB_COMMAND_TIMEOUT) {
3947 - sp->pkt->pkt_reason = CS_TIMEOUT;
3948 - sp->flags &= ~SRB_RETRY;
3949 - sp->flags |= SRB_ISP_COMPLETED;
3950 -
3951 - /* Call done routine to handle completion. */
3952 - ql_done(&sp->cmd);
3953 - continue;
3954 - }
3955 -
3956 - /* Acquire target queue lock. */
3957 - lq = sp->lun_queue;
3958 - tq = lq->target_queue;
3959 - DEVICE_QUEUE_LOCK(tq);
3960 -
3961 - /* Reset watchdog time. */
3962 - sp->wdg_q_time = sp->init_wdg_q_time;
3963 -
3964 - /* Place request back on top of device queue. */
3965 - sp->flags &= ~(SRB_ISP_STARTED | SRB_ISP_COMPLETED |
3966 - SRB_RETRY);
3967 -
3968 - ql_add_link_t(&lq->cmd, &sp->cmd);
3969 - sp->flags |= SRB_IN_DEVICE_QUEUE;
3970 -
3971 - /* Release target queue lock. */
3972 - DEVICE_QUEUE_UNLOCK(tq);
3973 - }
3974 -
3975 4155 /*
3976 4156 * Clear per LUN active count, because there should not be
3977 4157 * any IO outstanding at this time.
3978 4158 */
3979 4159 for (vha = ha; vha != NULL; vha = vha->vp_next) {
3980 4160 for (index = 0; index < DEVICE_HEAD_LIST_SIZE; index++) {
3981 4161 link = vha->dev[index].first;
3982 4162 while (link != NULL) {
3983 4163 tq = link->base_address;
3984 4164 link = link->next;
3985 4165 DEVICE_QUEUE_LOCK(tq);
3986 4166 tq->outcnt = 0;
3987 4167 tq->flags &= ~TQF_QUEUE_SUSPENDED;
3988 4168 for (link2 = tq->lun_queues.first;
3989 4169 link2 != NULL; link2 = link2->next) {
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3990 4170 lq = link2->base_address;
3991 4171 lq->lun_outcnt = 0;
3992 4172 lq->flags &= ~LQF_UNTAGGED_PENDING;
3993 4173 }
3994 4174 DEVICE_QUEUE_UNLOCK(tq);
3995 4175 }
3996 4176 }
3997 4177 }
3998 4178
3999 4179 if ((rval = ql_check_isp_firmware(ha)) != QL_SUCCESS) {
4000 - if ((rval = ql_chip_diag(ha)) == QL_SUCCESS) {
4180 + if (ha->dev_state != NX_DEV_READY) {
4181 + EL(ha, "dev_state not ready\n");
4182 + } else if ((rval = ql_mbx_wrap_test(ha, NULL)) == QL_SUCCESS) {
4001 4183 rval = ql_load_isp_firmware(ha);
4002 4184 }
4003 4185 }
4004 4186
4005 4187 if (rval == QL_SUCCESS && (rval = ql_set_cache_line(ha)) ==
4006 4188 QL_SUCCESS && (rval = ql_init_rings(ha)) == QL_SUCCESS &&
4007 4189 (rval = ql_fw_ready(ha, 10)) == QL_SUCCESS) {
4008 4190
4191 + /* Enable ISP interrupts. */
4192 + if (!(ha->flags & INTERRUPTS_ENABLED)) {
4193 + ql_enable_intr(ha);
4194 + }
4195 +
4009 4196 /* If reset abort needed that may have been set. */
4010 4197 TASK_DAEMON_LOCK(ha);
4011 4198 ha->task_daemon_flags &= ~(ISP_ABORT_NEEDED |
4012 4199 ABORT_ISP_ACTIVE);
4013 4200 TASK_DAEMON_UNLOCK(ha);
4014 4201
4015 - /* Enable ISP interrupts. */
4016 - if (CFG_IST(ha, CFG_CTRL_8021)) {
4017 - ql_8021_enable_intrs(ha);
4018 - } else if (CFG_IST(ha, CFG_CTRL_242581)) {
4019 - WRT32_IO_REG(ha, ictrl, ISP_EN_RISC);
4020 - } else {
4021 - WRT16_IO_REG(ha, ictrl, ISP_EN_INT + ISP_EN_RISC);
4022 - }
4023 -
4024 - ADAPTER_STATE_LOCK(ha);
4025 - ha->flags |= INTERRUPTS_ENABLED;
4026 - ADAPTER_STATE_UNLOCK(ha);
4027 -
4028 4202 /* Set loop online, if it really is. */
4029 4203 ql_loop_online(ha);
4030 -
4031 - state = ddi_get_devstate(ha->dip);
4032 - if (state != DDI_DEVSTATE_UP) {
4033 - /*EMPTY*/
4034 - ddi_dev_report_fault(ha->dip, DDI_SERVICE_RESTORED,
4035 - DDI_DEVICE_FAULT, "Device reset succeeded");
4036 - }
4037 4204 } else {
4038 4205 /* Enable ISP interrupts. */
4039 - if (CFG_IST(ha, CFG_CTRL_8021)) {
4040 - ql_8021_enable_intrs(ha);
4041 - } else if (CFG_IST(ha, CFG_CTRL_242581)) {
4042 - WRT32_IO_REG(ha, ictrl, ISP_EN_RISC);
4043 - } else {
4044 - WRT16_IO_REG(ha, ictrl, ISP_EN_INT + ISP_EN_RISC);
4206 + if (!(ha->flags & INTERRUPTS_ENABLED)) {
4207 + ql_enable_intr(ha);
4045 4208 }
4046 4209
4047 - ADAPTER_STATE_LOCK(ha);
4048 - ha->flags |= INTERRUPTS_ENABLED;
4049 - ADAPTER_STATE_UNLOCK(ha);
4050 -
4051 4210 TASK_DAEMON_LOCK(ha);
4052 - ha->task_daemon_flags &= ~(ISP_ABORT_NEEDED | ABORT_ISP_ACTIVE);
4053 - ha->task_daemon_flags |= LOOP_DOWN;
4211 + for (vha = ha; vha != NULL; vha = vha->vp_next) {
4212 + vha->task_daemon_flags |= LOOP_DOWN;
4213 + }
4214 + ha->task_daemon_flags &= ~ISP_ABORT_NEEDED;
4054 4215 TASK_DAEMON_UNLOCK(ha);
4055 4216
4056 4217 ql_port_state(ha, FC_STATE_OFFLINE, FC_STATE_CHANGE);
4218 +
4219 + ql_abort_queues(ha);
4220 +
4221 + TASK_DAEMON_LOCK(ha);
4222 + ha->task_daemon_flags &= ~ABORT_ISP_ACTIVE;
4223 + TASK_DAEMON_UNLOCK(ha);
4057 4224 }
4058 4225
4226 + for (vha = ha; vha != NULL; vha = vha->vp_next) {
4227 + if (!(vha->task_daemon_flags & LOOP_DOWN) &&
4228 + abort_loop_down == B_TRUE) {
4229 + vha->loop_down_timer = LOOP_DOWN_TIMER_OFF;
4230 + }
4231 + }
4232 +
4059 4233 if (rval != QL_SUCCESS) {
4060 4234 EL(ha, "failed, rval = %xh\n", rval);
4061 4235 } else {
4062 4236 /*EMPTY*/
4063 - QL_PRINT_2(CE_CONT, "(%d): done\n", ha->instance);
4237 + QL_PRINT_2(ha, "done\n");
4064 4238 }
4065 4239 return (rval);
4066 4240 }
4067 4241
4068 4242 /*
4243 + * ql_requeue_all_cmds
4244 + * Requeue all commands.
4245 + *
4246 + * Input:
4247 + * ha = virtual adapter state pointer.
4248 + *
4249 + * Returns:
4250 + * ql local function return status code.
4251 + *
4252 + * Context:
4253 + * Kernel context.
4254 + */
4255 +void
4256 +ql_requeue_all_cmds(ql_adapter_state_t *ha)
4257 +{
4258 + ql_link_t *link;
4259 + ql_tgt_t *tq;
4260 + ql_lun_t *lq;
4261 + ql_srb_t *sp;
4262 + uint16_t index;
4263 +
4264 + /* Place all commands in outstanding cmd list on device queue. */
4265 + for (index = 1; index < ha->osc_max_cnt; index++) {
4266 + INTR_LOCK(ha);
4267 + REQUEST_RING_LOCK(ha);
4268 + if ((link = ha->pending_cmds.first) != NULL) {
4269 + sp = link->base_address;
4270 + ql_remove_link(&ha->pending_cmds, &sp->cmd);
4271 +
4272 + REQUEST_RING_UNLOCK(ha);
4273 + index = 0;
4274 + } else {
4275 + REQUEST_RING_UNLOCK(ha);
4276 + if ((sp = ha->outstanding_cmds[index]) == NULL ||
4277 + sp == QL_ABORTED_SRB(ha)) {
4278 + INTR_UNLOCK(ha);
4279 + continue;
4280 + }
4281 + }
4282 +
4283 + /*
4284 + * It's not obvious but the index for commands pulled from
4285 + * pending will be zero and that entry in the outstanding array
4286 + * is not used so nulling it is "no harm, no foul".
4287 + */
4288 +
4289 + ha->outstanding_cmds[index] = NULL;
4290 + sp->handle = 0;
4291 + sp->flags &= ~SRB_IN_TOKEN_ARRAY;
4292 +
4293 + INTR_UNLOCK(ha);
4294 +
4295 + /* If command timeout. */
4296 + if (sp->flags & SRB_COMMAND_TIMEOUT) {
4297 + sp->pkt->pkt_reason = CS_TIMEOUT;
4298 + sp->flags &= ~SRB_RETRY;
4299 + sp->flags |= SRB_ISP_COMPLETED;
4300 +
4301 + /* Call done routine to handle completion. */
4302 + ql_done(&sp->cmd, B_FALSE);
4303 + continue;
4304 + }
4305 +
4306 + /* Acquire target queue lock. */
4307 + lq = sp->lun_queue;
4308 + tq = lq->target_queue;
4309 +
4310 + /* return any tape IO as exchange dropped due to chip reset */
4311 + if (tq->flags & TQF_TAPE_DEVICE) {
4312 + sp->pkt->pkt_reason = CS_TRANSPORT;
4313 + sp->flags &= ~SRB_RETRY;
4314 + sp->flags |= SRB_ISP_COMPLETED;
4315 +
4316 + EL(ha, "rtn seq IO, sp=%ph", sp);
4317 +
4318 + /* Call done routine to handle completion. */
4319 + ql_done(&sp->cmd, B_FALSE);
4320 + continue;
4321 + }
4322 +
4323 + DEVICE_QUEUE_LOCK(tq);
4324 +
4325 + /* Reset watchdog time. */
4326 + sp->wdg_q_time = sp->init_wdg_q_time;
4327 +
4328 + /* Place request back on top of device queue. */
4329 + sp->flags &= ~(SRB_ISP_STARTED | SRB_ISP_COMPLETED |
4330 + SRB_RETRY);
4331 +
4332 + ql_add_link_t(&lq->cmd, &sp->cmd);
4333 + sp->flags |= SRB_IN_DEVICE_QUEUE;
4334 +
4335 + /* Release target queue lock. */
4336 + DEVICE_QUEUE_UNLOCK(tq);
4337 + }
4338 +}
4339 +
4340 +/*
4069 4341 * ql_vport_control
4070 4342 * Issue Virtual Port Control command.
4071 4343 *
4072 4344 * Input:
4073 4345 * ha = virtual adapter state pointer.
4074 4346 * cmd = control command.
4075 4347 *
4076 4348 * Returns:
4077 4349 * ql local function return status code.
4078 4350 *
4079 4351 * Context:
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4080 4352 * Kernel context.
4081 4353 */
4082 4354 int
4083 4355 ql_vport_control(ql_adapter_state_t *ha, uint8_t cmd)
4084 4356 {
4085 4357 ql_mbx_iocb_t *pkt;
4086 4358 uint8_t bit;
4087 4359 int rval;
4088 4360 uint32_t pkt_size;
4089 4361
4090 - QL_PRINT_10(CE_CONT, "(%d,%d): started\n", ha->instance, ha->vp_index);
4362 + QL_PRINT_10(ha, "started\n");
4091 4363
4092 4364 if (ha->vp_index != 0) {
4093 4365 pkt_size = sizeof (ql_mbx_iocb_t);
4094 4366 pkt = kmem_zalloc(pkt_size, KM_SLEEP);
4095 4367 if (pkt == NULL) {
4096 4368 EL(ha, "failed, kmem_zalloc\n");
4097 4369 return (QL_MEMORY_ALLOC_FAILED);
4098 4370 }
4099 4371
4100 4372 pkt->vpc.entry_type = VP_CONTROL_TYPE;
4101 4373 pkt->vpc.entry_count = 1;
4102 4374 pkt->vpc.command = cmd;
4103 4375 pkt->vpc.vp_count = 1;
4376 + pkt->vpc.fcf_index = ha->fcoe_fcf_idx;
4104 4377 bit = (uint8_t)(ha->vp_index - 1);
4105 4378 pkt->vpc.vp_index[bit / 8] = (uint8_t)
4106 4379 (pkt->vpc.vp_index[bit / 8] | BIT_0 << bit % 8);
4107 4380
4108 4381 rval = ql_issue_mbx_iocb(ha, (caddr_t)pkt, pkt_size);
4109 4382 if (rval == QL_SUCCESS && pkt->vpc.status != 0) {
4110 4383 rval = QL_COMMAND_ERROR;
4111 4384 }
4112 4385
4113 4386 kmem_free(pkt, pkt_size);
4114 4387 } else {
4115 4388 rval = QL_SUCCESS;
4116 4389 }
4117 4390
4118 4391 if (rval != QL_SUCCESS) {
4119 4392 EL(ha, "failed, rval = %xh\n", rval);
4120 4393 } else {
4121 4394 /*EMPTY*/
4122 - QL_PRINT_10(CE_CONT, "(%d,%d): done\n", ha->instance,
4123 - ha->vp_index);
4395 + QL_PRINT_10(ha, "done\n");
4124 4396 }
4125 4397 return (rval);
4126 4398 }
4127 4399
4128 4400 /*
4129 4401 * ql_vport_modify
4130 4402 * Issue of Modify Virtual Port command.
4131 4403 *
4132 4404 * Input:
4133 4405 * ha = virtual adapter state pointer.
4134 4406 * cmd = command.
4135 4407 * opt = option.
4136 4408 *
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4137 4409 * Context:
4138 4410 * Interrupt or Kernel context, no mailbox commands allowed.
4139 4411 */
4140 4412 int
4141 4413 ql_vport_modify(ql_adapter_state_t *ha, uint8_t cmd, uint8_t opt)
4142 4414 {
4143 4415 ql_mbx_iocb_t *pkt;
4144 4416 int rval;
4145 4417 uint32_t pkt_size;
4146 4418
4147 - QL_PRINT_10(CE_CONT, "(%d,%d): started\n", ha->instance, ha->vp_index);
4419 + QL_PRINT_10(ha, "started\n");
4148 4420
4421 + if (ha->pha->task_daemon_flags & LOOP_DOWN) {
4422 + QL_PRINT_10(ha, "loop_down\n");
4423 + return (QL_FUNCTION_FAILED);
4424 + }
4425 +
4149 4426 pkt_size = sizeof (ql_mbx_iocb_t);
4150 4427 pkt = kmem_zalloc(pkt_size, KM_SLEEP);
4151 4428 if (pkt == NULL) {
4152 4429 EL(ha, "failed, kmem_zalloc\n");
4153 4430 return (QL_MEMORY_ALLOC_FAILED);
4154 4431 }
4155 4432
4156 4433 pkt->vpm.entry_type = VP_MODIFY_TYPE;
4157 4434 pkt->vpm.entry_count = 1;
4158 4435 pkt->vpm.command = cmd;
4159 4436 pkt->vpm.vp_count = 1;
4160 4437 pkt->vpm.first_vp_index = ha->vp_index;
4161 4438 pkt->vpm.first_options = opt;
4439 + pkt->vpm.fcf_index = ha->fcoe_fcf_idx;
4162 4440 bcopy(ha->loginparams.nport_ww_name.raw_wwn, pkt->vpm.first_port_name,
4163 4441 8);
4164 4442 bcopy(ha->loginparams.node_ww_name.raw_wwn, pkt->vpm.first_node_name,
4165 4443 8);
4166 4444
4167 4445 rval = ql_issue_mbx_iocb(ha, (caddr_t)pkt, pkt_size);
4168 4446 if (rval == QL_SUCCESS && pkt->vpm.status != 0) {
4169 4447 EL(ha, "failed, ql_issue_mbx_iocb=%xh, status=%xh\n", rval,
4170 4448 pkt->vpm.status);
4171 4449 rval = QL_COMMAND_ERROR;
4172 4450 }
4173 4451
4174 4452 kmem_free(pkt, pkt_size);
4175 4453
4176 4454 if (rval != QL_SUCCESS) {
4177 4455 EL(ha, "failed, rval = %xh\n", rval);
4178 4456 } else {
4179 4457 /*EMPTY*/
4180 - QL_PRINT_10(CE_CONT, "(%d,%d): done\n", ha->instance,
4181 - ha->vp_index);
4458 + QL_PRINT_10(ha, "done\n");
4182 4459 }
4183 4460 return (rval);
4184 4461 }
4185 4462
4186 4463 /*
4187 4464 * ql_vport_enable
4188 4465 * Enable virtual port.
4189 4466 *
4190 4467 * Input:
4191 4468 * ha = virtual adapter state pointer.
4192 4469 *
4193 4470 * Context:
4194 4471 * Kernel context.
4195 4472 */
4196 4473 int
4197 4474 ql_vport_enable(ql_adapter_state_t *ha)
4198 4475 {
4199 4476 int timer;
4200 4477
4201 - QL_PRINT_10(CE_CONT, "(%d,%d): started\n", ha->instance, ha->vp_index);
4478 + QL_PRINT_10(ha, "started\n");
4202 4479
4203 4480 ha->state = FC_PORT_SPEED_MASK(ha->state) | FC_STATE_OFFLINE;
4204 4481 TASK_DAEMON_LOCK(ha);
4205 4482 ha->task_daemon_flags |= LOOP_DOWN;
4206 4483 ha->task_daemon_flags &= ~(FC_STATE_CHANGE | STATE_ONLINE);
4207 4484 TASK_DAEMON_UNLOCK(ha);
4208 4485
4209 4486 ADAPTER_STATE_LOCK(ha);
4210 4487 ha->flags |= VP_ENABLED;
4488 + ha->flags &= ~VP_ID_NOT_ACQUIRED;
4211 4489 ADAPTER_STATE_UNLOCK(ha);
4490 + ha->fcoe_fcf_idx = 0;
4212 4491
4213 4492 if (ql_vport_modify(ha, VPM_MODIFY_ENABLE, VPO_TARGET_MODE_DISABLED |
4214 4493 VPO_INITIATOR_MODE_ENABLED | VPO_ENABLED) != QL_SUCCESS) {
4215 - QL_PRINT_2(CE_CONT, "(%d): failed to enable virtual port=%d\n",
4216 - ha->instance, ha->vp_index);
4494 + QL_PRINT_2(ha, "failed to enable virtual port\n");
4217 4495 return (QL_FUNCTION_FAILED);
4218 4496 }
4219 4497 if (!(ha->pha->task_daemon_flags & LOOP_DOWN)) {
4220 4498 /* Wait for loop to come up. */
4221 4499 for (timer = 0; timer < 3000 &&
4222 4500 !(ha->task_daemon_flags & STATE_ONLINE);
4223 4501 timer++) {
4502 + if (ha->flags & VP_ID_NOT_ACQUIRED) {
4503 + break;
4504 + }
4224 4505 delay(1);
4225 4506 }
4226 4507 }
4227 4508
4228 - QL_PRINT_10(CE_CONT, "(%d,%d): done\n", ha->instance, ha->vp_index);
4509 + QL_PRINT_10(ha, "done\n");
4229 4510
4230 4511 return (QL_SUCCESS);
4231 4512 }
4232 4513
4233 4514 /*
4234 4515 * ql_vport_create
4235 4516 * Create virtual port context.
4236 4517 *
4237 4518 * Input:
4238 4519 * ha: parent adapter state pointer.
4239 4520 * index: virtual port index number.
4240 4521 *
4241 4522 * Context:
4242 4523 * Kernel context.
4243 4524 */
4244 4525 ql_adapter_state_t *
4245 4526 ql_vport_create(ql_adapter_state_t *ha, uint8_t index)
4246 4527 {
4247 4528 ql_adapter_state_t *vha;
4248 4529
4249 - QL_PRINT_10(CE_CONT, "(%d,%d): started\n", ha->instance, ha->vp_index);
4530 + QL_PRINT_10(ha, "started\n");
4250 4531
4251 4532 /* Inherit the parents data. */
4252 4533 vha = kmem_alloc(sizeof (ql_adapter_state_t), KM_SLEEP);
4253 4534
4254 4535 ADAPTER_STATE_LOCK(ha);
4255 4536 bcopy(ha, vha, sizeof (ql_adapter_state_t));
4256 4537 vha->pi_attrs = NULL;
4257 4538 vha->ub_outcnt = 0;
4258 4539 vha->ub_allocated = 0;
4259 4540 vha->flags = 0;
4260 4541 vha->task_daemon_flags = 0;
4261 4542 ha->vp_next = vha;
4262 4543 vha->pha = ha;
4263 4544 vha->vp_index = index;
4264 4545 ADAPTER_STATE_UNLOCK(ha);
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4265 4546
4266 4547 vha->hba.next = NULL;
4267 4548 vha->hba.prev = NULL;
4268 4549 vha->hba.base_address = vha;
4269 4550 vha->state = FC_PORT_SPEED_MASK(ha->state) | FC_STATE_OFFLINE;
4270 4551 vha->dev = kmem_zalloc(sizeof (*vha->dev) * DEVICE_HEAD_LIST_SIZE,
4271 4552 KM_SLEEP);
4272 4553 vha->ub_array = kmem_zalloc(sizeof (*vha->ub_array) * QL_UB_LIMIT,
4273 4554 KM_SLEEP);
4274 4555
4275 - QL_PRINT_10(CE_CONT, "(%d,%d): done\n", ha->instance, ha->vp_index);
4556 + QL_PRINT_10(ha, "done\n");
4276 4557
4277 4558 return (vha);
4278 4559 }
4279 4560
4280 4561 /*
4281 4562 * ql_vport_destroy
4282 4563 * Destroys virtual port context.
4283 4564 *
4284 4565 * Input:
4285 4566 * ha = virtual adapter state pointer.
4286 4567 *
4287 4568 * Context:
4288 4569 * Kernel context.
4289 4570 */
4290 4571 void
4291 4572 ql_vport_destroy(ql_adapter_state_t *ha)
4292 4573 {
4293 4574 ql_adapter_state_t *vha;
4294 4575
4295 - QL_PRINT_10(CE_CONT, "(%d,%d): started\n", ha->instance, ha->vp_index);
4576 + QL_PRINT_10(ha, "started\n");
4296 4577
4297 4578 /* Remove port from list. */
4298 4579 ADAPTER_STATE_LOCK(ha);
4299 4580 for (vha = ha->pha; vha != NULL; vha = vha->vp_next) {
4300 4581 if (vha->vp_next == ha) {
4301 4582 vha->vp_next = ha->vp_next;
4302 4583 break;
4303 4584 }
4304 4585 }
4305 4586 ADAPTER_STATE_UNLOCK(ha);
4306 4587
4307 4588 if (ha->ub_array != NULL) {
4308 4589 kmem_free(ha->ub_array, sizeof (*ha->ub_array) * QL_UB_LIMIT);
4309 4590 }
4310 4591 if (ha->dev != NULL) {
4311 4592 kmem_free(ha->dev, sizeof (*vha->dev) * DEVICE_HEAD_LIST_SIZE);
4312 4593 }
4313 4594 kmem_free(ha, sizeof (ql_adapter_state_t));
4314 4595
4315 - QL_PRINT_10(CE_CONT, "(%d,%d): done\n", ha->instance, ha->vp_index);
4596 + QL_PRINT_10(ha, "done\n");
4316 4597 }
4317 4598
4318 4599 /*
4319 4600 * ql_mps_reset
4320 4601 * Reset MPS for FCoE functions.
4321 4602 *
4322 4603 * Input:
4323 4604 * ha = virtual adapter state pointer.
4324 4605 *
4325 4606 * Context:
4326 4607 * Kernel context.
4327 4608 */
4328 4609 static void
4329 4610 ql_mps_reset(ql_adapter_state_t *ha)
4330 4611 {
4331 4612 uint32_t data, dctl = 1000;
4332 4613
4333 4614 do {
4334 4615 if (dctl-- == 0 || ql_wrt_risc_ram_word(ha, 0x7c00, 1) !=
4335 4616 QL_SUCCESS) {
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4336 4617 return;
4337 4618 }
4338 4619 if (ql_rd_risc_ram_word(ha, 0x7c00, &data) != QL_SUCCESS) {
4339 4620 (void) ql_wrt_risc_ram_word(ha, 0x7c00, 0);
4340 4621 return;
4341 4622 }
4342 4623 } while (!(data & BIT_0));
4343 4624
4344 4625 if (ql_rd_risc_ram_word(ha, 0x7A15, &data) == QL_SUCCESS) {
4345 4626 dctl = (uint16_t)ql_pci_config_get16(ha, 0x54);
4346 - if ((data & 0xe0) != (dctl & 0xe0)) {
4627 + if ((data & 0xe0) < (dctl & 0xe0)) {
4347 4628 data &= 0xff1f;
4348 4629 data |= dctl & 0xe0;
4349 4630 (void) ql_wrt_risc_ram_word(ha, 0x7A15, data);
4631 + } else if ((data & 0xe0) != (dctl & 0xe0)) {
4632 + data &= 0xff1f;
4633 + data |= dctl & 0xe0;
4634 + (void) ql_wrt_risc_ram_word(ha, 0x7A15, data);
4350 4635 }
4351 4636 }
4352 4637 (void) ql_wrt_risc_ram_word(ha, 0x7c00, 0);
4638 +}
4639 +
4640 +/*
4641 + * ql_update_dev
4642 + * Updates device status on loop reconfigure.
4643 + *
4644 + * Input:
4645 + * ha: adapter state pointer.
4646 + * index: list index of device data.
4647 + *
4648 + * Context:
4649 + * Kernel context.
4650 + */
4651 +static void
4652 +ql_update_dev(ql_adapter_state_t *ha, uint32_t index)
4653 +{
4654 + ql_link_t *link;
4655 + ql_tgt_t *tq;
4656 + int rval;
4657 +
4658 + QL_PRINT_3(ha, "started\n");
4659 +
4660 + link = ha->dev[index].first;
4661 + while (link != NULL) {
4662 + tq = link->base_address;
4663 + link = link->next;
4664 +
4665 + if (tq->loop_id & PORT_LOST_ID &&
4666 + !(tq->flags & (TQF_INITIATOR_DEVICE | TQF_FABRIC_DEVICE))) {
4667 +
4668 + tq->loop_id &= ~PORT_LOST_ID;
4669 +
4670 + if (VALID_DEVICE_ID(ha, tq->loop_id)) {
4671 + /* implicit logo due to fw issue */
4672 + rval = ql_get_port_database(ha, tq, PDF_NONE);
4673 +
4674 + if (rval == QL_NOT_LOGGED_IN) {
4675 + if (tq->master_state ==
4676 + PD_STATE_PORT_UNAVAILABLE) {
4677 + (void) ql_logout_fabric_port(
4678 + ha, tq);
4679 + tq->loop_id = PORT_NO_LOOP_ID;
4680 + }
4681 + } else if (rval == QL_SUCCESS) {
4682 + tq->loop_id = PORT_NO_LOOP_ID;
4683 + }
4684 + }
4685 + } else if (ha->topology & QL_NL_PORT &&
4686 + tq->flags & TQF_FABRIC_DEVICE) {
4687 +
4688 + tq->loop_id &= ~PORT_LOST_ID;
4689 +
4690 + if (VALID_DEVICE_ID(ha, tq->loop_id)) {
4691 + /* implicit logo due to fw issue */
4692 + rval = ql_get_port_database(ha, tq, PDF_NONE);
4693 +
4694 + if (rval == QL_NOT_LOGGED_IN) {
4695 + if (tq->master_state ==
4696 + PD_STATE_PORT_UNAVAILABLE) {
4697 + (void) ql_logout_fabric_port(
4698 + ha, tq);
4699 + /*
4700 + * fabric to AL topo change
4701 + */
4702 + tq->loop_id = PORT_NO_LOOP_ID;
4703 + }
4704 + } else if (rval == QL_SUCCESS) {
4705 + /*
4706 + * Normally this is 7fe,
4707 + * Don't issue logo, it causes
4708 + * logo in single tgt AL.
4709 + */
4710 + tq->loop_id = PORT_NO_LOOP_ID;
4711 + }
4712 + }
4713 + }
4714 + }
4715 +
4716 + QL_PRINT_3(ha, "done\n");
4353 4717 }
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