8 *
9 * Copyright(c) 1999 - 2009 Intel Corporation. All rights reserved.
10 *
11 * The contents of this file are subject to the terms of Version
12 * 1.0 of the Common Development and Distribution License (the "License").
13 *
14 * You should have received a copy of the License with this software.
15 * You can obtain a copy of the License at
16 * http://www.opensolaris.org/os/licensing.
17 * See the License for the specific language governing permissions
18 * and limitations under the License.
19 */
20
21 /*
22 * Copyright (c) 2010, Oracle and/or its affiliates. All rights reserved.
23 */
24
25 /*
26 * Copyright 2012 DEY Storage Systems, Inc. All rights reserved.
27 * Copyright 2013 Nexenta Systems, Inc. All rights reserved.
28 * Copyright (c) 2017, Joyent, Inc.
29 */
30
31 /*
32 * **********************************************************************
33 * *
34 * Module Name: *
35 * e1000g_main.c *
36 * *
37 * Abstract: *
38 * This file contains the interface routines for the solaris OS. *
39 * It has all DDI entry point routines and GLD entry point routines. *
40 * *
41 * This file also contains routines that take care of initialization *
42 * uninit routine and interrupt routine. *
43 * *
44 * **********************************************************************
45 */
46
47 #include <sys/dlpi.h>
48 #include <sys/mac.h>
694
695 /* get flash size */
696 if (ddi_dev_regsize(devinfo, rnumber,
697 &mem_size) != DDI_SUCCESS) {
698 E1000G_DEBUGLOG_0(Adapter, CE_WARN,
699 "ddi_dev_regsize for ICH flash failed");
700 goto regs_map_fail;
701 }
702
703 /* map flash in */
704 if (ddi_regs_map_setup(devinfo, rnumber,
705 (caddr_t *)&hw->flash_address, 0,
706 mem_size, &e1000g_regs_acc_attr,
707 &osdep->ich_flash_handle) != DDI_SUCCESS) {
708 E1000G_DEBUGLOG_0(Adapter, CE_WARN,
709 "ddi_regs_map_setup for ICH flash failed");
710 goto regs_map_fail;
711 }
712 break;
713 case e1000_pch_spt:
714 /*
715 * On the SPT, the device flash is actually in BAR0, not a
716 * separate BAR. Therefore we end up setting the
717 * ich_flash_handle to be the same as the register handle.
718 * We mark the same to reduce the confusion in the other
719 * functions and macros. Though this does make the set up and
720 * tear-down path slightly more complicated.
721 */
722 osdep->ich_flash_handle = osdep->reg_handle;
723 hw->flash_address = hw->hw_addr;
724 default:
725 break;
726 }
727
728 /* map io space */
729 switch (hw->mac.type) {
730 case e1000_82544:
731 case e1000_82540:
732 case e1000_82545:
733 case e1000_82546:
763 /* map io space */
764 if ((ddi_regs_map_setup(devinfo, rnumber,
765 (caddr_t *)&hw->io_base, 0, mem_size,
766 &e1000g_regs_acc_attr,
767 &osdep->io_reg_handle)) != DDI_SUCCESS) {
768 E1000G_DEBUGLOG_0(Adapter, CE_WARN,
769 "ddi_regs_map_setup for io space failed");
770 goto regs_map_fail;
771 }
772 break;
773 default:
774 hw->io_base = 0;
775 break;
776 }
777
778 return (DDI_SUCCESS);
779
780 regs_map_fail:
781 if (osdep->reg_handle != NULL)
782 ddi_regs_map_free(&osdep->reg_handle);
783 if (osdep->ich_flash_handle != NULL && hw->mac.type != e1000_pch_spt)
784 ddi_regs_map_free(&osdep->ich_flash_handle);
785 return (DDI_FAILURE);
786 }
787
788 static int
789 e1000g_set_driver_params(struct e1000g *Adapter)
790 {
791 struct e1000_hw *hw;
792
793 hw = &Adapter->shared;
794
795 /* Set MAC type and initialize hardware functions */
796 if (e1000_setup_init_funcs(hw, B_TRUE) != E1000_SUCCESS) {
797 E1000G_DEBUGLOG_0(Adapter, CE_WARN,
798 "Could not setup hardware functions");
799 return (DDI_FAILURE);
800 }
801
802 /* Get bus information */
803 if (e1000_get_bus_info(hw) != E1000_SUCCESS) {
892 case e1000_ich8lan:
893 case e1000_82573:
894 case e1000_82583:
895 Adapter->max_mtu = ETHERMTU;
896 break;
897 /* ich9 supports jumbo frames except on one phy type */
898 case e1000_ich9lan:
899 if (phy->type == e1000_phy_ife)
900 Adapter->max_mtu = ETHERMTU;
901 else
902 Adapter->max_mtu = MAXIMUM_MTU_9K;
903 break;
904 /* pch can do jumbo frames up to 4K */
905 case e1000_pchlan:
906 Adapter->max_mtu = MAXIMUM_MTU_4K;
907 break;
908 /* pch2 can do jumbo frames up to 9K */
909 case e1000_pch2lan:
910 case e1000_pch_lpt:
911 case e1000_pch_spt:
912 Adapter->max_mtu = MAXIMUM_MTU_9K;
913 break;
914 /* types with a special limit */
915 case e1000_82571:
916 case e1000_82572:
917 case e1000_82574:
918 case e1000_80003es2lan:
919 case e1000_ich10lan:
920 if (e1000g_jumbo_mtu >= ETHERMTU &&
921 e1000g_jumbo_mtu <= MAXIMUM_MTU_9K) {
922 Adapter->max_mtu = e1000g_jumbo_mtu;
923 } else {
924 Adapter->max_mtu = MAXIMUM_MTU_9K;
925 }
926 break;
927 /* default limit is 16K */
928 default:
929 Adapter->max_mtu = FRAME_SIZE_UPTO_16K -
930 sizeof (struct ether_vlan_header) - ETHERFCSL;
931 break;
1130
1131 if (Adapter->attach_progress & ATTACH_PROGRESS_INIT) {
1132 stop_link_timer(Adapter);
1133
1134 mutex_enter(&e1000g_nvm_lock);
1135 result = e1000_reset_hw(&Adapter->shared);
1136 mutex_exit(&e1000g_nvm_lock);
1137
1138 if (result != E1000_SUCCESS) {
1139 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE);
1140 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST);
1141 }
1142 }
1143
1144 e1000g_release_multicast(Adapter);
1145
1146 if (Adapter->attach_progress & ATTACH_PROGRESS_REGS_MAP) {
1147 if (Adapter->osdep.reg_handle != NULL)
1148 ddi_regs_map_free(&Adapter->osdep.reg_handle);
1149 if (Adapter->osdep.ich_flash_handle != NULL &&
1150 Adapter->shared.mac.type != e1000_pch_spt)
1151 ddi_regs_map_free(&Adapter->osdep.ich_flash_handle);
1152 if (Adapter->osdep.io_reg_handle != NULL)
1153 ddi_regs_map_free(&Adapter->osdep.io_reg_handle);
1154 }
1155
1156 if (Adapter->attach_progress & ATTACH_PROGRESS_PCI_CONFIG) {
1157 if (Adapter->osdep.cfg_handle != NULL)
1158 pci_config_teardown(&Adapter->osdep.cfg_handle);
1159 }
1160
1161 if (Adapter->attach_progress & ATTACH_PROGRESS_LOCKS) {
1162 e1000g_destroy_locks(Adapter);
1163 }
1164
1165 if (Adapter->attach_progress & ATTACH_PROGRESS_FMINIT) {
1166 e1000g_fm_fini(Adapter);
1167 }
1168
1169 mutex_enter(&e1000g_rx_detach_lock);
1170 if (e1000g_force_detach && (Adapter->priv_devi_node != NULL)) {
1469 pba = E1000_PBA_38K; /* 38K for Rx, 10K for Tx */
1470 } else if (hw->mac.type == e1000_82573) {
1471 pba = E1000_PBA_20K; /* 20K for Rx, 12K for Tx */
1472 } else if (hw->mac.type == e1000_82574) {
1473 /* Keep adapter default: 20K for Rx, 20K for Tx */
1474 pba = E1000_READ_REG(hw, E1000_PBA);
1475 } else if (hw->mac.type == e1000_ich8lan) {
1476 pba = E1000_PBA_8K; /* 8K for Rx, 12K for Tx */
1477 } else if (hw->mac.type == e1000_ich9lan) {
1478 pba = E1000_PBA_10K;
1479 } else if (hw->mac.type == e1000_ich10lan) {
1480 pba = E1000_PBA_10K;
1481 } else if (hw->mac.type == e1000_pchlan) {
1482 pba = E1000_PBA_26K;
1483 } else if (hw->mac.type == e1000_pch2lan) {
1484 pba = E1000_PBA_26K;
1485 } else if (hw->mac.type == e1000_pch_lpt) {
1486 pba = E1000_PBA_26K;
1487 } else if (hw->mac.type == e1000_pch_spt) {
1488 pba = E1000_PBA_26K;
1489 } else {
1490 /*
1491 * Total FIFO is 40K
1492 */
1493 if (Adapter->max_frame_size > FRAME_SIZE_UPTO_8K)
1494 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */
1495 else
1496 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */
1497 }
1498 E1000_WRITE_REG(hw, E1000_PBA, pba);
1499
1500 /*
1501 * These parameters set thresholds for the adapter's generation(Tx)
1502 * and response(Rx) to Ethernet PAUSE frames. These are just threshold
1503 * settings. Flow control is enabled or disabled in the configuration
1504 * file.
1505 * High-water mark is set down from the top of the rx fifo (not
1506 * sensitive to max_frame_size) and low-water is set just below
1507 * high-water mark.
1508 * The high water mark must be low enough to fit one full frame above
1695
1696 /*
1697 * Check if the link is up
1698 */
1699 static boolean_t
1700 e1000g_link_up(struct e1000g *Adapter)
1701 {
1702 struct e1000_hw *hw = &Adapter->shared;
1703 boolean_t link_up = B_FALSE;
1704
1705 /*
1706 * get_link_status is set in the interrupt handler on link-status-change
1707 * or rx sequence error interrupt. get_link_status will stay
1708 * false until the e1000_check_for_link establishes link only
1709 * for copper adapters.
1710 */
1711 switch (hw->phy.media_type) {
1712 case e1000_media_type_copper:
1713 if (hw->mac.get_link_status) {
1714 /*
1715 * SPT devices need a bit of extra time before we ask
1716 * them.
1717 */
1718 if (hw->mac.type == e1000_pch_spt)
1719 msec_delay(50);
1720 (void) e1000_check_for_link(hw);
1721 if ((E1000_READ_REG(hw, E1000_STATUS) &
1722 E1000_STATUS_LU)) {
1723 link_up = B_TRUE;
1724 } else {
1725 link_up = !hw->mac.get_link_status;
1726 }
1727 } else {
1728 link_up = B_TRUE;
1729 }
1730 break;
1731 case e1000_media_type_fiber:
1732 (void) e1000_check_for_link(hw);
1733 link_up = (E1000_READ_REG(hw, E1000_STATUS) &
1734 E1000_STATUS_LU);
1735 break;
1736 case e1000_media_type_internal_serdes:
1737 (void) e1000_check_for_link(hw);
1738 link_up = hw->mac.serdes_has_link;
2059 }
2060
2061 mutex_enter(&Adapter->link_lock);
2062 Adapter->link_complete = B_FALSE;
2063 mutex_exit(&Adapter->link_lock);
2064
2065 /* Release resources still held by the TX descriptors */
2066 e1000g_tx_clean(Adapter);
2067
2068 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK)
2069 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST);
2070
2071 /* Clean the pending rx jumbo packet fragment */
2072 e1000g_rx_clean(Adapter);
2073
2074 /*
2075 * The I219, eg. the pch_spt, has bugs such that we must ensure that
2076 * rings are flushed before we do anything else. This must be done
2077 * before we release DMA resources.
2078 */
2079 if (Adapter->shared.mac.type == e1000_pch_spt)
2080 e1000g_flush_desc_rings(Adapter);
2081
2082 if (global) {
2083 e1000g_release_dma_resources(Adapter);
2084
2085 mutex_enter(&e1000g_rx_detach_lock);
2086 rx_data = Adapter->rx_ring->rx_data;
2087 rx_data->flag |= E1000G_RX_STOPPED;
2088
2089 if (rx_data->pending_count == 0) {
2090 e1000g_free_rx_pending_buffers(rx_data);
2091 e1000g_free_rx_data(rx_data);
2092 } else {
2093 devi_node = rx_data->priv_devi_node;
2094 if (devi_node != NULL)
2095 atomic_inc_32(&devi_node->pending_rx_count);
2096 else
2097 atomic_inc_32(&Adapter->pending_rx_count);
2098 }
2099 mutex_exit(&e1000g_rx_detach_lock);
2519 int slot;
2520
2521 hw = &Adapter->shared;
2522
2523 if (Adapter->init_count == 0) {
2524 /* Initialize the multiple unicast addresses */
2525 Adapter->unicst_total = min(hw->mac.rar_entry_count,
2526 MAX_NUM_UNICAST_ADDRESSES);
2527
2528 /*
2529 * The common code does not correctly calculate the number of
2530 * rar's that could be reserved by firmware for the pch_lpt and
2531 * pch_spt macs. The interface has one primary rar, and 11
2532 * additional ones. Those 11 additional ones are not always
2533 * available. According to the datasheet, we need to check a
2534 * few of the bits set in the FWSM register. If the value is
2535 * zero, everything is available. If the value is 1, none of the
2536 * additional registers are available. If the value is 2-7, only
2537 * that number are available.
2538 */
2539 if (hw->mac.type == e1000_pch_lpt ||
2540 hw->mac.type == e1000_pch_spt) {
2541 uint32_t locked, rar;
2542
2543 locked = E1000_READ_REG(hw, E1000_FWSM) &
2544 E1000_FWSM_WLOCK_MAC_MASK;
2545 locked >>= E1000_FWSM_WLOCK_MAC_SHIFT;
2546 rar = 1;
2547 if (locked == 0)
2548 rar += 11;
2549 else if (locked == 1)
2550 rar += 0;
2551 else
2552 rar += locked;
2553 Adapter->unicst_total = min(rar,
2554 MAX_NUM_UNICAST_ADDRESSES);
2555 }
2556
2557 /* Workaround for an erratum of 82571 chipst */
2558 if ((hw->mac.type == e1000_82571) &&
2559 (e1000_get_laa_state_82571(hw) == B_TRUE))
2560 Adapter->unicst_total--;
|
8 *
9 * Copyright(c) 1999 - 2009 Intel Corporation. All rights reserved.
10 *
11 * The contents of this file are subject to the terms of Version
12 * 1.0 of the Common Development and Distribution License (the "License").
13 *
14 * You should have received a copy of the License with this software.
15 * You can obtain a copy of the License at
16 * http://www.opensolaris.org/os/licensing.
17 * See the License for the specific language governing permissions
18 * and limitations under the License.
19 */
20
21 /*
22 * Copyright (c) 2010, Oracle and/or its affiliates. All rights reserved.
23 */
24
25 /*
26 * Copyright 2012 DEY Storage Systems, Inc. All rights reserved.
27 * Copyright 2013 Nexenta Systems, Inc. All rights reserved.
28 * Copyright (c) 2018, Joyent, Inc.
29 */
30
31 /*
32 * **********************************************************************
33 * *
34 * Module Name: *
35 * e1000g_main.c *
36 * *
37 * Abstract: *
38 * This file contains the interface routines for the solaris OS. *
39 * It has all DDI entry point routines and GLD entry point routines. *
40 * *
41 * This file also contains routines that take care of initialization *
42 * uninit routine and interrupt routine. *
43 * *
44 * **********************************************************************
45 */
46
47 #include <sys/dlpi.h>
48 #include <sys/mac.h>
694
695 /* get flash size */
696 if (ddi_dev_regsize(devinfo, rnumber,
697 &mem_size) != DDI_SUCCESS) {
698 E1000G_DEBUGLOG_0(Adapter, CE_WARN,
699 "ddi_dev_regsize for ICH flash failed");
700 goto regs_map_fail;
701 }
702
703 /* map flash in */
704 if (ddi_regs_map_setup(devinfo, rnumber,
705 (caddr_t *)&hw->flash_address, 0,
706 mem_size, &e1000g_regs_acc_attr,
707 &osdep->ich_flash_handle) != DDI_SUCCESS) {
708 E1000G_DEBUGLOG_0(Adapter, CE_WARN,
709 "ddi_regs_map_setup for ICH flash failed");
710 goto regs_map_fail;
711 }
712 break;
713 case e1000_pch_spt:
714 case e1000_pch_cnp:
715 /*
716 * On the SPT, the device flash is actually in BAR0, not a
717 * separate BAR. Therefore we end up setting the
718 * ich_flash_handle to be the same as the register handle.
719 * We mark the same to reduce the confusion in the other
720 * functions and macros. Though this does make the set up and
721 * tear-down path slightly more complicated.
722 */
723 osdep->ich_flash_handle = osdep->reg_handle;
724 hw->flash_address = hw->hw_addr;
725 default:
726 break;
727 }
728
729 /* map io space */
730 switch (hw->mac.type) {
731 case e1000_82544:
732 case e1000_82540:
733 case e1000_82545:
734 case e1000_82546:
764 /* map io space */
765 if ((ddi_regs_map_setup(devinfo, rnumber,
766 (caddr_t *)&hw->io_base, 0, mem_size,
767 &e1000g_regs_acc_attr,
768 &osdep->io_reg_handle)) != DDI_SUCCESS) {
769 E1000G_DEBUGLOG_0(Adapter, CE_WARN,
770 "ddi_regs_map_setup for io space failed");
771 goto regs_map_fail;
772 }
773 break;
774 default:
775 hw->io_base = 0;
776 break;
777 }
778
779 return (DDI_SUCCESS);
780
781 regs_map_fail:
782 if (osdep->reg_handle != NULL)
783 ddi_regs_map_free(&osdep->reg_handle);
784 if (osdep->ich_flash_handle != NULL && hw->mac.type < e1000_pch_spt)
785 ddi_regs_map_free(&osdep->ich_flash_handle);
786 return (DDI_FAILURE);
787 }
788
789 static int
790 e1000g_set_driver_params(struct e1000g *Adapter)
791 {
792 struct e1000_hw *hw;
793
794 hw = &Adapter->shared;
795
796 /* Set MAC type and initialize hardware functions */
797 if (e1000_setup_init_funcs(hw, B_TRUE) != E1000_SUCCESS) {
798 E1000G_DEBUGLOG_0(Adapter, CE_WARN,
799 "Could not setup hardware functions");
800 return (DDI_FAILURE);
801 }
802
803 /* Get bus information */
804 if (e1000_get_bus_info(hw) != E1000_SUCCESS) {
893 case e1000_ich8lan:
894 case e1000_82573:
895 case e1000_82583:
896 Adapter->max_mtu = ETHERMTU;
897 break;
898 /* ich9 supports jumbo frames except on one phy type */
899 case e1000_ich9lan:
900 if (phy->type == e1000_phy_ife)
901 Adapter->max_mtu = ETHERMTU;
902 else
903 Adapter->max_mtu = MAXIMUM_MTU_9K;
904 break;
905 /* pch can do jumbo frames up to 4K */
906 case e1000_pchlan:
907 Adapter->max_mtu = MAXIMUM_MTU_4K;
908 break;
909 /* pch2 can do jumbo frames up to 9K */
910 case e1000_pch2lan:
911 case e1000_pch_lpt:
912 case e1000_pch_spt:
913 case e1000_pch_cnp:
914 Adapter->max_mtu = MAXIMUM_MTU_9K;
915 break;
916 /* types with a special limit */
917 case e1000_82571:
918 case e1000_82572:
919 case e1000_82574:
920 case e1000_80003es2lan:
921 case e1000_ich10lan:
922 if (e1000g_jumbo_mtu >= ETHERMTU &&
923 e1000g_jumbo_mtu <= MAXIMUM_MTU_9K) {
924 Adapter->max_mtu = e1000g_jumbo_mtu;
925 } else {
926 Adapter->max_mtu = MAXIMUM_MTU_9K;
927 }
928 break;
929 /* default limit is 16K */
930 default:
931 Adapter->max_mtu = FRAME_SIZE_UPTO_16K -
932 sizeof (struct ether_vlan_header) - ETHERFCSL;
933 break;
1132
1133 if (Adapter->attach_progress & ATTACH_PROGRESS_INIT) {
1134 stop_link_timer(Adapter);
1135
1136 mutex_enter(&e1000g_nvm_lock);
1137 result = e1000_reset_hw(&Adapter->shared);
1138 mutex_exit(&e1000g_nvm_lock);
1139
1140 if (result != E1000_SUCCESS) {
1141 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE);
1142 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST);
1143 }
1144 }
1145
1146 e1000g_release_multicast(Adapter);
1147
1148 if (Adapter->attach_progress & ATTACH_PROGRESS_REGS_MAP) {
1149 if (Adapter->osdep.reg_handle != NULL)
1150 ddi_regs_map_free(&Adapter->osdep.reg_handle);
1151 if (Adapter->osdep.ich_flash_handle != NULL &&
1152 Adapter->shared.mac.type < e1000_pch_spt)
1153 ddi_regs_map_free(&Adapter->osdep.ich_flash_handle);
1154 if (Adapter->osdep.io_reg_handle != NULL)
1155 ddi_regs_map_free(&Adapter->osdep.io_reg_handle);
1156 }
1157
1158 if (Adapter->attach_progress & ATTACH_PROGRESS_PCI_CONFIG) {
1159 if (Adapter->osdep.cfg_handle != NULL)
1160 pci_config_teardown(&Adapter->osdep.cfg_handle);
1161 }
1162
1163 if (Adapter->attach_progress & ATTACH_PROGRESS_LOCKS) {
1164 e1000g_destroy_locks(Adapter);
1165 }
1166
1167 if (Adapter->attach_progress & ATTACH_PROGRESS_FMINIT) {
1168 e1000g_fm_fini(Adapter);
1169 }
1170
1171 mutex_enter(&e1000g_rx_detach_lock);
1172 if (e1000g_force_detach && (Adapter->priv_devi_node != NULL)) {
1471 pba = E1000_PBA_38K; /* 38K for Rx, 10K for Tx */
1472 } else if (hw->mac.type == e1000_82573) {
1473 pba = E1000_PBA_20K; /* 20K for Rx, 12K for Tx */
1474 } else if (hw->mac.type == e1000_82574) {
1475 /* Keep adapter default: 20K for Rx, 20K for Tx */
1476 pba = E1000_READ_REG(hw, E1000_PBA);
1477 } else if (hw->mac.type == e1000_ich8lan) {
1478 pba = E1000_PBA_8K; /* 8K for Rx, 12K for Tx */
1479 } else if (hw->mac.type == e1000_ich9lan) {
1480 pba = E1000_PBA_10K;
1481 } else if (hw->mac.type == e1000_ich10lan) {
1482 pba = E1000_PBA_10K;
1483 } else if (hw->mac.type == e1000_pchlan) {
1484 pba = E1000_PBA_26K;
1485 } else if (hw->mac.type == e1000_pch2lan) {
1486 pba = E1000_PBA_26K;
1487 } else if (hw->mac.type == e1000_pch_lpt) {
1488 pba = E1000_PBA_26K;
1489 } else if (hw->mac.type == e1000_pch_spt) {
1490 pba = E1000_PBA_26K;
1491 } else if (hw->mac.type == e1000_pch_cnp) {
1492 pba = E1000_PBA_26K;
1493 } else {
1494 /*
1495 * Total FIFO is 40K
1496 */
1497 if (Adapter->max_frame_size > FRAME_SIZE_UPTO_8K)
1498 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */
1499 else
1500 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */
1501 }
1502 E1000_WRITE_REG(hw, E1000_PBA, pba);
1503
1504 /*
1505 * These parameters set thresholds for the adapter's generation(Tx)
1506 * and response(Rx) to Ethernet PAUSE frames. These are just threshold
1507 * settings. Flow control is enabled or disabled in the configuration
1508 * file.
1509 * High-water mark is set down from the top of the rx fifo (not
1510 * sensitive to max_frame_size) and low-water is set just below
1511 * high-water mark.
1512 * The high water mark must be low enough to fit one full frame above
1699
1700 /*
1701 * Check if the link is up
1702 */
1703 static boolean_t
1704 e1000g_link_up(struct e1000g *Adapter)
1705 {
1706 struct e1000_hw *hw = &Adapter->shared;
1707 boolean_t link_up = B_FALSE;
1708
1709 /*
1710 * get_link_status is set in the interrupt handler on link-status-change
1711 * or rx sequence error interrupt. get_link_status will stay
1712 * false until the e1000_check_for_link establishes link only
1713 * for copper adapters.
1714 */
1715 switch (hw->phy.media_type) {
1716 case e1000_media_type_copper:
1717 if (hw->mac.get_link_status) {
1718 /*
1719 * SPT and newer devices need a bit of extra time before
1720 * we ask them.
1721 */
1722 if (hw->mac.type >= e1000_pch_spt)
1723 msec_delay(50);
1724 (void) e1000_check_for_link(hw);
1725 if ((E1000_READ_REG(hw, E1000_STATUS) &
1726 E1000_STATUS_LU)) {
1727 link_up = B_TRUE;
1728 } else {
1729 link_up = !hw->mac.get_link_status;
1730 }
1731 } else {
1732 link_up = B_TRUE;
1733 }
1734 break;
1735 case e1000_media_type_fiber:
1736 (void) e1000_check_for_link(hw);
1737 link_up = (E1000_READ_REG(hw, E1000_STATUS) &
1738 E1000_STATUS_LU);
1739 break;
1740 case e1000_media_type_internal_serdes:
1741 (void) e1000_check_for_link(hw);
1742 link_up = hw->mac.serdes_has_link;
2063 }
2064
2065 mutex_enter(&Adapter->link_lock);
2066 Adapter->link_complete = B_FALSE;
2067 mutex_exit(&Adapter->link_lock);
2068
2069 /* Release resources still held by the TX descriptors */
2070 e1000g_tx_clean(Adapter);
2071
2072 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK)
2073 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST);
2074
2075 /* Clean the pending rx jumbo packet fragment */
2076 e1000g_rx_clean(Adapter);
2077
2078 /*
2079 * The I219, eg. the pch_spt, has bugs such that we must ensure that
2080 * rings are flushed before we do anything else. This must be done
2081 * before we release DMA resources.
2082 */
2083 if (Adapter->shared.mac.type >= e1000_pch_spt)
2084 e1000g_flush_desc_rings(Adapter);
2085
2086 if (global) {
2087 e1000g_release_dma_resources(Adapter);
2088
2089 mutex_enter(&e1000g_rx_detach_lock);
2090 rx_data = Adapter->rx_ring->rx_data;
2091 rx_data->flag |= E1000G_RX_STOPPED;
2092
2093 if (rx_data->pending_count == 0) {
2094 e1000g_free_rx_pending_buffers(rx_data);
2095 e1000g_free_rx_data(rx_data);
2096 } else {
2097 devi_node = rx_data->priv_devi_node;
2098 if (devi_node != NULL)
2099 atomic_inc_32(&devi_node->pending_rx_count);
2100 else
2101 atomic_inc_32(&Adapter->pending_rx_count);
2102 }
2103 mutex_exit(&e1000g_rx_detach_lock);
2523 int slot;
2524
2525 hw = &Adapter->shared;
2526
2527 if (Adapter->init_count == 0) {
2528 /* Initialize the multiple unicast addresses */
2529 Adapter->unicst_total = min(hw->mac.rar_entry_count,
2530 MAX_NUM_UNICAST_ADDRESSES);
2531
2532 /*
2533 * The common code does not correctly calculate the number of
2534 * rar's that could be reserved by firmware for the pch_lpt and
2535 * pch_spt macs. The interface has one primary rar, and 11
2536 * additional ones. Those 11 additional ones are not always
2537 * available. According to the datasheet, we need to check a
2538 * few of the bits set in the FWSM register. If the value is
2539 * zero, everything is available. If the value is 1, none of the
2540 * additional registers are available. If the value is 2-7, only
2541 * that number are available.
2542 */
2543 if (hw->mac.type >= e1000_pch_lpt) {
2544 uint32_t locked, rar;
2545
2546 locked = E1000_READ_REG(hw, E1000_FWSM) &
2547 E1000_FWSM_WLOCK_MAC_MASK;
2548 locked >>= E1000_FWSM_WLOCK_MAC_SHIFT;
2549 rar = 1;
2550 if (locked == 0)
2551 rar += 11;
2552 else if (locked == 1)
2553 rar += 0;
2554 else
2555 rar += locked;
2556 Adapter->unicst_total = min(rar,
2557 MAX_NUM_UNICAST_ADDRESSES);
2558 }
2559
2560 /* Workaround for an erratum of 82571 chipst */
2561 if ((hw->mac.type == e1000_82571) &&
2562 (e1000_get_laa_state_82571(hw) == B_TRUE))
2563 Adapter->unicst_total--;
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