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MFV: illumos-gate@5bb0bdfe588c5df0f63ff8ac292cd608a5f4492a
9950 Need support for Intel I219 v6-v9
Reviewed by: Jason King <jason.king@joyent.com>
Reviewed by: Garrett D'Amore <garrett@damore.org>
Approved by: Garrett D'Amore <garrett@damore.org>
Author: Robert Mustacchi <rm@joyent.com>
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--- old/usr/src/uts/common/io/e1000api/e1000_hw.h
+++ new/usr/src/uts/common/io/e1000api/e1000_hw.h
1 1 /******************************************************************************
2 2
3 3 Copyright (c) 2001-2015, Intel Corporation
4 4 All rights reserved.
5 5
6 6 Redistribution and use in source and binary forms, with or without
7 7 modification, are permitted provided that the following conditions are met:
8 8
9 9 1. Redistributions of source code must retain the above copyright notice,
10 10 this list of conditions and the following disclaimer.
11 11
12 12 2. Redistributions in binary form must reproduce the above copyright
13 13 notice, this list of conditions and the following disclaimer in the
14 14 documentation and/or other materials provided with the distribution.
15 15
16 16 3. Neither the name of the Intel Corporation nor the names of its
17 17 contributors may be used to endorse or promote products derived from
18 18 this software without specific prior written permission.
19 19
20 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 30 POSSIBILITY OF SUCH DAMAGE.
31 31
32 32 ******************************************************************************/
33 33 /*$FreeBSD$*/
34 34
35 35 #ifndef _E1000_HW_H_
36 36 #define _E1000_HW_H_
37 37
38 38 #include "e1000_osdep.h"
39 39 #include "e1000_regs.h"
40 40 #include "e1000_defines.h"
41 41
42 42 struct e1000_hw;
43 43
44 44 #define E1000_DEV_ID_82542 0x1000
45 45 #define E1000_DEV_ID_82543GC_FIBER 0x1001
46 46 #define E1000_DEV_ID_82543GC_COPPER 0x1004
47 47 #define E1000_DEV_ID_82544EI_COPPER 0x1008
48 48 #define E1000_DEV_ID_82544EI_FIBER 0x1009
49 49 #define E1000_DEV_ID_82544GC_COPPER 0x100C
50 50 #define E1000_DEV_ID_82544GC_LOM 0x100D
51 51 #define E1000_DEV_ID_82540EM 0x100E
52 52 #define E1000_DEV_ID_82540EM_LOM 0x1015
53 53 #define E1000_DEV_ID_82540EP_LOM 0x1016
54 54 #define E1000_DEV_ID_82540EP 0x1017
55 55 #define E1000_DEV_ID_82540EP_LP 0x101E
56 56 #define E1000_DEV_ID_82545EM_COPPER 0x100F
57 57 #define E1000_DEV_ID_82545EM_FIBER 0x1011
58 58 #define E1000_DEV_ID_82545GM_COPPER 0x1026
59 59 #define E1000_DEV_ID_82545GM_FIBER 0x1027
60 60 #define E1000_DEV_ID_82545GM_SERDES 0x1028
61 61 #define E1000_DEV_ID_82546EB_COPPER 0x1010
62 62 #define E1000_DEV_ID_82546EB_FIBER 0x1012
63 63 #define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D
64 64 #define E1000_DEV_ID_82546GB_COPPER 0x1079
65 65 #define E1000_DEV_ID_82546GB_FIBER 0x107A
66 66 #define E1000_DEV_ID_82546GB_SERDES 0x107B
67 67 #define E1000_DEV_ID_82546GB_PCIE 0x108A
68 68 #define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099
69 69 #define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5
70 70 #define E1000_DEV_ID_82541EI 0x1013
71 71 #define E1000_DEV_ID_82541EI_MOBILE 0x1018
72 72 #define E1000_DEV_ID_82541ER_LOM 0x1014
73 73 #define E1000_DEV_ID_82541ER 0x1078
74 74 #define E1000_DEV_ID_82541GI 0x1076
75 75 #define E1000_DEV_ID_82541GI_LF 0x107C
76 76 #define E1000_DEV_ID_82541GI_MOBILE 0x1077
77 77 #define E1000_DEV_ID_82547EI 0x1019
78 78 #define E1000_DEV_ID_82547EI_MOBILE 0x101A
79 79 #define E1000_DEV_ID_82547GI 0x1075
80 80 #define E1000_DEV_ID_82571EB_COPPER 0x105E
81 81 #define E1000_DEV_ID_82571EB_FIBER 0x105F
82 82 #define E1000_DEV_ID_82571EB_SERDES 0x1060
83 83 #define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9
84 84 #define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA
85 85 #define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4
86 86 #define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5
87 87 #define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5
88 88 #define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC
89 89 #define E1000_DEV_ID_82572EI_COPPER 0x107D
90 90 #define E1000_DEV_ID_82572EI_FIBER 0x107E
91 91 #define E1000_DEV_ID_82572EI_SERDES 0x107F
92 92 #define E1000_DEV_ID_82572EI 0x10B9
93 93 #define E1000_DEV_ID_82573E 0x108B
94 94 #define E1000_DEV_ID_82573E_IAMT 0x108C
95 95 #define E1000_DEV_ID_82573L 0x109A
96 96 #define E1000_DEV_ID_82574L 0x10D3
97 97 #define E1000_DEV_ID_82574LA 0x10F6
98 98 #define E1000_DEV_ID_82583V 0x150C
99 99 #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096
100 100 #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098
101 101 #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA
102 102 #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB
103 103 #define E1000_DEV_ID_ICH8_82567V_3 0x1501
104 104 #define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049
105 105 #define E1000_DEV_ID_ICH8_IGP_AMT 0x104A
106 106 #define E1000_DEV_ID_ICH8_IGP_C 0x104B
107 107 #define E1000_DEV_ID_ICH8_IFE 0x104C
108 108 #define E1000_DEV_ID_ICH8_IFE_GT 0x10C4
109 109 #define E1000_DEV_ID_ICH8_IFE_G 0x10C5
110 110 #define E1000_DEV_ID_ICH8_IGP_M 0x104D
111 111 #define E1000_DEV_ID_ICH9_IGP_M 0x10BF
112 112 #define E1000_DEV_ID_ICH9_IGP_M_AMT 0x10F5
113 113 #define E1000_DEV_ID_ICH9_IGP_M_V 0x10CB
114 114 #define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD
115 115 #define E1000_DEV_ID_ICH9_BM 0x10E5
116 116 #define E1000_DEV_ID_ICH9_IGP_C 0x294C
117 117 #define E1000_DEV_ID_ICH9_IFE 0x10C0
118 118 #define E1000_DEV_ID_ICH9_IFE_GT 0x10C3
119 119 #define E1000_DEV_ID_ICH9_IFE_G 0x10C2
120 120 #define E1000_DEV_ID_ICH10_R_BM_LM 0x10CC
121 121 #define E1000_DEV_ID_ICH10_R_BM_LF 0x10CD
122 122 #define E1000_DEV_ID_ICH10_R_BM_V 0x10CE
123 123 #define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE
124 124 #define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF
125 125 #define E1000_DEV_ID_ICH10_D_BM_V 0x1525
126 126 #define E1000_DEV_ID_PCH_M_HV_LM 0x10EA
127 127 #define E1000_DEV_ID_PCH_M_HV_LC 0x10EB
128 128 #define E1000_DEV_ID_PCH_D_HV_DM 0x10EF
129 129 #define E1000_DEV_ID_PCH_D_HV_DC 0x10F0
130 130 #define E1000_DEV_ID_PCH2_LV_LM 0x1502
131 131 #define E1000_DEV_ID_PCH2_LV_V 0x1503
132 132 #define E1000_DEV_ID_PCH_LPT_I217_LM 0x153A
133 133 #define E1000_DEV_ID_PCH_LPT_I217_V 0x153B
134 134 #define E1000_DEV_ID_PCH_LPTLP_I218_LM 0x155A
135 135 #define E1000_DEV_ID_PCH_LPTLP_I218_V 0x1559
136 136 #define E1000_DEV_ID_PCH_I218_LM2 0x15A0
137 137 #define E1000_DEV_ID_PCH_I218_V2 0x15A1
138 138 #define E1000_DEV_ID_PCH_I218_LM3 0x15A2 /* Wildcat Point PCH */
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139 139 #define E1000_DEV_ID_PCH_I218_V3 0x15A3 /* Wildcat Point PCH */
140 140 #define E1000_DEV_ID_PCH_SPT_I219_LM 0x156F /* Sunrise Point PCH */
141 141 #define E1000_DEV_ID_PCH_SPT_I219_V 0x1570 /* Sunrise Point PCH */
142 142 #define E1000_DEV_ID_PCH_SPT_I219_LM2 0x15B7 /* Sunrise Point-H PCH */
143 143 #define E1000_DEV_ID_PCH_SPT_I219_V2 0x15B8 /* Sunrise Point-H PCH */
144 144 #define E1000_DEV_ID_PCH_LBG_I219_LM3 0x15B9 /* LEWISBURG PCH */
145 145 #define E1000_DEV_ID_PCH_SPT_I219_LM4 0x15D7
146 146 #define E1000_DEV_ID_PCH_SPT_I219_V4 0x15D8
147 147 #define E1000_DEV_ID_PCH_SPT_I219_LM5 0x15E3
148 148 #define E1000_DEV_ID_PCH_SPT_I219_V5 0x15D6
149 +#define E1000_DEV_ID_PCH_CNP_I219_LM6 0x15BD
150 +#define E1000_DEV_ID_PCH_CNP_I219_V6 0x15BE
151 +#define E1000_DEV_ID_PCH_CNP_I219_LM7 0x15BB
152 +#define E1000_DEV_ID_PCH_CNP_I219_V7 0x15BC
153 +#define E1000_DEV_ID_PCH_ICP_I219_LM8 0x15DF
154 +#define E1000_DEV_ID_PCH_ICP_I219_V8 0x15E0
155 +#define E1000_DEV_ID_PCH_ICP_I219_LM9 0x15E1
156 +#define E1000_DEV_ID_PCH_ICP_I219_V9 0x15E2
149 157 #define E1000_DEV_ID_82576 0x10C9
150 158 #define E1000_DEV_ID_82576_FIBER 0x10E6
151 159 #define E1000_DEV_ID_82576_SERDES 0x10E7
152 160 #define E1000_DEV_ID_82576_QUAD_COPPER 0x10E8
153 161 #define E1000_DEV_ID_82576_QUAD_COPPER_ET2 0x1526
154 162 #define E1000_DEV_ID_82576_NS 0x150A
155 163 #define E1000_DEV_ID_82576_NS_SERDES 0x1518
156 164 #define E1000_DEV_ID_82576_SERDES_QUAD 0x150D
157 165 #define E1000_DEV_ID_82576_VF 0x10CA
158 166 #define E1000_DEV_ID_82576_VF_HV 0x152D
159 167 #define E1000_DEV_ID_I350_VF 0x1520
160 168 #define E1000_DEV_ID_I350_VF_HV 0x152F
161 169 #define E1000_DEV_ID_82575EB_COPPER 0x10A7
162 170 #define E1000_DEV_ID_82575EB_FIBER_SERDES 0x10A9
163 171 #define E1000_DEV_ID_82575GB_QUAD_COPPER 0x10D6
164 172 #define E1000_DEV_ID_82580_COPPER 0x150E
165 173 #define E1000_DEV_ID_82580_FIBER 0x150F
166 174 #define E1000_DEV_ID_82580_SERDES 0x1510
167 175 #define E1000_DEV_ID_82580_SGMII 0x1511
168 176 #define E1000_DEV_ID_82580_COPPER_DUAL 0x1516
169 177 #define E1000_DEV_ID_82580_QUAD_FIBER 0x1527
170 178 #define E1000_DEV_ID_I350_COPPER 0x1521
171 179 #define E1000_DEV_ID_I350_FIBER 0x1522
172 180 #define E1000_DEV_ID_I350_SERDES 0x1523
173 181 #define E1000_DEV_ID_I350_SGMII 0x1524
174 182 #define E1000_DEV_ID_I350_DA4 0x1546
175 183 #define E1000_DEV_ID_I210_COPPER 0x1533
176 184 #define E1000_DEV_ID_I210_COPPER_OEM1 0x1534
177 185 #define E1000_DEV_ID_I210_COPPER_IT 0x1535
178 186 #define E1000_DEV_ID_I210_FIBER 0x1536
179 187 #define E1000_DEV_ID_I210_SERDES 0x1537
180 188 #define E1000_DEV_ID_I210_SGMII 0x1538
181 189 #define E1000_DEV_ID_I210_COPPER_FLASHLESS 0x157B
182 190 #define E1000_DEV_ID_I210_SERDES_FLASHLESS 0x157C
183 191 #define E1000_DEV_ID_I211_COPPER 0x1539
184 192 #define E1000_DEV_ID_I354_BACKPLANE_1GBPS 0x1F40
185 193 #define E1000_DEV_ID_I354_SGMII 0x1F41
186 194 #define E1000_DEV_ID_I354_BACKPLANE_2_5GBPS 0x1F45
187 195 #define E1000_DEV_ID_DH89XXCC_SGMII 0x0438
188 196 #define E1000_DEV_ID_DH89XXCC_SERDES 0x043A
189 197 #define E1000_DEV_ID_DH89XXCC_BACKPLANE 0x043C
190 198 #define E1000_DEV_ID_DH89XXCC_SFP 0x0440
191 199
192 200 #define E1000_REVISION_0 0
193 201 #define E1000_REVISION_1 1
194 202 #define E1000_REVISION_2 2
195 203 #define E1000_REVISION_3 3
196 204 #define E1000_REVISION_4 4
197 205
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198 206 #define E1000_FUNC_0 0
199 207 #define E1000_FUNC_1 1
200 208 #define E1000_FUNC_2 2
201 209 #define E1000_FUNC_3 3
202 210
203 211 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0
204 212 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3
205 213 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2 6
206 214 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3 9
207 215
216 +/*
217 + * This enumeration represents all of the different kinds of MAC chips that are
218 + * used by both the e1000g and igb drivers. The ordering here is important as
219 + * certain classes of MACs are very similar, but have minor differences and so
220 + * are compared based on the ordering here. Changing the order here should not
221 + * be done arbitrarily.
222 + */
208 223 enum e1000_mac_type {
209 224 e1000_undefined = 0,
210 225 e1000_82542,
211 226 e1000_82543,
212 227 e1000_82544,
213 228 e1000_82540,
214 229 e1000_82545,
215 230 e1000_82545_rev_3,
216 231 e1000_82546,
217 232 e1000_82546_rev_3,
218 233 e1000_82541,
219 234 e1000_82541_rev_2,
220 235 e1000_82547,
221 236 e1000_82547_rev_2,
222 237 e1000_82571,
223 238 e1000_82572,
224 239 e1000_82573,
225 240 e1000_82574,
226 241 e1000_82583,
227 242 e1000_80003es2lan,
243 + /*
244 + * The following MACs all share the ich8 style of hardware and are
245 + * implemented in ich8, though some are a little more different than
246 + * others. The pch_lpt, pch_spt, and pch_cnp family are a bit more
247 + * different than the others and just have slight variants in behavior
248 + * between them. They are ordered based on release.
249 + */
228 250 e1000_ich8lan,
229 251 e1000_ich9lan,
230 252 e1000_ich10lan,
231 253 e1000_pchlan,
232 254 e1000_pch2lan,
233 255 e1000_pch_lpt,
234 256 e1000_pch_spt,
257 + e1000_pch_cnp,
258 + /*
259 + * After this point all MACs are used by the igb(7D) driver as opposed
260 + * to e1000g(7D). If a new MAC is specific to e1000g series of devices,
261 + * then it should be added above this.
262 + */
235 263 e1000_82575,
236 264 e1000_82576,
237 265 e1000_82580,
238 266 e1000_i350,
239 267 e1000_i354,
240 268 e1000_i210,
241 269 e1000_i211,
242 270 e1000_vfadapt,
243 271 e1000_vfadapt_i350,
244 272 e1000_num_macs /* List is 1-based, so subtract 1 for TRUE count. */
245 273 };
246 274
247 275 enum e1000_media_type {
248 276 e1000_media_type_unknown = 0,
249 277 e1000_media_type_copper = 1,
250 278 e1000_media_type_fiber = 2,
251 279 e1000_media_type_internal_serdes = 3,
252 280 e1000_num_media_types
253 281 };
254 282
255 283 enum e1000_nvm_type {
256 284 e1000_nvm_unknown = 0,
257 285 e1000_nvm_none,
258 286 e1000_nvm_eeprom_spi,
259 287 e1000_nvm_eeprom_microwire,
260 288 e1000_nvm_flash_hw,
261 289 e1000_nvm_invm,
262 290 e1000_nvm_flash_sw
263 291 };
264 292
265 293 enum e1000_nvm_override {
266 294 e1000_nvm_override_none = 0,
267 295 e1000_nvm_override_spi_small,
268 296 e1000_nvm_override_spi_large,
269 297 e1000_nvm_override_microwire_small,
270 298 e1000_nvm_override_microwire_large
271 299 };
272 300
273 301 enum e1000_phy_type {
274 302 e1000_phy_unknown = 0,
275 303 e1000_phy_none,
276 304 e1000_phy_m88,
277 305 e1000_phy_igp,
278 306 e1000_phy_igp_2,
279 307 e1000_phy_gg82563,
280 308 e1000_phy_igp_3,
281 309 e1000_phy_ife,
282 310 e1000_phy_bm,
283 311 e1000_phy_82578,
284 312 e1000_phy_82577,
285 313 e1000_phy_82579,
286 314 e1000_phy_i217,
287 315 e1000_phy_82580,
288 316 e1000_phy_vf,
289 317 e1000_phy_i210,
290 318 };
291 319
292 320 enum e1000_bus_type {
293 321 e1000_bus_type_unknown = 0,
294 322 e1000_bus_type_pci,
295 323 e1000_bus_type_pcix,
296 324 e1000_bus_type_pci_express,
297 325 e1000_bus_type_reserved
298 326 };
299 327
300 328 enum e1000_bus_speed {
301 329 e1000_bus_speed_unknown = 0,
302 330 e1000_bus_speed_33,
303 331 e1000_bus_speed_66,
304 332 e1000_bus_speed_100,
305 333 e1000_bus_speed_120,
306 334 e1000_bus_speed_133,
307 335 e1000_bus_speed_2500,
308 336 e1000_bus_speed_5000,
309 337 e1000_bus_speed_reserved
310 338 };
311 339
312 340 enum e1000_bus_width {
313 341 e1000_bus_width_unknown = 0,
314 342 e1000_bus_width_pcie_x1,
315 343 e1000_bus_width_pcie_x2,
316 344 e1000_bus_width_pcie_x4 = 4,
317 345 e1000_bus_width_pcie_x8 = 8,
318 346 e1000_bus_width_32,
319 347 e1000_bus_width_64,
320 348 e1000_bus_width_reserved
321 349 };
322 350
323 351 enum e1000_1000t_rx_status {
324 352 e1000_1000t_rx_status_not_ok = 0,
325 353 e1000_1000t_rx_status_ok,
326 354 e1000_1000t_rx_status_undefined = 0xFF
327 355 };
328 356
329 357 enum e1000_rev_polarity {
330 358 e1000_rev_polarity_normal = 0,
331 359 e1000_rev_polarity_reversed,
332 360 e1000_rev_polarity_undefined = 0xFF
333 361 };
334 362
335 363 enum e1000_fc_mode {
336 364 e1000_fc_none = 0,
337 365 e1000_fc_rx_pause,
338 366 e1000_fc_tx_pause,
339 367 e1000_fc_full,
340 368 e1000_fc_default = 0xFF
341 369 };
342 370
343 371 enum e1000_ffe_config {
344 372 e1000_ffe_config_enabled = 0,
345 373 e1000_ffe_config_active,
346 374 e1000_ffe_config_blocked
347 375 };
348 376
349 377 enum e1000_dsp_config {
350 378 e1000_dsp_config_disabled = 0,
351 379 e1000_dsp_config_enabled,
352 380 e1000_dsp_config_activated,
353 381 e1000_dsp_config_undefined = 0xFF
354 382 };
355 383
356 384 enum e1000_ms_type {
357 385 e1000_ms_hw_default = 0,
358 386 e1000_ms_force_master,
359 387 e1000_ms_force_slave,
360 388 e1000_ms_auto
361 389 };
362 390
363 391 enum e1000_smart_speed {
364 392 e1000_smart_speed_default = 0,
365 393 e1000_smart_speed_on,
366 394 e1000_smart_speed_off
367 395 };
368 396
369 397 enum e1000_serdes_link_state {
370 398 e1000_serdes_link_down = 0,
371 399 e1000_serdes_link_autoneg_progress,
372 400 e1000_serdes_link_autoneg_complete,
373 401 e1000_serdes_link_forced_up
374 402 };
375 403
376 404 #define __le16 u16
377 405 #define __le32 u32
378 406 #define __le64 u64
379 407 /* Receive Descriptor */
380 408 struct e1000_rx_desc {
381 409 __le64 buffer_addr; /* Address of the descriptor's data buffer */
382 410 __le16 length; /* Length of data DMAed into data buffer */
383 411 __le16 csum; /* Packet checksum */
384 412 u8 status; /* Descriptor status */
385 413 u8 errors; /* Descriptor Errors */
386 414 __le16 special;
387 415 };
388 416
389 417 /* Receive Descriptor - Extended */
390 418 union e1000_rx_desc_extended {
391 419 struct {
392 420 __le64 buffer_addr;
393 421 __le64 reserved;
394 422 } read;
395 423 struct {
396 424 struct {
397 425 __le32 mrq; /* Multiple Rx Queues */
398 426 union {
399 427 __le32 rss; /* RSS Hash */
400 428 struct {
401 429 __le16 ip_id; /* IP id */
402 430 __le16 csum; /* Packet Checksum */
403 431 } csum_ip;
404 432 } hi_dword;
405 433 } lower;
406 434 struct {
407 435 __le32 status_error; /* ext status/error */
408 436 __le16 length;
409 437 __le16 vlan; /* VLAN tag */
410 438 } upper;
411 439 } wb; /* writeback */
412 440 };
413 441
414 442 #define MAX_PS_BUFFERS 4
415 443
416 444 /* Number of packet split data buffers (not including the header buffer) */
417 445 #define PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1)
418 446
419 447 /* Receive Descriptor - Packet Split */
420 448 union e1000_rx_desc_packet_split {
421 449 struct {
422 450 /* one buffer for protocol header(s), three data buffers */
423 451 __le64 buffer_addr[MAX_PS_BUFFERS];
424 452 } read;
425 453 struct {
426 454 struct {
427 455 __le32 mrq; /* Multiple Rx Queues */
428 456 union {
429 457 __le32 rss; /* RSS Hash */
430 458 struct {
431 459 __le16 ip_id; /* IP id */
432 460 __le16 csum; /* Packet Checksum */
433 461 } csum_ip;
434 462 } hi_dword;
435 463 } lower;
436 464 struct {
437 465 __le32 status_error; /* ext status/error */
438 466 __le16 length0; /* length of buffer 0 */
439 467 __le16 vlan; /* VLAN tag */
440 468 } middle;
441 469 struct {
442 470 __le16 header_status;
443 471 /* length of buffers 1-3 */
444 472 __le16 length[PS_PAGE_BUFFERS];
445 473 } upper;
446 474 __le64 reserved;
447 475 } wb; /* writeback */
448 476 };
449 477
450 478 /* Transmit Descriptor */
451 479 struct e1000_tx_desc {
452 480 __le64 buffer_addr; /* Address of the descriptor's data buffer */
453 481 union {
454 482 __le32 data;
455 483 struct {
456 484 __le16 length; /* Data buffer length */
457 485 u8 cso; /* Checksum offset */
458 486 u8 cmd; /* Descriptor control */
459 487 } flags;
460 488 } lower;
461 489 union {
462 490 __le32 data;
463 491 struct {
464 492 u8 status; /* Descriptor status */
465 493 u8 css; /* Checksum start */
466 494 __le16 special;
467 495 } fields;
468 496 } upper;
469 497 };
470 498
471 499 /* Offload Context Descriptor */
472 500 struct e1000_context_desc {
473 501 union {
474 502 __le32 ip_config;
475 503 struct {
476 504 u8 ipcss; /* IP checksum start */
477 505 u8 ipcso; /* IP checksum offset */
478 506 __le16 ipcse; /* IP checksum end */
479 507 } ip_fields;
480 508 } lower_setup;
481 509 union {
482 510 __le32 tcp_config;
483 511 struct {
484 512 u8 tucss; /* TCP checksum start */
485 513 u8 tucso; /* TCP checksum offset */
486 514 __le16 tucse; /* TCP checksum end */
487 515 } tcp_fields;
488 516 } upper_setup;
489 517 __le32 cmd_and_length;
490 518 union {
491 519 __le32 data;
492 520 struct {
493 521 u8 status; /* Descriptor status */
494 522 u8 hdr_len; /* Header length */
495 523 __le16 mss; /* Maximum segment size */
496 524 } fields;
497 525 } tcp_seg_setup;
498 526 };
499 527
500 528 /* Offload data descriptor */
501 529 struct e1000_data_desc {
502 530 __le64 buffer_addr; /* Address of the descriptor's buffer address */
503 531 union {
504 532 __le32 data;
505 533 struct {
506 534 __le16 length; /* Data buffer length */
507 535 u8 typ_len_ext;
508 536 u8 cmd;
509 537 } flags;
510 538 } lower;
511 539 union {
512 540 __le32 data;
513 541 struct {
514 542 u8 status; /* Descriptor status */
515 543 u8 popts; /* Packet Options */
516 544 __le16 special;
517 545 } fields;
518 546 } upper;
519 547 };
520 548
521 549 /* Statistics counters collected by the MAC */
522 550 struct e1000_hw_stats {
523 551 u64 crcerrs;
524 552 u64 algnerrc;
525 553 u64 symerrs;
526 554 u64 rxerrc;
527 555 u64 mpc;
528 556 u64 scc;
529 557 u64 ecol;
530 558 u64 mcc;
531 559 u64 latecol;
532 560 u64 colc;
533 561 u64 dc;
534 562 u64 tncrs;
535 563 u64 sec;
536 564 u64 cexterr;
537 565 u64 rlec;
538 566 u64 xonrxc;
539 567 u64 xontxc;
540 568 u64 xoffrxc;
541 569 u64 xofftxc;
542 570 u64 fcruc;
543 571 u64 prc64;
544 572 u64 prc127;
545 573 u64 prc255;
546 574 u64 prc511;
547 575 u64 prc1023;
548 576 u64 prc1522;
549 577 u64 gprc;
550 578 u64 bprc;
551 579 u64 mprc;
552 580 u64 gptc;
553 581 u64 gorc;
554 582 u64 gotc;
555 583 u64 rnbc;
556 584 u64 ruc;
557 585 u64 rfc;
558 586 u64 roc;
559 587 u64 rjc;
560 588 u64 mgprc;
561 589 u64 mgpdc;
562 590 u64 mgptc;
563 591 u64 tor;
564 592 u64 tot;
565 593 u64 tpr;
566 594 u64 tpt;
567 595 u64 ptc64;
568 596 u64 ptc127;
569 597 u64 ptc255;
570 598 u64 ptc511;
571 599 u64 ptc1023;
572 600 u64 ptc1522;
573 601 u64 mptc;
574 602 u64 bptc;
575 603 u64 tsctc;
576 604 u64 tsctfc;
577 605 u64 iac;
578 606 u64 icrxptc;
579 607 u64 icrxatc;
580 608 u64 ictxptc;
581 609 u64 ictxatc;
582 610 u64 ictxqec;
583 611 u64 ictxqmtc;
584 612 u64 icrxdmtc;
585 613 u64 icrxoc;
586 614 u64 cbtmpc;
587 615 u64 htdpmc;
588 616 u64 cbrdpc;
589 617 u64 cbrmpc;
590 618 u64 rpthc;
591 619 u64 hgptc;
592 620 u64 htcbdpc;
593 621 u64 hgorc;
594 622 u64 hgotc;
595 623 u64 lenerrs;
596 624 u64 scvpc;
597 625 u64 hrmpc;
598 626 u64 doosync;
599 627 u64 o2bgptc;
600 628 u64 o2bspc;
601 629 u64 b2ospc;
602 630 u64 b2ogprc;
603 631 };
604 632
605 633 struct e1000_vf_stats {
606 634 u64 base_gprc;
607 635 u64 base_gptc;
608 636 u64 base_gorc;
609 637 u64 base_gotc;
610 638 u64 base_mprc;
611 639 u64 base_gotlbc;
612 640 u64 base_gptlbc;
613 641 u64 base_gorlbc;
614 642 u64 base_gprlbc;
615 643
616 644 u32 last_gprc;
617 645 u32 last_gptc;
618 646 u32 last_gorc;
619 647 u32 last_gotc;
620 648 u32 last_mprc;
621 649 u32 last_gotlbc;
622 650 u32 last_gptlbc;
623 651 u32 last_gorlbc;
624 652 u32 last_gprlbc;
625 653
626 654 u64 gprc;
627 655 u64 gptc;
628 656 u64 gorc;
629 657 u64 gotc;
630 658 u64 mprc;
631 659 u64 gotlbc;
632 660 u64 gptlbc;
633 661 u64 gorlbc;
634 662 u64 gprlbc;
635 663 };
636 664
637 665 struct e1000_phy_stats {
638 666 u32 idle_errors;
639 667 u32 receive_errors;
640 668 };
641 669
642 670 struct e1000_host_mng_dhcp_cookie {
643 671 u32 signature;
644 672 u8 status;
645 673 u8 reserved0;
646 674 u16 vlan_id;
647 675 u32 reserved1;
648 676 u16 reserved2;
649 677 u8 reserved3;
650 678 u8 checksum;
651 679 };
652 680
653 681 /* Host Interface "Rev 1" */
654 682 struct e1000_host_command_header {
655 683 u8 command_id;
656 684 u8 command_length;
657 685 u8 command_options;
658 686 u8 checksum;
659 687 };
660 688
661 689 #define E1000_HI_MAX_DATA_LENGTH 252
662 690 struct e1000_host_command_info {
663 691 struct e1000_host_command_header command_header;
664 692 u8 command_data[E1000_HI_MAX_DATA_LENGTH];
665 693 };
666 694
667 695 /* Host Interface "Rev 2" */
668 696 struct e1000_host_mng_command_header {
669 697 u8 command_id;
670 698 u8 checksum;
671 699 u16 reserved1;
672 700 u16 reserved2;
673 701 u16 command_length;
674 702 };
675 703
676 704 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
677 705 struct e1000_host_mng_command_info {
678 706 struct e1000_host_mng_command_header command_header;
679 707 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
680 708 };
681 709
682 710 #include "e1000_mac.h"
683 711 #include "e1000_phy.h"
684 712 #include "e1000_nvm.h"
685 713 #include "e1000_manage.h"
686 714 #include "e1000_mbx.h"
687 715
688 716 /* Function pointers for the MAC. */
689 717 struct e1000_mac_operations {
690 718 s32 (*init_params)(struct e1000_hw *);
691 719 s32 (*id_led_init)(struct e1000_hw *);
692 720 s32 (*blink_led)(struct e1000_hw *);
693 721 bool (*check_mng_mode)(struct e1000_hw *);
694 722 s32 (*check_for_link)(struct e1000_hw *);
695 723 s32 (*cleanup_led)(struct e1000_hw *);
696 724 void (*clear_hw_cntrs)(struct e1000_hw *);
697 725 void (*clear_vfta)(struct e1000_hw *);
698 726 s32 (*get_bus_info)(struct e1000_hw *);
699 727 void (*set_lan_id)(struct e1000_hw *);
700 728 s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
701 729 s32 (*led_on)(struct e1000_hw *);
702 730 s32 (*led_off)(struct e1000_hw *);
703 731 void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);
704 732 s32 (*reset_hw)(struct e1000_hw *);
705 733 s32 (*init_hw)(struct e1000_hw *);
706 734 void (*shutdown_serdes)(struct e1000_hw *);
707 735 void (*power_up_serdes)(struct e1000_hw *);
708 736 s32 (*setup_link)(struct e1000_hw *);
709 737 s32 (*setup_physical_interface)(struct e1000_hw *);
710 738 s32 (*setup_led)(struct e1000_hw *);
711 739 void (*write_vfta)(struct e1000_hw *, u32, u32);
712 740 void (*config_collision_dist)(struct e1000_hw *);
713 741 int (*rar_set)(struct e1000_hw *, u8*, u32);
714 742 s32 (*read_mac_addr)(struct e1000_hw *);
715 743 s32 (*validate_mdi_setting)(struct e1000_hw *);
716 744 s32 (*set_obff_timer)(struct e1000_hw *, u32);
717 745 s32 (*acquire_swfw_sync)(struct e1000_hw *, u16);
718 746 void (*release_swfw_sync)(struct e1000_hw *, u16);
719 747 };
720 748
721 749 /* When to use various PHY register access functions:
722 750 *
723 751 * Func Caller
724 752 * Function Does Does When to use
725 753 * ~~~~~~~~~~~~ ~~~~~ ~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
726 754 * X_reg L,P,A n/a for simple PHY reg accesses
727 755 * X_reg_locked P,A L for multiple accesses of different regs
728 756 * on different pages
729 757 * X_reg_page A L,P for multiple accesses of different regs
730 758 * on the same page
731 759 *
732 760 * Where X=[read|write], L=locking, P=sets page, A=register access
733 761 *
734 762 */
735 763 struct e1000_phy_operations {
736 764 s32 (*init_params)(struct e1000_hw *);
737 765 s32 (*acquire)(struct e1000_hw *);
738 766 s32 (*cfg_on_link_up)(struct e1000_hw *);
739 767 s32 (*check_polarity)(struct e1000_hw *);
740 768 s32 (*check_reset_block)(struct e1000_hw *);
741 769 s32 (*commit)(struct e1000_hw *);
742 770 s32 (*force_speed_duplex)(struct e1000_hw *);
743 771 s32 (*get_cfg_done)(struct e1000_hw *hw);
744 772 s32 (*get_cable_length)(struct e1000_hw *);
745 773 s32 (*get_info)(struct e1000_hw *);
746 774 s32 (*set_page)(struct e1000_hw *, u16);
747 775 s32 (*read_reg)(struct e1000_hw *, u32, u16 *);
748 776 s32 (*read_reg_locked)(struct e1000_hw *, u32, u16 *);
749 777 s32 (*read_reg_page)(struct e1000_hw *, u32, u16 *);
750 778 void (*release)(struct e1000_hw *);
751 779 s32 (*reset)(struct e1000_hw *);
752 780 s32 (*set_d0_lplu_state)(struct e1000_hw *, bool);
753 781 s32 (*set_d3_lplu_state)(struct e1000_hw *, bool);
754 782 s32 (*write_reg)(struct e1000_hw *, u32, u16);
755 783 s32 (*write_reg_locked)(struct e1000_hw *, u32, u16);
756 784 s32 (*write_reg_page)(struct e1000_hw *, u32, u16);
757 785 void (*power_up)(struct e1000_hw *);
758 786 void (*power_down)(struct e1000_hw *);
759 787 s32 (*read_i2c_byte)(struct e1000_hw *, u8, u8, u8 *);
760 788 s32 (*write_i2c_byte)(struct e1000_hw *, u8, u8, u8);
761 789 };
762 790
763 791 /* Function pointers for the NVM. */
764 792 struct e1000_nvm_operations {
765 793 s32 (*init_params)(struct e1000_hw *);
766 794 s32 (*acquire)(struct e1000_hw *);
767 795 s32 (*read)(struct e1000_hw *, u16, u16, u16 *);
768 796 void (*release)(struct e1000_hw *);
769 797 void (*reload)(struct e1000_hw *);
770 798 s32 (*update)(struct e1000_hw *);
771 799 s32 (*valid_led_default)(struct e1000_hw *, u16 *);
772 800 s32 (*validate)(struct e1000_hw *);
773 801 s32 (*write)(struct e1000_hw *, u16, u16, u16 *);
774 802 };
775 803
776 804 struct e1000_mac_info {
777 805 struct e1000_mac_operations ops;
778 806 u8 addr[ETH_ADDR_LEN];
779 807 u8 perm_addr[ETH_ADDR_LEN];
780 808
781 809 enum e1000_mac_type type;
782 810
783 811 u32 collision_delta;
784 812 u32 ledctl_default;
785 813 u32 ledctl_mode1;
786 814 u32 ledctl_mode2;
787 815 u32 mc_filter_type;
788 816 u32 tx_packet_delta;
789 817 u32 txcw;
790 818
791 819 u16 current_ifs_val;
792 820 u16 ifs_max_val;
793 821 u16 ifs_min_val;
794 822 u16 ifs_ratio;
795 823 u16 ifs_step_size;
796 824 u16 mta_reg_count;
797 825 u16 uta_reg_count;
798 826
799 827 /* Maximum size of the MTA register table in all supported adapters */
800 828 #define MAX_MTA_REG 128
801 829 u32 mta_shadow[MAX_MTA_REG];
802 830 u16 rar_entry_count;
803 831
804 832 u8 forced_speed_duplex;
805 833
806 834 bool adaptive_ifs;
807 835 bool has_fwsm;
808 836 bool arc_subsystem_valid;
809 837 bool asf_firmware_present;
810 838 bool autoneg;
811 839 bool autoneg_failed;
812 840 bool get_link_status;
813 841 bool in_ifs_mode;
814 842 bool report_tx_early;
815 843 enum e1000_serdes_link_state serdes_link_state;
816 844 bool serdes_has_link;
817 845 bool tx_pkt_filtering;
818 846 u32 max_frame_size;
819 847 };
820 848
821 849 struct e1000_phy_info {
822 850 struct e1000_phy_operations ops;
823 851 enum e1000_phy_type type;
824 852
825 853 enum e1000_1000t_rx_status local_rx;
826 854 enum e1000_1000t_rx_status remote_rx;
827 855 enum e1000_ms_type ms_type;
828 856 enum e1000_ms_type original_ms_type;
829 857 enum e1000_rev_polarity cable_polarity;
830 858 enum e1000_smart_speed smart_speed;
831 859
832 860 u32 addr;
833 861 u32 id;
834 862 u32 reset_delay_us; /* in usec */
835 863 u32 revision;
836 864
837 865 enum e1000_media_type media_type;
838 866
839 867 u16 autoneg_advertised;
840 868 u16 autoneg_mask;
841 869 u16 cable_length;
842 870 u16 max_cable_length;
843 871 u16 min_cable_length;
844 872
845 873 u8 mdix;
846 874
847 875 bool disable_polarity_correction;
848 876 bool is_mdix;
849 877 bool polarity_correction;
850 878 bool speed_downgraded;
851 879 bool autoneg_wait_to_complete;
852 880 };
853 881
854 882 struct e1000_nvm_info {
855 883 struct e1000_nvm_operations ops;
856 884 enum e1000_nvm_type type;
857 885 enum e1000_nvm_override override;
858 886
859 887 u32 flash_bank_size;
860 888 u32 flash_base_addr;
861 889
862 890 u16 word_size;
863 891 u16 delay_usec;
864 892 u16 address_bits;
865 893 u16 opcode_bits;
866 894 u16 page_size;
867 895 };
868 896
869 897 struct e1000_bus_info {
870 898 enum e1000_bus_type type;
871 899 enum e1000_bus_speed speed;
872 900 enum e1000_bus_width width;
873 901
874 902 u16 func;
875 903 u16 pci_cmd_word;
876 904 };
877 905
878 906 struct e1000_fc_info {
879 907 u32 high_water; /* Flow control high-water mark */
880 908 u32 low_water; /* Flow control low-water mark */
881 909 u16 pause_time; /* Flow control pause timer */
882 910 u16 refresh_time; /* Flow control refresh timer */
883 911 bool send_xon; /* Flow control send XON */
884 912 bool strict_ieee; /* Strict IEEE mode */
885 913 enum e1000_fc_mode current_mode; /* FC mode in effect */
886 914 enum e1000_fc_mode requested_mode; /* FC mode requested by caller */
887 915 };
888 916
889 917 struct e1000_mbx_operations {
890 918 s32 (*init_params)(struct e1000_hw *hw);
891 919 s32 (*read)(struct e1000_hw *, u32 *, u16, u16);
892 920 s32 (*write)(struct e1000_hw *, u32 *, u16, u16);
893 921 s32 (*read_posted)(struct e1000_hw *, u32 *, u16, u16);
894 922 s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16);
895 923 s32 (*check_for_msg)(struct e1000_hw *, u16);
896 924 s32 (*check_for_ack)(struct e1000_hw *, u16);
897 925 s32 (*check_for_rst)(struct e1000_hw *, u16);
898 926 };
899 927
900 928 struct e1000_mbx_stats {
901 929 u32 msgs_tx;
902 930 u32 msgs_rx;
903 931
904 932 u32 acks;
905 933 u32 reqs;
906 934 u32 rsts;
907 935 };
908 936
909 937 struct e1000_mbx_info {
910 938 struct e1000_mbx_operations ops;
911 939 struct e1000_mbx_stats stats;
912 940 u32 timeout;
913 941 u32 usec_delay;
914 942 u16 size;
915 943 };
916 944
917 945 struct e1000_dev_spec_82541 {
918 946 enum e1000_dsp_config dsp_config;
919 947 enum e1000_ffe_config ffe_config;
920 948 u32 tx_fifo_head;
921 949 u32 tx_fifo_start;
922 950 u32 tx_fifo_size;
923 951 u16 dsp_reset_counter;
924 952 u16 spd_default;
925 953 bool phy_init_script;
926 954 bool ttl_workaround;
927 955 };
928 956
929 957 struct e1000_dev_spec_82542 {
930 958 bool dma_fairness;
931 959 };
932 960
933 961 struct e1000_dev_spec_82543 {
934 962 u32 tbi_compatibility;
935 963 bool dma_fairness;
936 964 bool init_phy_disabled;
937 965 };
938 966
939 967 struct e1000_dev_spec_82571 {
940 968 bool laa_is_present;
941 969 u32 smb_counter;
942 970 E1000_MUTEX swflag_mutex;
943 971 };
944 972
945 973 struct e1000_dev_spec_80003es2lan {
946 974 bool mdic_wa_enable;
947 975 };
948 976
949 977 struct e1000_shadow_ram {
950 978 u16 value;
951 979 bool modified;
952 980 };
953 981
954 982 #define E1000_SHADOW_RAM_WORDS 2048
955 983
956 984 /* I218 PHY Ultra Low Power (ULP) states */
957 985 enum e1000_ulp_state {
958 986 e1000_ulp_state_unknown,
959 987 e1000_ulp_state_off,
960 988 e1000_ulp_state_on,
961 989 };
962 990
963 991 struct e1000_dev_spec_ich8lan {
964 992 bool kmrn_lock_loss_workaround_enabled;
965 993 struct e1000_shadow_ram shadow_ram[E1000_SHADOW_RAM_WORDS];
966 994 E1000_MUTEX nvm_mutex;
967 995 E1000_MUTEX swflag_mutex;
968 996 bool nvm_k1_enabled;
969 997 bool disable_k1_off;
970 998 bool eee_disable;
971 999 u16 eee_lp_ability;
972 1000 enum e1000_ulp_state ulp_state;
973 1001 bool ulp_capability_disabled;
974 1002 bool during_suspend_flow;
975 1003 bool during_dpg_exit;
976 1004 };
977 1005
978 1006 struct e1000_dev_spec_82575 {
979 1007 bool sgmii_active;
980 1008 bool global_device_reset;
981 1009 bool eee_disable;
982 1010 bool module_plugged;
983 1011 bool clear_semaphore_once;
984 1012 u32 mtu;
985 1013 struct sfp_e1000_flags eth_flags;
986 1014 u8 media_port;
987 1015 bool media_changed;
988 1016 };
989 1017
990 1018 struct e1000_dev_spec_vf {
991 1019 u32 vf_number;
992 1020 u32 v2p_mailbox;
993 1021 };
994 1022
995 1023 struct e1000_hw {
996 1024 void *back;
997 1025
998 1026 u8 *hw_addr;
999 1027 u8 *flash_address;
1000 1028 unsigned long io_base;
1001 1029
1002 1030 struct e1000_mac_info mac;
1003 1031 struct e1000_fc_info fc;
1004 1032 struct e1000_phy_info phy;
1005 1033 struct e1000_nvm_info nvm;
1006 1034 struct e1000_bus_info bus;
1007 1035 struct e1000_mbx_info mbx;
1008 1036 struct e1000_host_mng_dhcp_cookie mng_cookie;
1009 1037
1010 1038 union {
1011 1039 struct e1000_dev_spec_82541 _82541;
1012 1040 struct e1000_dev_spec_82542 _82542;
1013 1041 struct e1000_dev_spec_82543 _82543;
1014 1042 struct e1000_dev_spec_82571 _82571;
1015 1043 struct e1000_dev_spec_80003es2lan _80003es2lan;
1016 1044 struct e1000_dev_spec_ich8lan ich8lan;
1017 1045 struct e1000_dev_spec_82575 _82575;
1018 1046 struct e1000_dev_spec_vf vf;
1019 1047 } dev_spec;
1020 1048
1021 1049 u16 device_id;
1022 1050 u16 subsystem_vendor_id;
1023 1051 u16 subsystem_device_id;
1024 1052 u16 vendor_id;
1025 1053
1026 1054 u8 revision_id;
1027 1055 };
1028 1056
1029 1057 #include "e1000_82541.h"
1030 1058 #include "e1000_82543.h"
1031 1059 #include "e1000_82571.h"
1032 1060 #include "e1000_80003es2lan.h"
1033 1061 #include "e1000_ich8lan.h"
1034 1062 #include "e1000_82575.h"
1035 1063 #include "e1000_i210.h"
1036 1064
1037 1065 /* These functions must be implemented by drivers */
1038 1066 void e1000_pci_clear_mwi(struct e1000_hw *hw);
1039 1067 void e1000_pci_set_mwi(struct e1000_hw *hw);
1040 1068 s32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
1041 1069 s32 e1000_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
1042 1070 void e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
1043 1071 void e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
1044 1072
1045 1073 #endif
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