1 /*
2 * This file and its contents are supplied under the terms of the
3 * Common Development and Distribution License ("CDDL"), version 1.0.
4 * You may only use this file in accordance with the terms of version
5 * 1.0 of the CDDL.
6 *
7 * A full copy of the text of the CDDL should have accompanied this
8 * source. A copy of the CDDL is also available via the Internet at
9 * http://www.illumos.org/license/CDDL.
10 */
11
12 /*
13 * This file is part of the Chelsio T4 support code.
14 *
15 * Copyright (C) 2011-2013 Chelsio Communications. All rights reserved.
16 *
17 * This program is distributed in the hope that it will be useful, but WITHOUT
18 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
19 * FITNESS FOR A PARTICULAR PURPOSE. See the LICENSE file included in this
20 * release for licensing terms and conditions.
21 */
22
23 #ifndef __T4NEX_H
24 #define __T4NEX_H
25
26 #ifdef __cplusplus
27 extern "C" {
28 #endif
29
30 #define T4_IOCTL ((('t' << 16) | '4') << 8)
31 #define T4_IOCTL_PCIGET32 (T4_IOCTL + 1)
32 #define T4_IOCTL_PCIPUT32 (T4_IOCTL + 2)
33 #define T4_IOCTL_GET32 (T4_IOCTL + 3)
34 #define T4_IOCTL_PUT32 (T4_IOCTL + 4)
35 #define T4_IOCTL_REGDUMP (T4_IOCTL + 5)
36 #define T4_IOCTL_SGE_CONTEXT (T4_IOCTL + 6)
37 #define T4_IOCTL_DEVLOG (T4_IOCTL + 7)
38 #define T4_IOCTL_GET_MEM (T4_IOCTL + 8)
39 #define T4_IOCTL_GET_TID_TAB (T4_IOCTL + 9)
40 #define T4_IOCTL_GET_MBOX (T4_IOCTL + 10)
41 #define T4_IOCTL_GET_CIM_LA (T4_IOCTL + 11)
42 #define T4_IOCTL_GET_CIM_QCFG (T4_IOCTL + 12)
43 #define T4_IOCTL_GET_CIM_IBQ (T4_IOCTL + 13)
44 #define T4_IOCTL_GET_EDC (T4_IOCTL + 14)
45 #define T4_IOCTL_LOAD_FW (T4_IOCTL + 15)
46
47 enum {
48 T4_CTXT_EGRESS,
49 T4_CTXT_INGRESS,
50 T4_CTXT_FLM
51 };
52
53 struct t4_reg32_cmd {
54 uint32_t reg;
55 uint32_t value;
56 };
57
58 #define T4_REGDUMP_SIZE (160 * 1024)
59 #define T5_REGDUMP_SIZE (332 * 1024)
60 struct t4_regdump {
61 uint32_t version;
62 uint32_t len;
63 uint8_t *data;
64 };
65
66 struct t4_sge_context {
67 uint32_t version;
68 uint32_t mem_id;
69 uint32_t addr;
70 uint32_t len;
71 uint8_t *data;
72 };
73
74 struct t4_mem_range {
75 uint32_t addr;
76 uint32_t len;
77 uint32_t *data;
78 };
79
80 struct t4_tid_info {
81 uint32_t len;
82 uint32_t *data;
83 };
84
85 struct t4_mbox {
86 uint32_t len;
87 uint32_t *data;
88 };
89
90 struct t4_cim_la {
91 uint32_t len;
92 uint32_t *data;
93 };
94
95 struct t4_ibq {
96 uint32_t len;
97 uint32_t *data;
98 };
99
100 struct t4_edc {
101 uint32_t len;
102 uint32_t mem;
103 uint32_t pos;
104 char *data;
105 };
106
107 struct t4_cim_qcfg {
108 uint16_t base[14];
109 uint16_t size[14];
110 uint16_t thres[6];
111 uint32_t stat[4 * (6 + 8)];
112 uint32_t obq_wr[2 * (8)];
113 uint32_t num_obq;
114 };
115
116 #define T4_DEVLOG_SIZE 32768
117 struct t4_devlog {
118 uint32_t len;
119 uint32_t data[0];
120 };
121
122 struct t4_ldfw {
123 uint32_t len;
124 uint32_t data[0];
125 };
126
127 #ifdef __cplusplus
128 }
129 #endif
130
131 #endif /* __T4NEX_H */