27 #include "t4nex.h"
28 #include "common/common.h"
29 #include "common/t4_regs.h"
30
31 /* helpers */
32 static int pci_rw(struct adapter *sc, void *data, int flags, int write);
33 static int reg_rw(struct adapter *sc, void *data, int flags, int write);
34 static void reg_block_dump(struct adapter *sc, uint8_t *buf, unsigned int start,
35 unsigned int end);
36 static int regdump(struct adapter *sc, void *data, int flags);
37 static int get_sge_context(struct adapter *sc, void *data, int flags);
38 static int get_devlog(struct adapter *sc, void *data, int flags);
39 static int validate_mem_range(struct adapter *, uint32_t, int);
40 static int read_card_mem(struct adapter *sc, void *data, int flags);
41 static int read_tid_tab(struct adapter *sc, void *data, int flags);
42 static int read_mbox(struct adapter *sc, void *data, int flags);
43 static int read_cim_la(struct adapter *sc, void *data, int flags);
44 static int read_cim_qcfg(struct adapter *sc, void *data, int flags);
45 static int read_cim_ibq(struct adapter *sc, void *data, int flags);
46 static int read_edc(struct adapter *sc, void *data, int flags);
47
48 int
49 t4_ioctl(struct adapter *sc, int cmd, void *data, int mode)
50 {
51 int rc = ENOTSUP;
52
53 switch (cmd) {
54 case T4_IOCTL_PCIGET32:
55 case T4_IOCTL_PCIPUT32:
56 rc = pci_rw(sc, data, mode, cmd == T4_IOCTL_PCIPUT32);
57 break;
58 case T4_IOCTL_GET32:
59 case T4_IOCTL_PUT32:
60 rc = reg_rw(sc, data, mode, cmd == T4_IOCTL_PUT32);
61 break;
62 case T4_IOCTL_REGDUMP:
63 rc = regdump(sc, data, mode);
64 break;
65 case T4_IOCTL_SGE_CONTEXT:
66 rc = get_sge_context(sc, data, mode);
72 rc = read_card_mem(sc, data, mode);
73 break;
74 case T4_IOCTL_GET_TID_TAB:
75 rc = read_tid_tab(sc, data, mode);
76 break;
77 case T4_IOCTL_GET_MBOX:
78 rc = read_mbox(sc, data, mode);
79 break;
80 case T4_IOCTL_GET_CIM_LA:
81 rc = read_cim_la(sc, data, mode);
82 break;
83 case T4_IOCTL_GET_CIM_QCFG:
84 rc = read_cim_qcfg(sc, data, mode);
85 break;
86 case T4_IOCTL_GET_CIM_IBQ:
87 rc = read_cim_ibq(sc, data, mode);
88 break;
89 case T4_IOCTL_GET_EDC:
90 rc = read_edc(sc, data, mode);
91 break;
92 default:
93 return (EINVAL);
94 }
95
96 return (rc);
97 }
98
99 static int
100 pci_rw(struct adapter *sc, void *data, int flags, int write)
101 {
102 struct t4_reg32_cmd r;
103
104 if (ddi_copyin(data, &r, sizeof (r), flags) < 0)
105 return (EFAULT);
106
107 /* address must be 32 bit aligned */
108 r.reg &= ~0x3;
109
110 if (write != 0)
111 t4_os_pci_write_cfg4(sc, r.reg, r.value);
1409 * to indicate that the buffer size was not enough. Return of
1410 * EFAULT indicates that the copyout was not successful.
1411 */
1412 rc = (rc == 0) ? ENOBUFS : EFAULT;
1413 goto done;
1414 }
1415
1416 buf = kmem_zalloc(dparams->size, KM_NOSLEEP);
1417 if (buf == NULL) {
1418 rc = ENOMEM;
1419 goto done;
1420 }
1421
1422 rc = -t4_memory_rw(sc, sc->params.drv_memwin, dparams->memtype,
1423 dparams->start, dparams->size, (void *)buf,
1424 T4_MEMORY_READ);
1425 if (rc != 0)
1426 goto done1;
1427
1428 /* Copyout device log buffer and then carrier buffer */
1429 if (ddi_copyout(buf, dl.data, dl.len, flags) < 0)
1430 rc = EFAULT;
1431 else if (ddi_copyout(&dl, data, sizeof (dl), flags) < 0)
1432 rc = EFAULT;
1433
1434 done1:
1435 kmem_free(buf, dparams->size);
1436
1437 done:
1438 return (rc);
1439 }
1440
1441 static int
1442 read_cim_qcfg(struct adapter *sc, void *data, int flags)
1443 {
1444 struct t4_cim_qcfg t4cimqcfg;
1445 int rc = 0;
1446 unsigned int ibq_rdaddr, obq_rdaddr, nq;
1447
1448 if (ddi_copyin(data, &t4cimqcfg, sizeof (t4cimqcfg), flags) < 0) {
1449 rc = EFAULT;
1450 goto _exit;
1451 }
1618 goto _exit;
1619 }
1620
1621 buf = p = kmem_zalloc(t4mbox.len, KM_NOSLEEP);
1622 if (buf == NULL) {
1623 rc = ENOMEM;
1624 goto _exit;
1625 }
1626
1627 for (i = 0; i < t4mbox.len; i += 8, p++)
1628 *p = t4_read_reg64(sc, data_reg + i);
1629
1630 if (ddi_copyout(buf, t4mbox.data, t4mbox.len, flags) < 0)
1631 rc = EFAULT;
1632
1633 kmem_free(buf, t4mbox.len);
1634
1635 _exit:
1636 return (rc);
1637 }
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27 #include "t4nex.h"
28 #include "common/common.h"
29 #include "common/t4_regs.h"
30
31 /* helpers */
32 static int pci_rw(struct adapter *sc, void *data, int flags, int write);
33 static int reg_rw(struct adapter *sc, void *data, int flags, int write);
34 static void reg_block_dump(struct adapter *sc, uint8_t *buf, unsigned int start,
35 unsigned int end);
36 static int regdump(struct adapter *sc, void *data, int flags);
37 static int get_sge_context(struct adapter *sc, void *data, int flags);
38 static int get_devlog(struct adapter *sc, void *data, int flags);
39 static int validate_mem_range(struct adapter *, uint32_t, int);
40 static int read_card_mem(struct adapter *sc, void *data, int flags);
41 static int read_tid_tab(struct adapter *sc, void *data, int flags);
42 static int read_mbox(struct adapter *sc, void *data, int flags);
43 static int read_cim_la(struct adapter *sc, void *data, int flags);
44 static int read_cim_qcfg(struct adapter *sc, void *data, int flags);
45 static int read_cim_ibq(struct adapter *sc, void *data, int flags);
46 static int read_edc(struct adapter *sc, void *data, int flags);
47 static int flash_fw(struct adapter *, void *, int);
48
49 int
50 t4_ioctl(struct adapter *sc, int cmd, void *data, int mode)
51 {
52 int rc = ENOTSUP;
53
54 switch (cmd) {
55 case T4_IOCTL_PCIGET32:
56 case T4_IOCTL_PCIPUT32:
57 rc = pci_rw(sc, data, mode, cmd == T4_IOCTL_PCIPUT32);
58 break;
59 case T4_IOCTL_GET32:
60 case T4_IOCTL_PUT32:
61 rc = reg_rw(sc, data, mode, cmd == T4_IOCTL_PUT32);
62 break;
63 case T4_IOCTL_REGDUMP:
64 rc = regdump(sc, data, mode);
65 break;
66 case T4_IOCTL_SGE_CONTEXT:
67 rc = get_sge_context(sc, data, mode);
73 rc = read_card_mem(sc, data, mode);
74 break;
75 case T4_IOCTL_GET_TID_TAB:
76 rc = read_tid_tab(sc, data, mode);
77 break;
78 case T4_IOCTL_GET_MBOX:
79 rc = read_mbox(sc, data, mode);
80 break;
81 case T4_IOCTL_GET_CIM_LA:
82 rc = read_cim_la(sc, data, mode);
83 break;
84 case T4_IOCTL_GET_CIM_QCFG:
85 rc = read_cim_qcfg(sc, data, mode);
86 break;
87 case T4_IOCTL_GET_CIM_IBQ:
88 rc = read_cim_ibq(sc, data, mode);
89 break;
90 case T4_IOCTL_GET_EDC:
91 rc = read_edc(sc, data, mode);
92 break;
93 case T4_IOCTL_LOAD_FW:
94 rc = flash_fw(sc, data, mode);
95 break;
96 default:
97 return (EINVAL);
98 }
99
100 return (rc);
101 }
102
103 static int
104 pci_rw(struct adapter *sc, void *data, int flags, int write)
105 {
106 struct t4_reg32_cmd r;
107
108 if (ddi_copyin(data, &r, sizeof (r), flags) < 0)
109 return (EFAULT);
110
111 /* address must be 32 bit aligned */
112 r.reg &= ~0x3;
113
114 if (write != 0)
115 t4_os_pci_write_cfg4(sc, r.reg, r.value);
1413 * to indicate that the buffer size was not enough. Return of
1414 * EFAULT indicates that the copyout was not successful.
1415 */
1416 rc = (rc == 0) ? ENOBUFS : EFAULT;
1417 goto done;
1418 }
1419
1420 buf = kmem_zalloc(dparams->size, KM_NOSLEEP);
1421 if (buf == NULL) {
1422 rc = ENOMEM;
1423 goto done;
1424 }
1425
1426 rc = -t4_memory_rw(sc, sc->params.drv_memwin, dparams->memtype,
1427 dparams->start, dparams->size, (void *)buf,
1428 T4_MEMORY_READ);
1429 if (rc != 0)
1430 goto done1;
1431
1432 /* Copyout device log buffer and then carrier buffer */
1433 if (ddi_copyout(buf, (void *)((uintptr_t)data + sizeof(dl)), dl.len,
1434 flags) < 0)
1435 rc = EFAULT;
1436
1437 if (ddi_copyout(&dl, data, sizeof(dl), flags) < 0)
1438 rc = EFAULT;
1439
1440 done1:
1441 kmem_free(buf, dparams->size);
1442
1443 done:
1444 return (rc);
1445 }
1446
1447 static int
1448 read_cim_qcfg(struct adapter *sc, void *data, int flags)
1449 {
1450 struct t4_cim_qcfg t4cimqcfg;
1451 int rc = 0;
1452 unsigned int ibq_rdaddr, obq_rdaddr, nq;
1453
1454 if (ddi_copyin(data, &t4cimqcfg, sizeof (t4cimqcfg), flags) < 0) {
1455 rc = EFAULT;
1456 goto _exit;
1457 }
1624 goto _exit;
1625 }
1626
1627 buf = p = kmem_zalloc(t4mbox.len, KM_NOSLEEP);
1628 if (buf == NULL) {
1629 rc = ENOMEM;
1630 goto _exit;
1631 }
1632
1633 for (i = 0; i < t4mbox.len; i += 8, p++)
1634 *p = t4_read_reg64(sc, data_reg + i);
1635
1636 if (ddi_copyout(buf, t4mbox.data, t4mbox.len, flags) < 0)
1637 rc = EFAULT;
1638
1639 kmem_free(buf, t4mbox.len);
1640
1641 _exit:
1642 return (rc);
1643 }
1644
1645 static int
1646 flash_fw(struct adapter *sc, void *data, int flags)
1647 {
1648 unsigned int mbox = M_PCIE_FW_MASTER + 1;
1649 struct t4_ldfw fw;
1650 u8 *ptr = NULL;
1651 int rc = 0;
1652
1653 if (ddi_copyin(data, &fw, sizeof(struct t4_ldfw), flags) < 0)
1654 return EFAULT;
1655
1656 if (!fw.len)
1657 return EINVAL;
1658
1659 ptr = (u8 *)kmem_zalloc(fw.len, KM_NOSLEEP);
1660 if (ptr == NULL)
1661 return ENOMEM;
1662
1663 if (ddi_copyin((void *)((uintptr_t)data + sizeof(fw)), ptr, fw.len,
1664 flags) < 0) {
1665 kmem_free(ptr, fw.len);
1666 return EFAULT;
1667 }
1668
1669 if (sc->flags & FULL_INIT_DONE)
1670 mbox = sc->mbox;
1671
1672 rc = -t4_fw_upgrade(sc, mbox, ptr, fw.len, true);
1673
1674 kmem_free(ptr, fw.len);
1675
1676 return (rc);
1677 }
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