1 /*
2 * This file and its contents are supplied under the terms of the
3 * Common Development and Distribution License ("CDDL"), version 1.0.
4 * You may only use this file in accordance with the terms of version
5 * 1.0 of the CDDL.
6 *
7 * A full copy of the text of the CDDL should have accompanied this
8 * source. A copy of the CDDL is also available via the Internet at
9 * http://www.illumos.org/license/CDDL.
10 */
11
12 /*
13 * This file is part of the Chelsio T4 support code.
14 *
15 * Copyright (C) 2011-2013 Chelsio Communications. All rights reserved.
16 *
17 * This program is distributed in the hope that it will be useful, but WITHOUT
18 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
19 * FITNESS FOR A PARTICULAR PURPOSE. See the LICENSE file included in this
20 * release for licensing terms and conditions.
21 */
22
23 #ifndef __CXGBE_ADAPTER_H
24 #define __CXGBE_ADAPTER_H
25
26 #include <sys/ddi.h>
27 #include <sys/mac_provider.h>
28 #include <sys/ethernet.h>
29 #include <sys/queue.h>
30
31 #include "offload.h"
32 #include "firmware/t4fw_interface.h"
33 #include "shared.h"
34
35 struct adapter;
36 typedef struct adapter adapter_t;
37
38 enum {
39 FW_IQ_QSIZE = 256,
40 FW_IQ_ESIZE = 64, /* At least 64 mandated by the firmware spec */
41
42 RX_IQ_QSIZE = 1024,
43 RX_IQ_ESIZE = 64, /* At least 64 so CPL_RX_PKT will fit */
44
45 EQ_ESIZE = 64, /* All egres queues use this entry size */
46
47 RX_FL_ESIZE = 64, /* 8 64bit addresses */
48
49 FL_BUF_SIZES = 4,
50
51 CTRL_EQ_QSIZE = 128,
52
53 TX_EQ_QSIZE = 1024,
54 TX_SGL_SEGS = 36,
55 TX_WR_FLITS = SGE_MAX_WR_LEN / 8
56 };
57
58 enum {
59 /* adapter flags */
60 FULL_INIT_DONE = (1 << 0),
61 FW_OK = (1 << 1),
62 INTR_FWD = (1 << 2),
63 INTR_ALLOCATED = (1 << 3),
64 MASTER_PF = (1 << 4),
65
66 CXGBE_BUSY = (1 << 9),
67
68 /* port flags */
69 DOOMED = (1 << 0),
70 PORT_INIT_DONE = (1 << 1),
71 };
72
73 enum {
74 /* Features */
75 CXGBE_HW_LSO = (1 << 0),
76 CXGBE_HW_CSUM = (1 << 1),
77 };
78
79 enum {
80 UDBS_SEG_SHIFT = 7, /* log2(UDBS_SEG_SIZE) */
81 UDBS_DB_OFFSET = 8, /* offset of the 4B doorbell in a segment */
82 UDBS_WR_OFFSET = 64, /* offset of the work request in a segment */
83 };
84
85 #define IS_DOOMED(pi) (pi->flags & DOOMED)
86 #define SET_DOOMED(pi) do { pi->flags |= DOOMED; } while (0)
87 #define IS_BUSY(sc) (sc->flags & CXGBE_BUSY)
88 #define SET_BUSY(sc) do { sc->flags |= CXGBE_BUSY; } while (0)
89 #define CLR_BUSY(sc) do { sc->flags &= ~CXGBE_BUSY; } while (0)
90
91 struct port_info {
92 PORT_INFO_HDR;
93
94 kmutex_t lock;
95 struct adapter *adapter;
96
97 #ifdef TCP_OFFLOAD_ENABLE
98 void *tdev;
99 #endif
100
101 unsigned int flags;
102
103 uint16_t viid;
104 int16_t xact_addr_filt; /* index of exact MAC address filter */
105 uint16_t rss_size; /* size of VI's RSS table slice */
106 uint16_t ntxq; /* # of tx queues */
107 uint16_t first_txq; /* index of first tx queue */
108 uint16_t nrxq; /* # of rx queues */
109 uint16_t first_rxq; /* index of first rx queue */
110 #ifdef TCP_OFFLOAD_ENABLE
111 uint16_t nofldtxq; /* # of offload tx queues */
112 uint16_t first_ofld_txq; /* index of first offload tx queue */
113 uint16_t nofldrxq; /* # of offload rx queues */
114 uint16_t first_ofld_rxq; /* index of first offload rx queue */
115 #endif
116 uint8_t lport; /* associated offload logical port */
117 int8_t mdio_addr;
118 uint8_t port_type;
119 uint8_t mod_type;
120 uint8_t port_id;
121 uint8_t tx_chan;
122 uint8_t rx_chan;
123 uint8_t instance; /* Associated adapter instance */
124 uint8_t child_inst; /* Associated child instance */
125 uint8_t tmr_idx;
126 int8_t pktc_idx;
127 struct link_config link_cfg;
128 struct port_stats stats;
129 uint32_t features;
130 uint8_t macaddr_cnt;
131 u8 rss_mode;
132 u16 viid_mirror;
133 kstat_t *ksp_config;
134 kstat_t *ksp_info;
135 };
136
137 struct fl_sdesc {
138 struct rxbuf *rxb;
139 };
140
141 struct tx_desc {
142 __be64 flit[8];
143 };
144
145 /* DMA maps used for tx */
146 struct tx_maps {
147 ddi_dma_handle_t *map;
148 uint32_t map_total; /* # of DMA maps */
149 uint32_t map_pidx; /* next map to be used */
150 uint32_t map_cidx; /* reclaimed up to this index */
151 uint32_t map_avail; /* # of available maps */
152 };
153
154 struct tx_sdesc {
155 mblk_t *m;
156 uint32_t txb_used; /* # of bytes of tx copy buffer used */
157 uint16_t hdls_used; /* # of dma handles used */
158 uint16_t desc_used; /* # of hardware descriptors used */
159 };
160
161 enum {
162 /* iq flags */
163 IQ_ALLOCATED = (1 << 0), /* firmware resources allocated */
164 IQ_INTR = (1 << 1), /* iq takes direct interrupt */
165 IQ_HAS_FL = (1 << 2), /* iq has fl */
166
167 /* iq state */
168 IQS_DISABLED = 0,
169 IQS_BUSY = 1,
170 IQS_IDLE = 2,
171 };
172
173 /*
174 * Ingress Queue: T4 is producer, driver is consumer.
175 */
176 struct sge_iq {
177 unsigned int flags;
178 ddi_dma_handle_t dhdl;
179 ddi_acc_handle_t ahdl;
180
181 volatile uint_t state;
182 __be64 *desc; /* KVA of descriptor ring */
183 uint64_t ba; /* bus address of descriptor ring */
184 const __be64 *cdesc; /* current descriptor */
185 struct adapter *adapter; /* associated adapter */
186 uint8_t gen; /* generation bit */
187 uint8_t intr_params; /* interrupt holdoff parameters */
188 int8_t intr_pktc_idx; /* packet count threshold index */
189 uint8_t intr_next; /* holdoff for next interrupt */
190 uint8_t esize; /* size (bytes) of each entry in the queue */
191 uint16_t qsize; /* size (# of entries) of the queue */
192 uint16_t cidx; /* consumer index */
193 uint16_t pending; /* # of descs processed since last doorbell */
194 uint16_t cntxt_id; /* SGE context id for the iq */
195 uint16_t abs_id; /* absolute SGE id for the iq */
196 kmutex_t lock; /* Rx access lock */
197 uint8_t polling;
198
199 STAILQ_ENTRY(sge_iq) link;
200 };
201
202 enum {
203 EQ_CTRL = 1,
204 EQ_ETH = 2,
205 #ifdef TCP_OFFLOAD_ENABLE
206 EQ_OFLD = 3,
207 #endif
208
209 /* eq flags */
210 EQ_TYPEMASK = 7, /* 3 lsbits hold the type */
211 EQ_ALLOCATED = (1 << 3), /* firmware resources allocated */
212 EQ_DOOMED = (1 << 4), /* about to be destroyed */
213 EQ_CRFLUSHED = (1 << 5), /* expecting an update from SGE */
214 EQ_STALLED = (1 << 6), /* out of hw descriptors or dmamaps */
215 EQ_MTX = (1 << 7), /* mutex has been initialized */
216 EQ_STARTED = (1 << 8), /* started */
217 };
218
219 /* Listed in order of preference. Update t4_sysctls too if you change these */
220 enum {DOORBELL_UDB=0x1 , DOORBELL_WCWR=0x2, DOORBELL_UDBWC=0x4, DOORBELL_KDB=0x8};
221
222 /*
223 * Egress Queue: driver is producer, T4 is consumer.
224 *
225 * Note: A free list is an egress queue (driver produces the buffers and T4
226 * consumes them) but it's special enough to have its own struct (see sge_fl).
227 */
228 struct sge_eq {
229 ddi_dma_handle_t desc_dhdl;
230 ddi_acc_handle_t desc_ahdl;
231 unsigned int flags;
232 kmutex_t lock;
233
234 struct tx_desc *desc; /* KVA of descriptor ring */
235 uint64_t ba; /* bus address of descriptor ring */
236 struct sge_qstat *spg; /* status page, for convenience */
237 int doorbells;
238 volatile uint32_t *udb; /* KVA of doorbell (lies within BAR2) */
239 u_int udb_qid; /* relative qid within the doorbell page */
240 uint16_t cap; /* max # of desc, for convenience */
241 uint16_t avail; /* available descriptors, for convenience */
242 uint16_t qsize; /* size (# of entries) of the queue */
243 uint16_t cidx; /* consumer idx (desc idx) */
244 uint16_t pidx; /* producer idx (desc idx) */
245 uint16_t pending; /* # of descriptors used since last doorbell */
246 uint16_t iqid; /* iq that gets egr_update for the eq */
247 uint8_t tx_chan; /* tx channel used by the eq */
248 uint32_t cntxt_id; /* SGE context id for the eq */
249 };
250
251 enum {
252 /* fl flags */
253 FL_MTX = (1 << 0), /* mutex has been initialized */
254 FL_STARVING = (1 << 1), /* on the list of starving fl's */
255 FL_DOOMED = (1 << 2), /* about to be destroyed */
256 };
257
258 #define FL_RUNNING_LOW(fl) (fl->cap - fl->needed <= fl->lowat)
259 #define FL_NOT_RUNNING_LOW(fl) (fl->cap - fl->needed >= 2 * fl->lowat)
260
261 struct sge_fl {
262 unsigned int flags;
263 kmutex_t lock;
264 ddi_dma_handle_t dhdl;
265 ddi_acc_handle_t ahdl;
266
267 __be64 *desc; /* KVA of descriptor ring, ptr to addresses */
268 uint64_t ba; /* bus address of descriptor ring */
269 struct fl_sdesc *sdesc; /* KVA of software descriptor ring */
270 uint32_t cap; /* max # of buffers, for convenience */
271 uint16_t qsize; /* size (# of entries) of the queue */
272 uint16_t cntxt_id; /* SGE context id for the freelist */
273 uint32_t cidx; /* consumer idx (buffer idx, NOT hw desc idx) */
274 uint32_t pidx; /* producer idx (buffer idx, NOT hw desc idx) */
275 uint32_t needed; /* # of buffers needed to fill up fl. */
276 uint32_t lowat; /* # of buffers <= this means fl needs help */
277 uint32_t pending; /* # of bufs allocated since last doorbell */
278 uint32_t offset; /* current packet within the larger buffer */
279 uint16_t copy_threshold; /* anything this size or less is copied up */
280
281 uint64_t copied_up; /* # of frames copied into mblk and handed up */
282 uint64_t passed_up; /* # of frames wrapped in mblk and handed up */
283
284 TAILQ_ENTRY(sge_fl) link; /* All starving freelists */
285 };
286
287 /* txq: SGE egress queue + miscellaneous items */
288 struct sge_txq {
289 struct sge_eq eq; /* MUST be first */
290
291 struct port_info *port; /* the port this txq belongs to */
292 struct tx_sdesc *sdesc; /* KVA of software descriptor ring */
293 mac_ring_handle_t ring_handle;
294
295 /* DMA handles used for tx */
296 ddi_dma_handle_t *tx_dhdl;
297 uint32_t tx_dhdl_total; /* Total # of handles */
298 uint32_t tx_dhdl_pidx; /* next handle to be used */
299 uint32_t tx_dhdl_cidx; /* reclaimed up to this index */
300 uint32_t tx_dhdl_avail; /* # of available handles */
301
302 /* Copy buffers for tx */
303 ddi_dma_handle_t txb_dhdl;
304 ddi_acc_handle_t txb_ahdl;
305 caddr_t txb_va; /* KVA of copy buffers area */
306 uint64_t txb_ba; /* bus address of copy buffers area */
307 uint32_t txb_size; /* total size */
308 uint32_t txb_next; /* offset of next useable area in the buffer */
309 uint32_t txb_avail; /* # of bytes available */
310 uint16_t copy_threshold; /* anything this size or less is copied up */
311
312 uint64_t txpkts; /* # of ethernet packets */
313 uint64_t txbytes; /* # of ethernet bytes */
314 kstat_t *ksp;
315
316 /* stats for common events first */
317
318 uint64_t txcsum; /* # of times hardware assisted with checksum */
319 uint64_t tso_wrs; /* # of IPv4 TSO work requests */
320 uint64_t imm_wrs; /* # of work requests with immediate data */
321 uint64_t sgl_wrs; /* # of work requests with direct SGL */
322 uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */
323 uint64_t txpkts_wrs; /* # of coalesced tx work requests */
324 uint64_t txpkts_pkts; /* # of frames in coalesced tx work requests */
325 uint64_t txb_used; /* # of tx copy buffers used (64 byte each) */
326 uint64_t hdl_used; /* # of DMA handles used */
327
328 /* stats for not-that-common events */
329
330 uint32_t txb_full; /* txb ran out of space */
331 uint32_t dma_hdl_failed; /* couldn't obtain DMA handle */
332 uint32_t dma_map_failed; /* couldn't obtain DMA mapping */
333 uint32_t qfull; /* out of hardware descriptors */
334 uint32_t qflush; /* # of SGE_EGR_UPDATE notifications for txq */
335 uint32_t pullup_early; /* # of pullups before starting frame's SGL */
336 uint32_t pullup_late; /* # of pullups while building frame's SGL */
337 uint32_t pullup_failed; /* # of failed pullups */
338 };
339
340 /* rxq: SGE ingress queue + SGE free list + miscellaneous items */
341 struct sge_rxq {
342 struct sge_iq iq; /* MUST be first */
343 struct sge_fl fl;
344
345 struct port_info *port; /* the port this rxq belongs to */
346 kstat_t *ksp;
347
348 mac_ring_handle_t ring_handle;
349 uint64_t ring_gen_num;
350
351 /* stats for common events first */
352
353 uint64_t rxcsum; /* # of times hardware assisted with checksum */
354 uint64_t rxpkts; /* # of ethernet packets */
355 uint64_t rxbytes; /* # of ethernet bytes */
356
357 /* stats for not-that-common events */
358
359 uint32_t nomem; /* mblk allocation during rx failed */
360 };
361
362 #ifdef TCP_OFFLOAD_ENABLE
363 /* ofld_rxq: SGE ingress queue + SGE free list + miscellaneous items */
364 struct sge_ofld_rxq {
365 struct sge_iq iq; /* MUST be first */
366 struct sge_fl fl;
367 };
368
369 /*
370 * wrq: SGE egress queue that is given prebuilt work requests. Both the control
371 * and offload tx queues are of this type.
372 */
373 struct sge_wrq {
374 struct sge_eq eq; /* MUST be first */
375
376 struct adapter *adapter;
377
378 /* List of WRs held up due to lack of tx descriptors */
379 struct mblk_pair wr_list;
380
381 /* stats for common events first */
382
383 uint64_t tx_wrs; /* # of tx work requests */
384
385 /* stats for not-that-common events */
386
387 uint32_t no_desc; /* out of hardware descriptors */
388 };
389 #endif
390
391 struct sge {
392 int fl_starve_threshold;
393 int s_qpp;
394
395 int nrxq; /* total rx queues (all ports and the rest) */
396 int ntxq; /* total tx queues (all ports and the rest) */
397 #ifdef TCP_OFFLOAD_ENABLE
398 int nofldrxq; /* total # of TOE rx queues */
399 int nofldtxq; /* total # of TOE tx queues */
400 #endif
401 int niq; /* total ingress queues */
402 int neq; /* total egress queues */
403 int stat_len; /* length of status page at ring end */
404 int pktshift; /* padding between CPL & packet data */
405 int fl_align; /* response queue message alignment */
406
407 struct sge_iq fwq; /* Firmware event queue */
408 #ifdef TCP_OFFLOAD_ENABLE
409 struct sge_wrq mgmtq; /* Management queue (Control queue) */
410 #endif
411 struct sge_txq *txq; /* NIC tx queues */
412 struct sge_rxq *rxq; /* NIC rx queues */
413 #ifdef TCP_OFFLOAD_ENABLE
414 struct sge_wrq *ctrlq; /* Control queues */
415 struct sge_wrq *ofld_txq; /* TOE tx queues */
416 struct sge_ofld_rxq *ofld_rxq; /* TOE rx queues */
417 #endif
418
419 uint16_t iq_start;
420 int eq_start;
421 struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */
422 struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */
423
424 /* Device access and DMA attributes for all the descriptor rings */
425 ddi_device_acc_attr_t acc_attr_desc;
426 ddi_dma_attr_t dma_attr_desc;
427
428 /* Device access and DMA attributes for tx buffers */
429 ddi_device_acc_attr_t acc_attr_tx;
430 ddi_dma_attr_t dma_attr_tx;
431
432 /* Device access and DMA attributes for rx buffers are in rxb_params */
433 kmem_cache_t *rxbuf_cache;
434 struct rxbuf_cache_params rxb_params;
435 };
436
437 struct driver_properties {
438 /* There is a driver.conf variable for each of these */
439 int max_ntxq_10g;
440 int max_nrxq_10g;
441 int max_ntxq_1g;
442 int max_nrxq_1g;
443 #ifdef TCP_OFFLOAD_ENABLE
444 int max_nofldtxq_10g;
445 int max_nofldrxq_10g;
446 int max_nofldtxq_1g;
447 int max_nofldrxq_1g;
448 #endif
449 int intr_types;
450 int tmr_idx_10g;
451 int pktc_idx_10g;
452 int tmr_idx_1g;
453 int pktc_idx_1g;
454 int qsize_txq;
455 int qsize_rxq;
456
457 int timer_val[SGE_NTIMERS];
458 int counter_val[SGE_NCOUNTERS];
459
460 int wc;
461
462 int multi_rings;
463 int t4_fw_install;
464 };
465
466 struct rss_header;
467 typedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *,
468 mblk_t *);
469 typedef int (*fw_msg_handler_t)(struct adapter *, const __be64 *);
470
471 struct adapter {
472 SLIST_ENTRY(adapter) link;
473 dev_info_t *dip;
474 dev_t dev;
475
476 unsigned int pf;
477 unsigned int mbox;
478
479 unsigned int vpd_busy;
480 unsigned int vpd_flag;
481
482 u32 t4_bar0;
483
484 uint_t open; /* character device is open */
485
486 /* PCI config space access handle */
487 ddi_acc_handle_t pci_regh;
488
489 /* MMIO register access handle */
490 ddi_acc_handle_t regh;
491 caddr_t regp;
492 /* BAR1 register access handle */
493 ddi_acc_handle_t reg1h;
494 caddr_t reg1p;
495
496 /* Interrupt information */
497 int intr_type;
498 int intr_count;
499 int intr_cap;
500 uint_t intr_pri;
501 ddi_intr_handle_t *intr_handle;
502
503 struct driver_properties props;
504 kstat_t *ksp;
505 kstat_t *ksp_stat;
506
507 struct sge sge;
508
509 struct port_info *port[MAX_NPORTS];
510 uint8_t chan_map[NCHAN];
511 uint32_t filter_mode;
512
513 struct l2t_data *l2t; /* L2 table */
514 struct tid_info tids;
515
516 int doorbells;
517 int registered_device_map;
518 int open_device_map;
519 int flags;
520
521 unsigned int cfcsum;
522 struct adapter_params params;
523 struct t4_virt_res vres;
524
525 #ifdef TCP_OFFLOAD_ENABLE
526 struct uld_softc tom;
527 struct tom_tunables tt;
528 #endif
529
530 #ifdef TCP_OFFLOAD_ENABLE
531 int offload_map;
532 #endif
533 uint16_t linkcaps;
534 uint16_t niccaps;
535 uint16_t toecaps;
536 uint16_t rdmacaps;
537 uint16_t iscsicaps;
538 uint16_t fcoecaps;
539
540 fw_msg_handler_t fw_msg_handler[5]; /* NUM_FW6_TYPES */
541 cpl_handler_t cpl_handler[0xef]; /* NUM_CPL_CMDS */
542
543 kmutex_t lock;
544 kcondvar_t cv;
545
546 /* Starving free lists */
547 kmutex_t sfl_lock; /* same cache-line as sc_lock? but that's ok */
548 TAILQ_HEAD(, sge_fl) sfl;
549 timeout_id_t sfl_timer;
550 };
551
552 enum {
553 NIC_H = 0,
554 TOM_H,
555 IW_H,
556 ISCSI_H
557 };
558
559 struct memwin {
560 uint32_t base;
561 uint32_t aperture;
562 };
563
564 #define ADAPTER_LOCK(sc) mutex_enter(&(sc)->lock)
565 #define ADAPTER_UNLOCK(sc) mutex_exit(&(sc)->lock)
566 #define ADAPTER_LOCK_ASSERT_OWNED(sc) ASSERT(mutex_owned(&(sc)->lock))
567 #define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) ASSERT(!mutex_owned(&(sc)->lock))
568
569 #define PORT_LOCK(pi) mutex_enter(&(pi)->lock)
570 #define PORT_UNLOCK(pi) mutex_exit(&(pi)->lock)
571 #define PORT_LOCK_ASSERT_OWNED(pi) ASSERT(mutex_owned(&(pi)->lock))
572 #define PORT_LOCK_ASSERT_NOTOWNED(pi) ASSERT(!mutex_owned(&(pi)->lock))
573
574 #define IQ_LOCK(iq) mutex_enter(&(iq)->lock)
575 #define IQ_UNLOCK(iq) mutex_exit(&(iq)->lock)
576 #define IQ_LOCK_ASSERT_OWNED(iq) ASSERT(mutex_owned(&(iq)->lock))
577 #define IQ_LOCK_ASSERT_NOTOWNED(iq) ASSERT(!mutex_owned(&(iq)->lock))
578
579 #define FL_LOCK(fl) mutex_enter(&(fl)->lock)
580 #define FL_UNLOCK(fl) mutex_exit(&(fl)->lock)
581 #define FL_LOCK_ASSERT_OWNED(fl) ASSERT(mutex_owned(&(fl)->lock))
582 #define FL_LOCK_ASSERT_NOTOWNED(fl) ASSERT(!mutex_owned(&(fl)->lock))
583
584 #define RXQ_LOCK(rxq) IQ_LOCK(&(rxq)->iq)
585 #define RXQ_UNLOCK(rxq) IQ_UNLOCK(&(rxq)->iq)
586 #define RXQ_LOCK_ASSERT_OWNED(rxq) IQ_LOCK_ASSERT_OWNED(&(rxq)->iq)
587 #define RXQ_LOCK_ASSERT_NOTOWNED(rxq) IQ_LOCK_ASSERT_NOTOWNED(&(rxq)->iq)
588
589 #define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl)
590 #define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl)
591 #define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl)
592 #define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl)
593
594 #define EQ_LOCK(eq) mutex_enter(&(eq)->lock)
595 #define EQ_UNLOCK(eq) mutex_exit(&(eq)->lock)
596 #define EQ_LOCK_ASSERT_OWNED(eq) ASSERT(mutex_owned(&(eq)->lock))
597 #define EQ_LOCK_ASSERT_NOTOWNED(eq) ASSERT(!mutex_owned(&(eq)->lock))
598
599 #define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq)
600 #define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq)
601 #define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq)
602 #define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq)
603
604 #define for_each_txq(pi, iter, txq) \
605 txq = &pi->adapter->sge.txq[pi->first_txq]; \
606 for (iter = 0; iter < pi->ntxq; ++iter, ++txq)
607 #define for_each_rxq(pi, iter, rxq) \
608 rxq = &pi->adapter->sge.rxq[pi->first_rxq]; \
609 for (iter = 0; iter < pi->nrxq; ++iter, ++rxq)
610 #define for_each_ofld_txq(pi, iter, ofld_txq) \
611 ofld_txq = &pi->adapter->sge.ofld_txq[pi->first_ofld_txq]; \
612 for (iter = 0; iter < pi->nofldtxq; ++iter, ++ofld_txq)
613 #define for_each_ofld_rxq(pi, iter, ofld_rxq) \
614 ofld_rxq = &pi->adapter->sge.ofld_rxq[pi->first_ofld_rxq]; \
615 for (iter = 0; iter < pi->nofldrxq; ++iter, ++ofld_rxq)
616
617 #define NFIQ(sc) ((sc)->intr_count > 1 ? (sc)->intr_count - 1 : 1)
618
619 /* One for errors, one for firmware events */
620 #define T4_EXTRA_INTR 2
621
622 /* Presently disabling locking around mbox access
623 * We may need to reenable it later
624 */
625 typedef int t4_os_lock_t;
626 static inline void t4_os_lock(t4_os_lock_t *lock)
627 {
628
629 }
630 static inline void t4_os_unlock(t4_os_lock_t *lock)
631 {
632
633 }
634
635 static inline uint32_t
636 t4_read_reg(struct adapter *sc, uint32_t reg)
637 {
638 /* LINTED: E_BAD_PTR_CAST_ALIGN */
639 return (ddi_get32(sc->regh, (uint32_t *)(sc->regp + reg)));
640 }
641
642 static inline void
643 t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val)
644 {
645 /* LINTED: E_BAD_PTR_CAST_ALIGN */
646 ddi_put32(sc->regh, (uint32_t *)(sc->regp + reg), val);
647 }
648
649 static inline void
650 t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val)
651 {
652 *val = pci_config_get8(sc->pci_regh, reg);
653 }
654
655 static inline void
656 t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val)
657 {
658 pci_config_put8(sc->pci_regh, reg, val);
659 }
660
661 static inline void
662 t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val)
663 {
664 *val = pci_config_get16(sc->pci_regh, reg);
665 }
666
667 static inline void
668 t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val)
669 {
670 pci_config_put16(sc->pci_regh, reg, val);
671 }
672
673 static inline void
674 t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val)
675 {
676 *val = pci_config_get32(sc->pci_regh, reg);
677 }
678
679 static inline void
680 t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val)
681 {
682 pci_config_put32(sc->pci_regh, reg, val);
683 }
684
685 static inline uint64_t
686 t4_read_reg64(struct adapter *sc, uint32_t reg)
687 {
688 /* LINTED: E_BAD_PTR_CAST_ALIGN */
689 return (ddi_get64(sc->regh, (uint64_t *)(sc->regp + reg)));
690 }
691
692 static inline void
693 t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val)
694 {
695 /* LINTED: E_BAD_PTR_CAST_ALIGN */
696 ddi_put64(sc->regh, (uint64_t *)(sc->regp + reg), val);
697 }
698
699 static inline struct port_info *
700 adap2pinfo(struct adapter *sc, int idx)
701 {
702 return (sc->port[idx]);
703 }
704
705 static inline void
706 t4_os_set_hw_addr(struct adapter *sc, int idx, uint8_t hw_addr[])
707 {
708 bcopy(hw_addr, sc->port[idx]->hw_addr, ETHERADDRL);
709 }
710
711 static inline bool
712 is_10G_port(const struct port_info *pi)
713 {
714 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G) != 0);
715 }
716
717 static inline struct sge_rxq *
718 iq_to_rxq(struct sge_iq *iq)
719 {
720 return (container_of(iq, struct sge_rxq, iq));
721 }
722
723 static inline bool
724 is_25G_port(const struct port_info *pi)
725 {
726 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_25G) != 0);
727 }
728
729 static inline bool
730 is_40G_port(const struct port_info *pi)
731 {
732 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G) != 0);
733 }
734
735 static inline bool
736 is_100G_port(const struct port_info *pi)
737 {
738 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_100G) != 0);
739 }
740
741 static inline bool
742 is_10XG_port(const struct port_info *pi)
743 {
744 return (is_10G_port(pi) || is_40G_port(pi) ||
745 is_25G_port(pi) || is_100G_port(pi));
746 }
747
748 static inline char *
749 print_port_speed(const struct port_info *pi)
750 {
751 if (!pi)
752 return "-";
753
754 if (is_100G_port(pi))
755 return "100G";
756 else if (is_40G_port(pi))
757 return "40G";
758 else if (is_25G_port(pi))
759 return "25G";
760 else if (is_10G_port(pi))
761 return "10G";
762 else
763 return "1G";
764 }
765
766 #ifdef TCP_OFFLOAD_ENABLE
767 int t4_wrq_tx_locked(struct adapter *sc, struct sge_wrq *wrq, mblk_t *m0);
768
769 static inline int
770 t4_wrq_tx(struct adapter *sc, struct sge_wrq *wrq, mblk_t *m)
771 {
772 int rc;
773
774 TXQ_LOCK(wrq);
775 rc = t4_wrq_tx_locked(sc, wrq, m);
776 TXQ_UNLOCK(wrq);
777 return (rc);
778 }
779 #endif
780
781 /**
782 * t4_os_pci_read_seeprom - read four bytes of SEEPROM/VPD contents
783 * @adapter: the adapter
784 * @addr: SEEPROM/VPD Address to read
785 * @valp: where to store the value read
786 *
787 * Read a 32-bit value from the given address in the SEEPROM/VPD. The address
788 * must be four-byte aligned. Returns 0 on success, a negative erro number
789 * on failure.
790 */
791 static inline int t4_os_pci_read_seeprom(adapter_t *adapter,
792 int addr, u32 *valp)
793 {
794 int t4_seeprom_read(struct adapter *adapter, u32 addr, u32 *data);
795 int ret;
796
797 ret = t4_seeprom_read(adapter, addr, valp);
798
799 return ret >= 0 ? 0 : ret;
800 }
801
802 /**
803 * t4_os_pci_write_seeprom - write four bytes of SEEPROM/VPD contents
804 * @adapter: the adapter
805 * @addr: SEEPROM/VPD Address to write
806 * @val: the value write
807 *
808 * Write a 32-bit value to the given address in the SEEPROM/VPD. The address
809 * must be four-byte aligned. Returns 0 on success, a negative erro number
810 * on failure.
811 */
812 static inline int t4_os_pci_write_seeprom(adapter_t *adapter,
813 int addr, u32 val)
814 {
815 int t4_seeprom_write(struct adapter *adapter, u32 addr, u32 data);
816 int ret;
817
818 ret = t4_seeprom_write(adapter, addr, val);
819
820 return ret >= 0 ? 0 : ret;
821 }
822
823 static inline int t4_os_pci_set_vpd_size(struct adapter *adapter, size_t len)
824 {
825 return 0;
826 }
827
828 static inline unsigned int t4_use_ldst(struct adapter *adap)
829 {
830 return (adap->flags & FW_OK);
831 }
832 #define t4_os_alloc(_size) kmem_alloc(_size, KM_SLEEP)
833
834 static inline void t4_db_full(struct adapter *adap) {}
835 static inline void t4_db_dropped(struct adapter *adap) {}
836
837 /* t4_nexus.c */
838 int t4_os_find_pci_capability(struct adapter *sc, int cap);
839 void t4_os_portmod_changed(const struct adapter *sc, int idx);
840 int adapter_full_init(struct adapter *sc);
841 int adapter_full_uninit(struct adapter *sc);
842 int port_full_init(struct port_info *pi);
843 int port_full_uninit(struct port_info *pi);
844 void enable_port_queues(struct port_info *pi);
845 void disable_port_queues(struct port_info *pi);
846 int t4_register_cpl_handler(struct adapter *sc, int opcode, cpl_handler_t h);
847 int t4_register_fw_msg_handler(struct adapter *, int, fw_msg_handler_t);
848 void t4_iterate(void (*func)(int, void *), void *arg);
849
850 /* t4_sge.c */
851 void t4_sge_init(struct adapter *sc);
852 int t4_setup_adapter_queues(struct adapter *sc);
853 int t4_teardown_adapter_queues(struct adapter *sc);
854 int t4_setup_port_queues(struct port_info *pi);
855 int t4_teardown_port_queues(struct port_info *pi);
856 uint_t t4_intr_all(caddr_t arg1, caddr_t arg2);
857 uint_t t4_intr(caddr_t arg1, caddr_t arg2);
858 uint_t t4_intr_err(caddr_t arg1, caddr_t arg2);
859 int t4_mgmt_tx(struct adapter *sc, mblk_t *m);
860 void memwin_info(struct adapter *, int, uint32_t *, uint32_t *);
861 uint32_t position_memwin(struct adapter *, int, uint32_t);
862
863 mblk_t *t4_eth_tx(void *, mblk_t *);
864 mblk_t *t4_mc_tx(void *arg, mblk_t *m);
865 mblk_t *t4_ring_rx(struct sge_rxq *rxq, int poll_bytes);
866 int t4_alloc_tx_maps(struct adapter *sc, struct tx_maps *txmaps, int count,
867 int flags);
868
869 /* t4_mac.c */
870 void t4_mc_init(struct port_info *pi);
871 void t4_mc_cb_init(struct port_info *);
872 void t4_os_link_changed(struct adapter *sc, int idx, int link_stat);
873 void t4_mac_rx(struct port_info *pi, struct sge_rxq *rxq, mblk_t *m);
874 void t4_mac_tx_update(struct port_info *pi, struct sge_txq *txq);
875 int t4_addmac(void *arg, const uint8_t *ucaddr);
876
877 /* t4_ioctl.c */
878 int t4_ioctl(struct adapter *sc, int cmd, void *data, int mode);
879
880 struct l2t_data *t4_init_l2t(struct adapter *sc);
881 #endif /* __CXGBE_ADAPTER_H */