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NEX-10267 BAD TRAP: type=d (#gp General protection) in qlt_msix_resp_handler()
Reviewed by: Evan Layton <evan.layton@nexenta.com>
Reviewed by: Rob Gittins <rob.gittins@nexenta.com>
NEX-5733 cleanup qlt/qlc
Reviewed by: Yuri Pankov <yuri.pankov@nexenta.com>
Reviewed by: Alek Pinchuk <alek.pinchuk@nexenta.com>
NEX-5717 import QLogic 16G FC drivers
Reviewed by: Steve Peng <steve.peng@nexenta.com>
Reviewed by: Josef 'Jeff' Sipek <josef.sipek@nexenta.com>
Reviewed by: Yuri Pankov <yuri.pankov@nexenta.com>
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--- old/usr/src/uts/common/io/comstar/port/qlt/qlt_regs.h
+++ new/usr/src/uts/common/io/comstar/port/qlt/qlt_regs.h
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
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13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21
22 22 /*
23 - * Copyright 2009 QLogic Corporation. All rights reserved.
23 + * Copyright 2009-2015 QLogic Corporation. All rights reserved.
24 24 * Use is subject to license terms.
25 25 */
26 26
27 27 /*
28 - * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved.
28 + * Copyright (c) 2008, 2015, Oracle and/or its affiliates. All rights reserved.
29 29 */
30 30
31 31 #ifndef _QLT_REGS_H
32 32 #define _QLT_REGS_H
33 33
34 34 #include <sys/stmf_defines.h>
35 35
36 36 #ifdef __cplusplus
37 37 extern "C" {
38 38 #endif
39 39
40 40 /*
41 41 * Register offsets
42 42 */
43 43 #define REG_FLASH_ADDR 0x00
44 44 #define REG_FLASH_DATA 0x04
45 45 #define REG_CTRL_STATUS 0x08
46 46 #define REG_INTR_CTRL 0x0C
47 47 #define REG_INTR_STATUS 0x10
48 +
48 49 #define REG_REQ_IN_PTR 0x1C
49 50 #define REG_REQ_OUT_PTR 0x20
50 51 #define REG_RESP_IN_PTR 0x24
51 52 #define REG_RESP_OUT_PTR 0x28
52 53 #define REG_PREQ_IN_PTR 0x2C
53 54 #define REG_PREQ_OUT_PTR 0x30
54 55 #define REG_ATIO_IN_PTR 0x3C
55 56 #define REG_ATIO_OUT_PTR 0x40
57 +
56 58 #define REG_RISC_STATUS 0x44
57 59 #define REG_HCCR 0x48
58 60 #define REG_GPIO_DATA 0x4C
59 61 #define REG_GPIO_ENABLE 0x50
60 62 #define REG_IOBUS_BASE_ADDR 0x54
61 63 #define REG_HOST_SEMA 0x58
62 64 #define REG_MBOX0 0x80
63 65
64 66 #define REG_MBOX(n) (REG_MBOX0 + (n << 1))
65 67
66 68 #define MAX_MBOXES 32
67 69
68 70 /*
69 71 * Ctrl Status register definitions
70 72 */
71 73 #define FLASH_ERROR BIT_18
72 74 #define DMA_ACTIVE_STATUS BIT_17
73 75 #define DMA_SHUTDOWN_CTRL BIT_16
74 76 #define FUNCTION_NUMBER BIT_15
77 +#define H2RISC_INTR BIT_6
78 +#define RISC_RESET BIT_5
75 79 /*
76 80 * #define 81XX_FUNCTION_NUMBER BIT_15 | BIT_14 | BIT_13 | BIT_12
77 81 */
78 82 #define PCI_X_BUS_MODE (BIT_8 | BIT_9 | BIT_10 | BIT_11)
79 83 #define PCI_X_XFER_CTRL (BIT_4 | BIT_5)
80 84 #define PCI_64_BIT_SLOT BIT_2
81 85 #define FLASH_WRITE_ENABLE BIT_1
82 86 #define CHIP_SOFT_RESET BIT_0
83 87
84 88 /*
85 89 * INTR_CTRL register
86 90 */
87 91 #define ENABLE_RISC_INTR BIT_3
88 92
89 93 /*
90 94 * INTR_STATUS register
91 95 */
92 96 #define RISC_PCI_INTR_REQUEST BIT_3
93 97
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94 98 /*
95 99 * RISC_STATUS register
96 100 */
97 101 #define FW_INTR_INFO_MASK (BIT_15 | BIT_14 | BIT_13 | BIT_12 | \
98 102 BIT_11 | BIT_10 | BIT_9 | BIT_8 | \
99 103 BIT_7 | BIT_6 | BIT_5 | BIT_4 | \
100 104 BIT_3 | BIT_2 | BIT_1)
101 105 #define FW_INTR_INFO_SHIFT 18
102 106
103 107 #define FW_INTR_INFO(status) (status & (FW_INTR_INFO_MASK << \
104 - FW_INTR_INFO_SHIFT))
108 + FW_INTR_INFO_SHIFT))
105 109 #define RISC_HOST_INTR_REQUEST BIT_15
106 110 #define RISC_PAUSED BIT_8
107 111
108 112 #define FW_INTR_STATUS_MASK (BIT_7 | BIT_6 | BIT_5 | BIT_4 | \
109 113 BIT_3 | BIT_2 | BIT_1 | BIT_0)
110 114
111 115 #define ROM_MBX_CMD_SUCCESSFUL 0x01
112 116 #define ROM_MBX_CMD_NOT_SUCCESSFUL 0x02
113 117 #define MBX_CMD_SUCCESSFUL 0x10
114 118 #define MBX_CMD_NOT_SUCCESSFUL 0x11
115 119 #define ASYNC_EVENT 0x12
116 120 #define RESP_Q_UPDATE 0x13
117 121 #define ATIO_Q_UPDATE 0x1c
118 122 #define RESP_ATIO_Q_UPDATE 0x1d
119 123
124 +
120 125 /*
126 + * Firmware state codes from get firmware state mailbox command
127 + */
128 +#define FSTATE_CONFIG_WAIT 0
129 +#define FSTATE_WAIT_AL_PA 1
130 +#define FSTATE_WAIT_LOGIN 2
131 +#define FSTATE_READY 3
132 +#define FSTATE_LOSS_SYNC 4
133 +#define FSTATE_ERROR 5
134 +#define FSTATE_NON_PART 7
135 +
136 +#define FSTATE_MPI_NIC_ERROR 0x10
137 +
138 +
139 +/*
121 140 * Mailbox command completion status.
122 141 */
123 142 #define QLT_MBX_CMD_SUCCESS 0x4000
124 143
144 +
125 145 /*
126 146 * HCCR commands
127 147 */
128 148 #define NOP 0x00
129 149 #define SET_RISC_RESET 0x01
130 150 #define CLEAR_RISC_RESET 0x02
131 151 #define SET_RISC_PAUSE 0x03
132 152 #define CLEAR_RISC_PAUSE 0x04
133 153 #define SET_HOST_TO_RISC_INTR 0x05
134 154 #define CLEAR_HOST_TO_RISC_INTR 0x06
135 155 #define CLEAR_RISC_TO_PCI_INTR 0x0A
136 156
137 157 #define HCCR_CMD_SHIFT 28
138 158 #define HCCR_CMD(cmd) ((uint32_t)cmd << HCCR_CMD_SHIFT)
139 159
140 -#define MBC_STOP_FIRMWARE 0x14
160 +/*
161 + * ISP8100/83xx Multi-Queue MBAR definitions
162 + */
163 +#define MQBAR_REQ_IN 0x0
164 +#define MQBAR_REQ_OUT 0x4
165 +#define MQBAR_RESP_IN 0x8
166 +#define MQBAR_RESP_OUT 0xc
141 167
168 +#define MQBAR_ATIO_IN 0x10
169 +#define MQBAR_ATIO_OUT 0x14
170 +
171 +/* 83xx uses 32 bytes per queue pair */
172 +#define MQBAR_REG_SIZE 0x20
173 +#define MQBAR_REG_OFFSET 4096
174 +
175 +#define MQ_MAX_QUEUES 8
176 +#define MQ_MAX_QUEUES_MASK (MQ_MAX_QUEUES - 1)
177 +
142 178 /*
143 179 * Flash/NVRAM definitions
144 180 */
145 181 #define FLASH_DATA_FLAG BIT_31
182 +
146 183 #define FLASH_CONF_ADDR 0x7FFD0000
184 +
147 185 #define FLASH_DATA_ADDR 0x7FF00000
186 +
187 +#define FLASH_2400_DATA_ADDR 0x7FF00000
188 +#define FLASH_2500_DATA_ADDR 0x7FF00000
189 +#define FLASH_2700_DATA_ADDR 0x7F800000
190 +#define FLASH_8100_DATA_ADDR 0x7F800000
191 +#define FLASH_8200_DATA_ADDR 0
192 +#define FLASH_8300_DATA_ADDR 0x7F800000
193 +
148 194 #define FLASH_DATA_ADDR_81XX 0x7F8D0000
195 + /* 0x7F80000 + 0xD0000 */
196 +#define FLASH_DATA_ADDR_83XX 0x7FA70000
197 + /* 0x7F80000 + 0x270000 */
198 +
149 199 #define NVRAM_CONF_ADDR 0x7FFF0000
150 200 #define NVRAM_DATA_ADDR 0x7FFE0000
151 201
202 +#define NVRAM_2400_FUNC0_ADDR 0x80
203 +#define NVRAM_2400_FUNC1_ADDR 0x180
204 +
205 +#define NVRAM_2500_FUNC0_ADDR 0x48080
206 +#define NVRAM_2500_FUNC1_ADDR 0x48180
207 +
208 +#define NVRAM_2700_FUNC0_ADDR 0x270080
209 +#define NVRAM_2700_FUNC1_ADDR 0x270180
210 +#define NVRAM_2700_FUNC2_ADDR 0x270280
211 +#define NVRAM_2700_FUNC3_ADDR 0x270380
212 +
213 +#define NVRAM_8100_FUNC0_ADDR 0xD0080
214 +#define NVRAM_8100_FUNC1_ADDR 0xD0180
215 +
216 +#define NVRAM_8300_FC_FUNC0_ADDR 0x270080
217 +#define NVRAM_8300_FC_FUNC1_ADDR 0x270180
218 +
219 +#define NVRAM_8300_FCOE_FUNC0_ADDR 0x274080
220 +#define NVRAM_8300_FCOE_FUNC1_ADDR 0x274180
221 +
152 222 #define NVRAM_FUNC0_ADDR (NVRAM_DATA_ADDR + 0x80)
153 223 #define NVRAM_FUNC1_ADDR (NVRAM_DATA_ADDR + 0x180)
154 224
155 225 #define QLT25_NVRAM_FUNC0_ADDR (FLASH_DATA_ADDR + 0x48080)
156 226 #define QLT25_NVRAM_FUNC1_ADDR (FLASH_DATA_ADDR + 0x48180)
157 227
228 +#define QLT27_NVRAM_FUNC0_ADDR (FLASH_2700_DATA_ADDR + 0x270080)
229 +#define QLT27_NVRAM_FUNC1_ADDR (FLASH_2700_DATA_ADDR + 0x270180)
230 +#define QLT27_NVRAM_FUNC2_ADDR (FLASH_2700_DATA_ADDR + 0x270280)
231 +#define QLT27_NVRAM_FUNC3_ADDR (FLASH_2700_DATA_ADDR + 0x270380)
232 +
158 233 #define QLT81_NVRAM_FUNC0_ADDR (FLASH_DATA_ADDR_81XX + 0x80)
159 234 #define QLT81_NVRAM_FUNC1_ADDR (FLASH_DATA_ADDR_81XX + 0x180)
160 235
236 +#define QLT83FC_NVRAM_FUNC0_ADDR (FLASH_DATA_ADDR_83XX + 0x80)
237 +#define QLT83FC_NVRAM_FUNC1_ADDR (FLASH_DATA_ADDR_83XX + 0x180)
238 +
239 +#define QLT83FCOE_NVRAM_FUNC0_ADDR (FLASH_DATA_ADDR_83XX + 0x4080)
240 +#define QLT83FCOE_NVRAM_FUNC1_ADDR (FLASH_DATA_ADDR_83XX + 0x4180)
241 +
242 +#define VPD_2400_FUNC0_ADDR 0
243 +#define VPD_2400_FUNC1_ADDR 0x100
244 +
245 +#define VPD_2500_FUNC0_ADDR 0x48000
246 +#define VPD_2500_FUNC1_ADDR 0x48100
247 +
248 +#define VPD_2700_FUNC0_ADDR 0x270000
249 +#define VPD_2700_FUNC1_ADDR 0x270100
250 +#define VPD_2700_FUNC2_ADDR 0x270200
251 +#define VPD_2700_FUNC3_ADDR 0x270300
252 +
253 +#define VPD_8100_FUNC0_ADDR 0xD0000
254 +#define VPD_8100_FUNC1_ADDR 0xD0400
255 +
256 +#define VPD_8021_FUNC0_ADDR 0xFA300
257 +#define VPD_8021_FUNC1_ADDR 0xFA300
258 +
259 +#define VPD_8300_FC_FUNC0_ADDR 0x270000
260 +#define VPD_8300_FC_FUNC1_ADDR 0x270100
261 +
262 +#define VPD_8300_FCOE_FUNC0_ADDR 0x274000
263 +#define VPD_8300_FCOE_FUNC1_ADDR 0x274100
264 +#define VPD_SIZE 0x80
265 +
266 +#define QLT24_VPD_FUNC0_ADDR (NVRAM_DATA_ADDR + 0x0)
267 +#define QLT24_VPD_FUNC1_ADDR (NVRAM_DATA_ADDR + 0x100)
268 +
269 +#define QLT25_VPD_FUNC0_ADDR (FLASH_DATA_ADDR + 0x48000)
270 +#define QLT25_VPD_FUNC1_ADDR (FLASH_DATA_ADDR + 0x48100)
271 +
272 +#define QLT27_VPD_FUNC0_ADDR (FLASH_2700_DATA_ADDR + 0x270000)
273 +#define QLT27_VPD_FUNC1_ADDR (FLASH_2700_DATA_ADDR + 0x270100)
274 +#define QLT27_VPD_FUNC2_ADDR (FLASH_2700_DATA_ADDR + 0x270200)
275 +#define QLT27_VPD_FUNC3_ADDR (FLASH_2700_DATA_ADDR + 0x270300)
276 +
277 +#define QLT81_VPD_FUNC0_ADDR (FLASH_8100_DATA_ADDR + 0xD0000)
278 +#define QLT81_VPD_FUNC1_ADDR (FLASH_8100_DATA_ADDR + 0xD0400)
279 +
280 +#define QLT83FC_VPD_FUNC0_ADDR (FLASH_8300_DATA_ADDR + 0x270000)
281 +#define QLT83FC_VPD_FUNC1_ADDR (FLASH_8300_DATA_ADDR + 0x270100)
282 +
283 +#define QLT83FCOE_VPD_FUNC0_ADDR (FLASH_8300_DATA_ADDR + 0x274000)
284 +#define QLT83FCOE_VPD_FUNC1_ADDR (FLASH_8300_DATA_ADDR + 0x274100)
285 +
286 +#define FLASH_2400_FIRMWARE_ADDR 0x20000
287 +#define FLASH_2400_FIRMWARE_SIZE 0x10000
288 +
289 +#define FLASH_2500_FIRMWARE_ADDR 0x20000
290 +#define FLASH_2500_FIRMWARE_SIZE 0x10000
291 +
292 +#define FLASH_8100_FIRMWARE_ADDR 0xA0000
293 +#define FLASH_8100_FIRMWARE_SIZE 0x20000
294 +
295 +#define FLASH_8300_BFE_ADDR 0x200000 /* BIOS/FCode/EFI */
296 +#define FLASH_8300_BFE_SIZE 0x80000
297 +
298 +#define FLASH_8300_FC_FIRMWARE_ADDR 0x240000
299 +#define FLASH_8300_FCOE_FIRMWARE_ADDR 0x220000
300 +#define FLASH_8300_FIRMWARE_SIZE 0x20000
301 +
302 +#define FLASH_8300_FIRMWARE_IMAGE_ADDR 0x40000
303 +#define FLASH_8300_FIRMWARE_IMAGE_SIZE 0x80000
304 +
305 +#define FLASH_8200_BOOTLOADER_ADDR 0x4000
306 +#define FLASH_8200_BOOTLOADER_SIZE 0x8000
307 +
308 +#define FLASH_8300_BOOTLOADER_ADDR 0x4000
309 +#define FLASH_8300_BOOTLOADER_SIZE 0x8000
310 +
311 +#define FLASH_2400_DESCRIPTOR_TABLE 0
312 +#define FLASH_2500_DESCRIPTOR_TABLE 0x50000
313 +#define FLASH_8100_DESCRIPTOR_TABLE 0xD8000
314 +#define FLASH_8200_DESCRIPTOR_TABLE 0
315 +#define FLASH_8300_DESCRIPTOR_TABLE 0xFC000
316 +
317 +#define FLASH_2400_LAYOUT_TABLE 0x11400
318 +#define FLASH_2500_LAYOUT_TABLE 0x50400
319 +#define FLASH_8100_LAYOUT_TABLE 0xD8400
320 +#define FLASH_8200_LAYOUT_TABLE 0xFC400
321 +#define FLASH_8300_LAYOUT_TABLE 0xFC400
322 +
323 +#define FLASH_2400_BOOT_CODE_ADDR 0
324 +#define FLASH_2500_BOOT_CODE_ADDR 0
325 +#define FLASH_2700_BOOT_CODE_ADDR 0x200000
326 +#define FLASH_8100_BOOT_CODE_ADDR 0x80000
327 +#define FLASH_8300_BOOT_CODE_ADDR 0x200000
328 +
329 +#define VPD_TAG_END 0x78
330 +#define VPD_TAG_CHKSUM "RV"
331 +#define VPD_TAG_SN "SN"
332 +#define VPD_TAG_PN "PN"
333 +#define VPD_TAG_PRODID "\x82"
334 +#define VPD_TAG_LRT 0x90
335 +#define VPD_TAG_LRTC 0x91
336 +
337 +typedef struct qlt_rom_header {
338 + uint8_t signature[2];
339 + uint8_t reserved[0x16];
340 + uint8_t dataoffset[2];
341 + uint8_t pad[6];
342 +} qlt_rom_header_t;
343 +
344 +typedef struct qlt_rom_data {
345 + uint8_t signature[4];
346 + uint8_t vid[2];
347 + uint8_t did[2];
348 + uint8_t reserved0[2];
349 + uint8_t pcidatalen[2];
350 + uint8_t pcidatarev;
351 + uint8_t classcode[3];
352 + uint8_t imagelength[2]; /* In sectors */
353 + uint8_t revisionlevel[2];
354 + uint8_t codetype;
355 + uint8_t indicator;
356 + uint8_t reserved1[2];
357 + uint8_t pad[8];
358 +} qlt_rom_data_t;
359 +
360 +typedef struct qlt_rom_image {
361 + qlt_rom_header_t header;
362 + qlt_rom_data_t data;
363 + uint32_t cksum;
364 +} qlt_rom_image_t;
365 +
366 +#define PCI_HEADER0 0x55
367 +#define PCI_HEADER1 0xAA
368 +#define PCI_DATASIG "PCIR"
369 +#define PCI_SECTOR_SIZE 0x200
370 +#define PCI_CODE_X86PC 0
371 +#define PCI_CODE_FCODE 1
372 +#define PCI_CODE_HPPA 2
373 +#define PCI_CODE_EFI 3
374 +#define PCI_CODE_FW 0xfe
375 +#define PCI_IND_LAST_IMAGE 0x80
376 +#define SBUS_CODE_FCODE 0xf1
377 +
378 +/*
379 + * Firmware Dump structure definition
380 + */
381 +#define QL_2200_FW_DUMP_SIZE 0x68000 /* bytes */
382 +#define QL_2300_FW_DUMP_SIZE 0xE2000 /* bytes */
383 +#define QL_6322_FW_DUMP_SIZE 0xE2000 /* bytes */
384 +#define QL_24XX_FW_DUMP_SIZE 0x0330000 /* bytes */
385 +#define QL_25XX_FW_DUMP_SIZE 0x0330000 /* bytes */
386 +
387 +#define QL_24XX_VPD_SIZE 0x200 /* bytes */
388 +#define QL_24XX_SFP_SIZE 0x200 /* bytes */
389 +
390 +#define LNF_NVRAM_DATA BIT_0
391 +#define LNF_VPD_DATA BIT_1
392 +#define LNF_BFE_DATA BIT_2
393 +
161 394 typedef struct qlt_nvram {
162 395 /* NVRAM header. */
163 396 uint8_t id[4];
164 397 uint8_t nvram_version[2];
165 398 uint8_t reserved_0[2];
166 399
167 400 /* Firmware Initialization Control Block. */
168 401 uint8_t version[2];
169 402 uint8_t reserved_1[2];
170 403 uint8_t max_frame_length[2];
171 404 uint8_t execution_throttle[2];
172 405 uint8_t exchange_count[2];
173 406 uint8_t hard_address[2];
174 407 uint8_t port_name[8];
175 408 uint8_t node_name[8];
176 409 uint8_t login_retry_count[2];
177 410 uint8_t link_down_on_nos[2];
178 411 uint8_t interrupt_delay_timer[2];
179 412 uint8_t login_timeout[2];
180 413
181 414 /*
182 415 * BIT 0 = Hard Assigned Loop ID
183 416 * BIT 1 = Enable Fairness
184 417 * BIT 2 = Enable Full-Duplex
185 418 * BIT 3 = Reserved
186 419 * BIT 4 = Target Mode Enable
187 420 * BIT 5 = Initiator Mode Disable
188 421 * BIT 6 = Reserved
189 422 * BIT 7 = Reserved
190 423 *
191 424 * BIT 8 = Reserved
192 425 * BIT 9 = Disable Initial LIP
193 426 * BIT 10 = Descending Loop ID Search
194 427 * BIT 11 = Previous Assigned Loop ID
195 428 * BIT 12 = Reserved
196 429 * BIT 13 = Full Login after LIP
197 430 * BIT 14 = Node Name Option
198 431 * BIT 15-31 = Reserved
199 432 */
200 433 uint8_t firmware_options_1[4];
201 434
202 435 /*
203 436 * BIT 0 = Operation Mode bit 0
204 437 * BIT 1 = Operation Mode bit 1
205 438 * BIT 2 = Operation Mode bit 2
206 439 * BIT 3 = Operation Mode bit 3
207 440 * BIT 4 = Connection Options bit 0
208 441 * BIT 5 = Connection Options bit 1
209 442 * BIT 6 = Connection Options bit 2
210 443 * BIT 7 = Enable Non part on LIHA failure
211 444 *
212 445 * BIT 8 = Enable Class 2
213 446 * BIT 9 = Enable ACK0
214 447 * BIT 10 = Reserved
215 448 * BIT 11 = Enable FC-SP Security
216 449 * BIT 12 = FC Tape Enable
217 450 * BIT 13-31 = Reserved
218 451 */
219 452 uint8_t firmware_options_2[4];
220 453
221 454 /*
222 455 * BIT 0 = Reserved
223 456 * BIT 1 = Soft ID only
224 457 * BIT 2 = Reserved
225 458 * BIT 3 = Reserved
226 459 * BIT 4 = FCP RSP Payload bit 0
227 460 * BIT 5 = FCP RSP Payload bit 1
228 461 * BIT 6 = Enable Rec Out-of-Order data frame handling
229 462 * BIT 7 = Disable Automatic PLOGI on Local Loop
230 463 *
231 464 * BIT 8 = Reserved
232 465 * BIT 9 = Enable Out-of-Order FCP_XFER_RDY relative
233 466 * offset handling
234 467 * BIT 10 = Reserved
235 468 * BIT 11 = Reserved
236 469 * BIT 12 = Reserved
237 470 * BIT 13 = Data Rate bit 0
238 471 * BIT 14 = Data Rate bit 1
239 472 * BIT 15 = Data Rate bit 2
240 473 * BIT 16 = 75-ohm Termination Select
241 474 * BIT 17-31 = Reserved
242 475 */
243 476 uint8_t firmware_options_3[4];
244 477
245 478 /*
246 479 * Serial Link Control (offset 56)
247 480 * BIT 0 = control enable
248 481 * BIT 1-15 = Reserved
249 482 */
250 483 uint8_t swing_opt[2];
251 484
252 485 /*
253 486 * Serial Link Control 1G (offset 58)
254 487 * BIT 0-7 = Reserved
255 488 *
256 489 * BIT 8-10 = output swing
257 490 * BIT 11-13 = output emphasis
258 491 * BIT 14-15 = Reserved
259 492 */
260 493 uint8_t swing_1g[2];
261 494
262 495 /*
263 496 * Serial Link Control 2G (offset 60)
264 497 * BIT 0-7 = Reserved
265 498 *
266 499 * BIT 8-10 = output swing
267 500 * BIT 11-13 = output emphasis
268 501 * BIT 14-15 = Reserved
269 502 */
270 503 uint8_t swing_2g[2];
271 504
272 505 /*
273 506 * Serial Link Control 4G (offset 62)
274 507 * BIT 0-7 = Reserved
275 508 *
276 509 * BIT 8-10 = output swing
277 510 * BIT 11-13 = output emphasis
278 511 * BIT 14-15 = Reserved
279 512 */
280 513 uint8_t swing_4g[2];
281 514
282 515 /* Offset 64. */
283 516 uint8_t reserved_2[32];
284 517
285 518 /* Offset 96. */
286 519 uint8_t reserved_3[32];
287 520
288 521 /* PCIe table entries. */
289 522 uint8_t reserved_4[32];
290 523
291 524 /* Offset 160. */
292 525 uint8_t reserved_5[32];
293 526
294 527 /* Offset 192. */
295 528 uint8_t reserved_6[32];
296 529
297 530 /* Offset 224. */
298 531 uint8_t reserved_7[32];
299 532
300 533 /*
301 534 * BIT 0 = Enable spinup delay
302 535 * BIT 1 = Disable BIOS
303 536 * BIT 2 = Enable Memory Map BIOS
304 537 * BIT 3 = Enable Selectable Boot
305 538 * BIT 4 = Disable RISC code load
306 539 * BIT 5 = Disable serdes
307 540 * BIT 6 = Enable opt boot mode
308 541 * BIT 7 = Enable int mode BIOS
309 542 *
310 543 * BIT 8 =
311 544 * BIT 9 =
312 545 * BIT 10 = Enable lip full login
313 546 * BIT 11 = Enable target reset
314 547 * BIT 12 =
315 548 * BIT 13 = Default Node Name Option
316 549 * BIT 14 = Default valid
317 550 * BIT 15 = Enable alternate WWN
318 551 *
319 552 * BIT 16-31 =
320 553 */
321 554 uint8_t host_p[4];
322 555
323 556 uint8_t alternate_port_name[8];
324 557 uint8_t alternate_node_name[8];
325 558
326 559 uint8_t boot_port_name[8];
327 560 uint8_t boot_lun_number[2];
328 561 uint8_t reserved_8[2];
329 562
330 563 uint8_t alt1_boot_port_name[8];
331 564 uint8_t alt1_boot_lun_number[2];
332 565 uint8_t reserved_9[2];
333 566
334 567 uint8_t alt2_boot_port_name[8];
335 568 uint8_t alt2_boot_lun_number[2];
336 569 uint8_t reserved_10[2];
337 570
338 571 uint8_t alt3_boot_port_name[8];
339 572 uint8_t alt3_boot_lun_number[2];
340 573 uint8_t reserved_11[2];
341 574
342 575 /*
343 576 * BIT 0 = Selective Login
344 577 * BIT 1 = Alt-Boot Enable
345 578 * BIT 2 = Reserved
346 579 * BIT 3 = Enable Boot Order List
347 580 * BIT 4 = Reserved
348 581 * BIT 5 = Enable Selective LUN
349 582 * BIT 6 = Reserved
350 583 * BIT 7-31 =
351 584 */
352 585 uint8_t efi_parameters[4];
353 586
354 587 uint8_t reset_delay;
355 588 uint8_t reserved_12;
356 589 uint8_t reserved_13[2];
357 590
358 591 uint8_t boot_id_number[2];
359 592 uint8_t reserved_14[2];
360 593
361 594 uint8_t max_luns_per_target[2];
362 595 uint8_t reserved_15[2];
363 596
364 597 uint8_t port_down_retry_count[2];
365 598 uint8_t link_down_timeout[2];
366 599
367 600 /*
368 601 * FCode parameters word (offset 344)
369 602 *
370 603 * BIT 0 = Enable BIOS pathname
371 604 * BIT 1 = fcode qlc
372 605 * BIT 2 = fcode host
373 606 * BIT 3-7 =
374 607 */
375 608 uint8_t fcode_p0;
376 609 uint8_t reserved_16[7];
377 610
378 611 /* Offset 352. */
379 612 uint8_t prev_drv_ver_major;
380 613 uint8_t prev_drv_ver_submajob;
381 614 uint8_t prev_drv_ver_minor;
382 615 uint8_t prev_drv_ver_subminor;
383 616
384 617 uint8_t prev_bios_ver_major[2];
385 618 uint8_t prev_bios_ver_minor[2];
386 619
387 620 uint8_t prev_efi_ver_major[2];
388 621 uint8_t prev_efi_ver_minor[2];
389 622
390 623 uint8_t prev_fw_ver_major[2];
391 624 uint8_t prev_fw_ver_minor;
392 625 uint8_t prev_fw_ver_subminor;
393 626
394 627 uint8_t reserved_17[16];
395 628
396 629 /* Offset 384. */
397 630 uint8_t def_port_name[8];
398 631 uint8_t def_node_name[8];
399 632
400 633 uint8_t reserved_18[16];
401 634
402 635 /* Offset 416. */
403 636 uint8_t reserved_19[32];
404 637
405 638 /* Offset 448. */
406 639 uint8_t reserved_20[28];
407 640
408 641 /* Offset 476. */
409 642 uint8_t fw_table_offset[2];
410 643 uint8_t fw_table_sig[2];
411 644
412 645 /* Offset 480. */
413 646 uint8_t model_name[8];
414 647
415 648 /* Offset 488. */
416 649 uint8_t power_table[16];
417 650
418 651 uint8_t subsystem_vendor_id[2];
419 652 uint8_t subsystem_device_id[2];
420 653
421 654 uint8_t checksum[4];
422 655 } qlt_nvram_t;
423 656
424 657 /* ISP81xx Extended Initialisation Control Block */
425 658 typedef struct qlt_ext_icb_81xx {
426 659
427 660 uint8_t version[2];
428 661 uint8_t fcf_vlan_match;
429 662 uint8_t reserved_6[3];
430 663 uint8_t fcf_vlan_id[2];
431 664 uint8_t fcf_fabric_name[8];
432 665 uint8_t reserved_7[14];
433 666 uint8_t spma_proposed_mac_address[6];
434 667 uint8_t reserved_8[28];
435 668
436 669 } qlt_ext_icb_81xx_t;
437 670
438 671 typedef struct qlt_nvram_81xx {
439 672 /* NVRAM header. */
440 673 uint8_t id[4];
441 674 uint8_t nvram_version[2];
442 675 uint8_t reserved_0[2];
443 676
444 677 /* Firmware Initialization Control Block. */
445 678 uint8_t version[2];
446 679 uint8_t reserved_1[2];
447 680 uint8_t max_frame_length[2];
448 681 uint8_t execution_throttle[2];
449 682 uint8_t exchange_count[2];
450 683 uint8_t reserved_2[2];
451 684 uint8_t port_name[8];
452 685 uint8_t node_name[8];
453 686 uint8_t login_retry_count[2];
454 687 uint8_t reserved_3[2];
455 688 uint8_t interrupt_delay_timer[2];
456 689 uint8_t login_timeout[2];
457 690
458 691 /*
459 692 * BIT 0 = Hard Assigned Loop ID
460 693 * BIT 1 = Enable Fairness
461 694 * BIT 2 = Enable Full-Duplex
462 695 * BIT 3 = Reserved
463 696 * BIT 4 = Target Mode Enable
464 697 * BIT 5 = Initiator Mode Disable
465 698 * BIT 6 = Reserved
466 699 * BIT 7 = Reserved
467 700 *
468 701 * BIT 8 = Reserved
469 702 * BIT 9 = Reserved
470 703 * BIT 10 = Reserved
471 704 * BIT 11 = Reserved
472 705 * BIT 12 = Reserved
473 706 * BIT 13 = Reserved
474 707 * BIT 14 = Node Name Option
475 708 * BIT 15-31 = Reserved
476 709 */
477 710 uint8_t firmware_options_1[4];
478 711
479 712 /*
480 713 * BIT 0 = Operation Mode bit 0
481 714 * BIT 1 = Operation Mode bit 1
482 715 * BIT 2 = Operation Mode bit 2
483 716 * BIT 3 = Operation Mode bit 3
484 717 * BIT 4 = Reserved
485 718 * BIT 5 = Reserved
486 719 * BIT 6 = Reserved
487 720 * BIT 7 = Reserved
488 721 *
489 722 * BIT 8 = Enable Class 2
490 723 * BIT 9 = Enable ACK0
491 724 * BIT 10 = Reserved
492 725 * BIT 11 = Enable FC-SP Security
493 726 * BIT 12 = FC Tape Enable
494 727 * BIT 13 = Reserved
495 728 * BIT 14 = Target PRLI Control
496 729 * BIT 15-31 = Reserved
497 730 */
498 731 uint8_t firmware_options_2[4];
499 732
500 733 /*
501 734 * BIT 0 = Reserved
502 735 * BIT 1 = Soft ID only
503 736 * BIT 2 = Reserved
504 737 * BIT 3 = Reserved
505 738 * BIT 4 = FCP RSP Payload bit 0
506 739 * BIT 5 = FCP RSP Payload bit 1
507 740 * BIT 6 = Enable Rec Out-of-Order data frame handling
508 741 * BIT 7 = Reserved
509 742 *
510 743 * BIT 8 = Reserved
511 744 * BIT 9 = Enable Out-of-Order FCP_XFER_RDY relative
512 745 * offset handling
513 746 * BIT 10 = Reserved
514 747 * BIT 11 = Reserved
515 748 * BIT 12 = Reserved
516 749 * BIT 13 = Reserved
517 750 * BIT 14 = Reserved
518 751 * BIT 15 = Reserved
519 752 * BIT 16 = Reserved
520 753 * BIT 17 = Enable Multiple FCFs
521 754 * BIT 18-20 = MAC Addressing Mode
522 755 * BIT 21-25 = Ethernet Data Rate
523 756 * BIT 26 = Enable Ethernet Header Receive ATIO_Q
524 757 * BIT 27 = Enable Ethernet Header Receive RSP_Q
525 758 * BIT 28-29 = SPMA Selection
526 759 * BIT 30-31 = Reserved
527 760 */
528 761 uint8_t firmware_options_3[4];
529 762
530 763 /* Offset 56 (38h). */
531 764 uint8_t reserved_4[8];
532 765
533 766 /* Offset 64 (40h). */
534 767 uint8_t enode_mac[6];
535 768
536 769 /* Offset 70 (46h). */
537 770 uint8_t reserved_5[26];
538 771
539 772 /* Offset 96 (60h). */
540 773 uint8_t oem_specific;
541 774 uint8_t reserved_6[15];
542 775
543 776 /* Offset 112 (70h). */
544 777 uint8_t reserved_7[16];
545 778
546 779 /* Offset 128 (80h). */
547 780 qlt_ext_icb_81xx_t ext_blk;
548 781
549 782 /* Offset 192. */
550 783 uint8_t reserved_8[32];
551 784
552 785 /* Offset 224. */
553 786 uint8_t reserved_9[32];
554 787
555 788 uint8_t host_p[4];
556 789
557 790 uint8_t alternate_port_name[8];
558 791 uint8_t alternate_name_name[8];
559 792
560 793 uint8_t boot_port_name[8];
561 794 uint8_t boot_lun_number[2];
562 795 uint8_t reserved_10[2];
563 796
564 797 uint8_t alt1_boot_port_name[8];
565 798 uint8_t alt1_boot_lun_number[2];
566 799 uint8_t reserved_11[2];
567 800
568 801 uint8_t alt2_boot_port_name[8];
569 802 uint8_t alt2_boot_lun_number[2];
570 803 uint8_t reserved_12[2];
571 804
572 805 uint8_t alt3_boot_port_name[8];
573 806 uint8_t alt3_boot_lun_number[2];
574 807 uint8_t reserved_13[2];
575 808
576 809 /*
577 810 * BIT 0 = Selective Login
578 811 * BIT 1 = Alt-Boot Enable
579 812 * BIT 2 = Reserved
580 813 * BIT 3 = Enable Boot Order List
581 814 * BIT 4 = Reserved
582 815 * BIT 5 = Enable Selective LUN
583 816 * BIT 6 = Reserved
584 817 * BIT 7-31 =
585 818 */
586 819 uint8_t efi_parameters[4];
587 820
588 821 uint8_t reset_delay;
589 822 uint8_t reserved_14;
590 823 uint8_t reserved_15[2];
591 824
592 825 uint8_t boot_id_number[2];
593 826 uint8_t reserved_16[2];
594 827
595 828 uint8_t max_luns_per_target[2];
596 829 uint8_t reserved_17[2];
597 830
598 831 uint8_t port_down_retry_count[2];
599 832 uint8_t link_down_timeout[2];
600 833
601 834 /*
602 835 * FCode parameters word (offset 344)
603 836 *
604 837 * BIT 0 = Enable BIOS pathname
605 838 * BIT 1 = fcode qlc
606 839 * BIT 2 = fcode host
607 840 * BIT 3-7 =
608 841 */
609 842 uint8_t fcode_parameter[2];
610 843 uint8_t reserved_18[6];
611 844
612 845 /* Offset 352. */
613 846 uint8_t reserved_19[4];
614 847 uint8_t reserved_20[10];
615 848 uint8_t reserved_21[2];
616 849 uint8_t reserved_22[16];
617 850
618 851 /* Offset 384. */
619 852 uint8_t reserved_23[16];
620 853 uint8_t reserved_24[16];
621 854
622 855 /* Offset 416. */
623 856 uint8_t reserved_25[64];
624 857
625 858 /* Offset 480. */
626 859 uint8_t model_name[16];
627 860
628 861 /* Offset 496. */
629 862 uint8_t feature_mask_l[2];
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630 863 uint8_t feature_mask_h[2];
631 864 uint8_t reserved_26[4];
632 865
633 866 uint8_t subsystem_vendor_id[2];
634 867 uint8_t subsystem_device_id[2];
635 868
636 869 uint8_t checksum[4];
637 870
638 871 } qlt_nvram_81xx_t;
639 872
873 +/*
874 + * firmware dump Entry Types
875 + */
876 +#define DT_NOP 0
877 +#define DT_THDR 99
878 +#define DT_TEND 255
879 +#define DT_RIOB1 256
880 +#define DT_WIOB1 257
881 +#define DT_RIOB2 258
882 +#define DT_WIOB2 259
883 +#define DT_RPCI 260
884 +#define DT_WPCI 261
885 +#define DT_RRAM 262
886 +#define DT_GQUE 263
887 +#define DT_GFCE 264
888 +#define DT_PRISC 265
889 +#define DT_RRISC 266
890 +#define DT_DINT 267
891 +#define DT_GHBD 268
892 +#define DT_SCRA 269
893 +#define DT_RRREG 270
894 +#define DT_WRREG 271
895 +#define DT_RRRAM 272
896 +#define DT_RPCIC 273
897 +#define DT_GQUES 274
898 +#define DT_WDMP 275
899 +
900 +/*
901 + * firmware dump Template Header (Entry Type 99)
902 + */
903 +typedef struct qlt_dt_hdr {
904 + uint32_t type;
905 + uint32_t first_entry_offset;
906 + uint32_t size_of_template;
907 + uint32_t rsv;
908 + uint32_t num_of_entries;
909 + uint32_t version;
910 + uint32_t driver_timestamp;
911 + uint32_t checksum;
912 + uint32_t rsv_1;
913 + uint32_t driver_info[3];
914 + uint32_t saved_state_area[16];
915 + uint32_t rsv_2[8];
916 + uint32_t ver_attr[5];
917 +} qlt_dt_hdr_t;
918 +
919 +/*
920 + * firmware dump Common Entry Header
921 + */
922 +typedef struct qlt_dt_entry_hdr {
923 + uint32_t type;
924 + uint32_t size;
925 + uint32_t rsv;
926 +#ifdef _BIG_ENDIAN
927 + uint8_t driver_flags;
928 + uint8_t rsv_2;
929 + uint8_t rsv_1;
930 + uint8_t capture_flags;
931 +#else
932 + uint8_t capture_flags;
933 + uint8_t rsv_1;
934 + uint8_t rsv_2;
935 + uint8_t driver_flags;
936 +#endif
937 +} qlt_dt_entry_hdr_t;
938 +
939 +/*
940 + * Capture Flags
941 + */
942 +#define PF_ONLY_FLAG BIT_0 /* Physical Function Only */
943 +#define PF_VF_FLAG BIT_1 /* Physical and Virtual Functions */
944 +
945 +/*
946 + * Driver Flags
947 + */
948 +#define SKIPPED_FLAG BIT_7 /* driver skipped this entry */
949 +
950 +/*
951 + * firmware dump Entry Including Header
952 + */
953 +typedef struct qlt_dt_entry {
954 + qlt_dt_entry_hdr_t h;
955 + uint32_t data[1];
956 +} qlt_dt_entry_t;
957 +
958 +/*
959 + * firmware dump Template image
960 + */
961 +typedef struct qlt_dmp_template {
962 + uint32_t rsv[2];
963 + uint32_t len;
964 + uint32_t major_ver;
965 + uint32_t minor_ver;
966 + uint32_t subminor_ver;
967 + uint32_t attribute;
968 + qlt_dt_hdr_t hdr;
969 + qlt_dt_entry_t entries[1];
970 +} qlt_dmp_template_t;
971 +
972 +typedef struct qlt_dt_riob1 {
973 + qlt_dt_entry_hdr_t h;
974 + uint32_t addr;
975 +#ifdef _BIG_ENDIAN
976 + uint8_t pci_offset;
977 + uint8_t reg_count_h;
978 + uint8_t reg_count_l;
979 + uint8_t reg_size;
980 +#else
981 + uint8_t reg_size;
982 + uint8_t reg_count_l;
983 + uint8_t reg_count_h;
984 + uint8_t pci_offset;
985 +#endif
986 +} qlt_dt_riob1_t;
987 +
988 +typedef struct qlt_dt_wiob1 {
989 + qlt_dt_entry_hdr_t h;
990 + uint32_t addr;
991 + uint32_t data;
992 +#ifdef _BIG_ENDIAN
993 + uint8_t rsv[3];
994 + uint8_t pci_offset;
995 +#else
996 + uint8_t pci_offset;
997 + uint8_t rsv[3];
998 +#endif
999 +} qlt_dt_wiob1_t;
1000 +
1001 +typedef struct qlt_dt_riob2 {
1002 + qlt_dt_entry_hdr_t h;
1003 + uint32_t addr;
1004 +#ifdef _BIG_ENDIAN
1005 + uint8_t pci_offset;
1006 + uint8_t reg_count_h;
1007 + uint8_t reg_count_l;
1008 + uint8_t reg_size;
1009 + uint8_t rsv[3];
1010 + uint8_t bank_sel_offset;
1011 +#else
1012 + uint8_t reg_size;
1013 + uint8_t reg_count_l;
1014 + uint8_t reg_count_h;
1015 + uint8_t pci_offset;
1016 + uint8_t bank_sel_offset;
1017 + uint8_t rsv[3];
1018 +#endif
1019 + uint32_t reg_bank;
1020 +} qlt_dt_riob2_t;
1021 +
1022 +typedef struct qlt_dt_wiob2 {
1023 + qlt_dt_entry_hdr_t h;
1024 + uint32_t addr;
1025 +#ifdef _BIG_ENDIAN
1026 + uint8_t rsv[2];
1027 + uint8_t data_h;
1028 + uint8_t data_l;
1029 + uint8_t bank_sel_offset;
1030 + uint8_t pci_offset;
1031 + uint8_t rsv1[2];
1032 +#else
1033 + uint8_t data_l;
1034 + uint8_t data_h;
1035 + uint8_t rsv[2];
1036 + uint8_t rsv1[2];
1037 + uint8_t pci_offset;
1038 + uint8_t bank_sel_offset;
1039 +#endif
1040 + uint32_t reg_bank;
1041 +} qlt_dt_wiob2_t;
1042 +
1043 +typedef struct qlt_dt_rpci {
1044 + qlt_dt_entry_hdr_t h;
1045 + uint32_t addr;
1046 +} qlt_dt_rpci_t;
1047 +
1048 +typedef struct qlt_dt_wpci {
1049 + qlt_dt_entry_hdr_t h;
1050 + uint32_t addr;
1051 + uint32_t data;
1052 +} qlt_dt_wpci_t, qlt_dt_wrreg_t;
1053 +
1054 +typedef struct qlt_dt_rram {
1055 + qlt_dt_entry_hdr_t h;
1056 +#ifdef _BIG_ENDIAN
1057 + uint8_t rsv[3];
1058 + uint8_t ram_area;
1059 +#else
1060 + uint8_t ram_area;
1061 + uint8_t rsv[3];
1062 +#endif
1063 + uint32_t start_addr;
1064 + uint32_t end_addr;
1065 +} qlt_dt_rram_t;
1066 +
1067 +typedef struct qlt_dt_gque {
1068 + qlt_dt_entry_hdr_t h;
1069 + uint32_t num_queues;
1070 +#ifdef _BIG_ENDIAN
1071 + uint8_t rsv[3];
1072 + uint8_t queue_type;
1073 +#else
1074 + uint8_t queue_type;
1075 + uint8_t rsv[3];
1076 +#endif
1077 +} qlt_dt_gque_t, qlt_dt_gques_t;
1078 +
1079 +typedef struct qlt_dt_gfce {
1080 + qlt_dt_entry_hdr_t h;
1081 + uint32_t fce_trace_size;
1082 + uint32_t write_pointer[2];
1083 + uint32_t base_pointer[2];
1084 + uint32_t fce_enable_mb0;
1085 + uint32_t fce_enable_mb2;
1086 + uint32_t fce_enable_mb3;
1087 + uint32_t fce_enable_mb4;
1088 + uint32_t fce_enable_mb5;
1089 + uint32_t fce_enable_mb6;
1090 +} qlt_dt_gfce_t;
1091 +
1092 +typedef struct qlt_dt_prisc {
1093 + qlt_dt_entry_hdr_t h;
1094 +} qlt_dt_prisc_t, qlt_dt_rrisc_t;
1095 +
1096 +typedef struct qlt_dt_dint {
1097 + qlt_dt_entry_hdr_t h;
1098 +#ifdef _BIG_ENDIAN
1099 + uint8_t rsv[3];
1100 + uint8_t pci_offset;
1101 +#else
1102 + uint8_t pci_offset;
1103 + uint8_t rsv[3];
1104 +#endif
1105 + uint32_t data;
1106 +} qlt_dt_dint_t;
1107 +
1108 +typedef struct qlt_dt_ghbd {
1109 + qlt_dt_entry_hdr_t h;
1110 +#ifdef _BIG_ENDIAN
1111 + uint8_t rsv[3];
1112 + uint8_t host_buf_type;
1113 +#else
1114 + uint8_t host_buf_type;
1115 + uint8_t rsv[3];
1116 +#endif
1117 + uint32_t buf_size;
1118 + uint32_t start_addr;
1119 +} qlt_dt_ghbd_t;
1120 +
1121 +typedef struct qlt_dt_scra {
1122 + qlt_dt_entry_hdr_t h;
1123 + uint32_t scratch_size;
1124 +} qlt_dt_scra_t;
1125 +
1126 +typedef struct qlt_dt_rrreg {
1127 + qlt_dt_entry_hdr_t h;
1128 + uint32_t addr;
1129 + uint32_t count;
1130 +} qlt_dt_rrreg_t, qlt_dt_rrram_t, qlt_dt_rpcic_t;
1131 +
1132 +typedef struct qlt_dt_wdmp {
1133 + qlt_dt_entry_hdr_t h;
1134 + uint32_t length;
1135 + uint32_t data[1];
1136 +} qlt_dt_wdmp_t;
1137 +
640 1138 #ifdef __cplusplus
641 1139 }
642 1140 #endif
643 1141
644 1142 #endif /* _QLT_REGS_H */
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