1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright 2009 QLogic Corporation. All rights reserved.
24 * Use is subject to license terms.
25 */
26
27 /*
28 * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved.
29 */
30
31 #ifndef _QLT_REGS_H
32 #define _QLT_REGS_H
33
34 #include <sys/stmf_defines.h>
35
36 #ifdef __cplusplus
37 extern "C" {
38 #endif
39
40 /*
41 * Register offsets
42 */
43 #define REG_FLASH_ADDR 0x00
44 #define REG_FLASH_DATA 0x04
45 #define REG_CTRL_STATUS 0x08
46 #define REG_INTR_CTRL 0x0C
47 #define REG_INTR_STATUS 0x10
48 #define REG_REQ_IN_PTR 0x1C
49 #define REG_REQ_OUT_PTR 0x20
50 #define REG_RESP_IN_PTR 0x24
51 #define REG_RESP_OUT_PTR 0x28
52 #define REG_PREQ_IN_PTR 0x2C
53 #define REG_PREQ_OUT_PTR 0x30
54 #define REG_ATIO_IN_PTR 0x3C
55 #define REG_ATIO_OUT_PTR 0x40
56 #define REG_RISC_STATUS 0x44
57 #define REG_HCCR 0x48
58 #define REG_GPIO_DATA 0x4C
59 #define REG_GPIO_ENABLE 0x50
60 #define REG_IOBUS_BASE_ADDR 0x54
61 #define REG_HOST_SEMA 0x58
62 #define REG_MBOX0 0x80
63
64 #define REG_MBOX(n) (REG_MBOX0 + (n << 1))
65
66 #define MAX_MBOXES 32
67
68 /*
69 * Ctrl Status register definitions
70 */
71 #define FLASH_ERROR BIT_18
72 #define DMA_ACTIVE_STATUS BIT_17
73 #define DMA_SHUTDOWN_CTRL BIT_16
74 #define FUNCTION_NUMBER BIT_15
75 /*
76 * #define 81XX_FUNCTION_NUMBER BIT_15 | BIT_14 | BIT_13 | BIT_12
77 */
78 #define PCI_X_BUS_MODE (BIT_8 | BIT_9 | BIT_10 | BIT_11)
79 #define PCI_X_XFER_CTRL (BIT_4 | BIT_5)
80 #define PCI_64_BIT_SLOT BIT_2
81 #define FLASH_WRITE_ENABLE BIT_1
82 #define CHIP_SOFT_RESET BIT_0
83
84 /*
85 * INTR_CTRL register
86 */
87 #define ENABLE_RISC_INTR BIT_3
88
89 /*
90 * INTR_STATUS register
91 */
92 #define RISC_PCI_INTR_REQUEST BIT_3
93
94 /*
95 * RISC_STATUS register
96 */
97 #define FW_INTR_INFO_MASK (BIT_15 | BIT_14 | BIT_13 | BIT_12 | \
98 BIT_11 | BIT_10 | BIT_9 | BIT_8 | \
99 BIT_7 | BIT_6 | BIT_5 | BIT_4 | \
100 BIT_3 | BIT_2 | BIT_1)
101 #define FW_INTR_INFO_SHIFT 18
102
103 #define FW_INTR_INFO(status) (status & (FW_INTR_INFO_MASK << \
104 FW_INTR_INFO_SHIFT))
105 #define RISC_HOST_INTR_REQUEST BIT_15
106 #define RISC_PAUSED BIT_8
107
108 #define FW_INTR_STATUS_MASK (BIT_7 | BIT_6 | BIT_5 | BIT_4 | \
109 BIT_3 | BIT_2 | BIT_1 | BIT_0)
110
111 #define ROM_MBX_CMD_SUCCESSFUL 0x01
112 #define ROM_MBX_CMD_NOT_SUCCESSFUL 0x02
113 #define MBX_CMD_SUCCESSFUL 0x10
114 #define MBX_CMD_NOT_SUCCESSFUL 0x11
115 #define ASYNC_EVENT 0x12
116 #define RESP_Q_UPDATE 0x13
117 #define ATIO_Q_UPDATE 0x1c
118 #define RESP_ATIO_Q_UPDATE 0x1d
119
120 /*
121 * Mailbox command completion status.
122 */
123 #define QLT_MBX_CMD_SUCCESS 0x4000
124
125 /*
126 * HCCR commands
127 */
128 #define NOP 0x00
129 #define SET_RISC_RESET 0x01
130 #define CLEAR_RISC_RESET 0x02
131 #define SET_RISC_PAUSE 0x03
132 #define CLEAR_RISC_PAUSE 0x04
133 #define SET_HOST_TO_RISC_INTR 0x05
134 #define CLEAR_HOST_TO_RISC_INTR 0x06
135 #define CLEAR_RISC_TO_PCI_INTR 0x0A
136
137 #define HCCR_CMD_SHIFT 28
138 #define HCCR_CMD(cmd) ((uint32_t)cmd << HCCR_CMD_SHIFT)
139
140 #define MBC_STOP_FIRMWARE 0x14
141
142 /*
143 * Flash/NVRAM definitions
144 */
145 #define FLASH_DATA_FLAG BIT_31
146 #define FLASH_CONF_ADDR 0x7FFD0000
147 #define FLASH_DATA_ADDR 0x7FF00000
148 #define FLASH_DATA_ADDR_81XX 0x7F8D0000
149 #define NVRAM_CONF_ADDR 0x7FFF0000
150 #define NVRAM_DATA_ADDR 0x7FFE0000
151
152 #define NVRAM_FUNC0_ADDR (NVRAM_DATA_ADDR + 0x80)
153 #define NVRAM_FUNC1_ADDR (NVRAM_DATA_ADDR + 0x180)
154
155 #define QLT25_NVRAM_FUNC0_ADDR (FLASH_DATA_ADDR + 0x48080)
156 #define QLT25_NVRAM_FUNC1_ADDR (FLASH_DATA_ADDR + 0x48180)
157
158 #define QLT81_NVRAM_FUNC0_ADDR (FLASH_DATA_ADDR_81XX + 0x80)
159 #define QLT81_NVRAM_FUNC1_ADDR (FLASH_DATA_ADDR_81XX + 0x180)
160
161 typedef struct qlt_nvram {
162 /* NVRAM header. */
163 uint8_t id[4];
164 uint8_t nvram_version[2];
165 uint8_t reserved_0[2];
166
167 /* Firmware Initialization Control Block. */
168 uint8_t version[2];
169 uint8_t reserved_1[2];
170 uint8_t max_frame_length[2];
171 uint8_t execution_throttle[2];
172 uint8_t exchange_count[2];
173 uint8_t hard_address[2];
174 uint8_t port_name[8];
175 uint8_t node_name[8];
176 uint8_t login_retry_count[2];
177 uint8_t link_down_on_nos[2];
178 uint8_t interrupt_delay_timer[2];
179 uint8_t login_timeout[2];
180
181 /*
182 * BIT 0 = Hard Assigned Loop ID
183 * BIT 1 = Enable Fairness
184 * BIT 2 = Enable Full-Duplex
185 * BIT 3 = Reserved
186 * BIT 4 = Target Mode Enable
187 * BIT 5 = Initiator Mode Disable
188 * BIT 6 = Reserved
189 * BIT 7 = Reserved
190 *
191 * BIT 8 = Reserved
192 * BIT 9 = Disable Initial LIP
193 * BIT 10 = Descending Loop ID Search
194 * BIT 11 = Previous Assigned Loop ID
195 * BIT 12 = Reserved
196 * BIT 13 = Full Login after LIP
197 * BIT 14 = Node Name Option
198 * BIT 15-31 = Reserved
199 */
200 uint8_t firmware_options_1[4];
201
202 /*
203 * BIT 0 = Operation Mode bit 0
204 * BIT 1 = Operation Mode bit 1
205 * BIT 2 = Operation Mode bit 2
206 * BIT 3 = Operation Mode bit 3
207 * BIT 4 = Connection Options bit 0
208 * BIT 5 = Connection Options bit 1
209 * BIT 6 = Connection Options bit 2
210 * BIT 7 = Enable Non part on LIHA failure
211 *
212 * BIT 8 = Enable Class 2
213 * BIT 9 = Enable ACK0
214 * BIT 10 = Reserved
215 * BIT 11 = Enable FC-SP Security
216 * BIT 12 = FC Tape Enable
217 * BIT 13-31 = Reserved
218 */
219 uint8_t firmware_options_2[4];
220
221 /*
222 * BIT 0 = Reserved
223 * BIT 1 = Soft ID only
224 * BIT 2 = Reserved
225 * BIT 3 = Reserved
226 * BIT 4 = FCP RSP Payload bit 0
227 * BIT 5 = FCP RSP Payload bit 1
228 * BIT 6 = Enable Rec Out-of-Order data frame handling
229 * BIT 7 = Disable Automatic PLOGI on Local Loop
230 *
231 * BIT 8 = Reserved
232 * BIT 9 = Enable Out-of-Order FCP_XFER_RDY relative
233 * offset handling
234 * BIT 10 = Reserved
235 * BIT 11 = Reserved
236 * BIT 12 = Reserved
237 * BIT 13 = Data Rate bit 0
238 * BIT 14 = Data Rate bit 1
239 * BIT 15 = Data Rate bit 2
240 * BIT 16 = 75-ohm Termination Select
241 * BIT 17-31 = Reserved
242 */
243 uint8_t firmware_options_3[4];
244
245 /*
246 * Serial Link Control (offset 56)
247 * BIT 0 = control enable
248 * BIT 1-15 = Reserved
249 */
250 uint8_t swing_opt[2];
251
252 /*
253 * Serial Link Control 1G (offset 58)
254 * BIT 0-7 = Reserved
255 *
256 * BIT 8-10 = output swing
257 * BIT 11-13 = output emphasis
258 * BIT 14-15 = Reserved
259 */
260 uint8_t swing_1g[2];
261
262 /*
263 * Serial Link Control 2G (offset 60)
264 * BIT 0-7 = Reserved
265 *
266 * BIT 8-10 = output swing
267 * BIT 11-13 = output emphasis
268 * BIT 14-15 = Reserved
269 */
270 uint8_t swing_2g[2];
271
272 /*
273 * Serial Link Control 4G (offset 62)
274 * BIT 0-7 = Reserved
275 *
276 * BIT 8-10 = output swing
277 * BIT 11-13 = output emphasis
278 * BIT 14-15 = Reserved
279 */
280 uint8_t swing_4g[2];
281
282 /* Offset 64. */
283 uint8_t reserved_2[32];
284
285 /* Offset 96. */
286 uint8_t reserved_3[32];
287
288 /* PCIe table entries. */
289 uint8_t reserved_4[32];
290
291 /* Offset 160. */
292 uint8_t reserved_5[32];
293
294 /* Offset 192. */
295 uint8_t reserved_6[32];
296
297 /* Offset 224. */
298 uint8_t reserved_7[32];
299
300 /*
301 * BIT 0 = Enable spinup delay
302 * BIT 1 = Disable BIOS
303 * BIT 2 = Enable Memory Map BIOS
304 * BIT 3 = Enable Selectable Boot
305 * BIT 4 = Disable RISC code load
306 * BIT 5 = Disable serdes
307 * BIT 6 = Enable opt boot mode
308 * BIT 7 = Enable int mode BIOS
309 *
310 * BIT 8 =
311 * BIT 9 =
312 * BIT 10 = Enable lip full login
313 * BIT 11 = Enable target reset
314 * BIT 12 =
315 * BIT 13 = Default Node Name Option
316 * BIT 14 = Default valid
317 * BIT 15 = Enable alternate WWN
318 *
319 * BIT 16-31 =
320 */
321 uint8_t host_p[4];
322
323 uint8_t alternate_port_name[8];
324 uint8_t alternate_node_name[8];
325
326 uint8_t boot_port_name[8];
327 uint8_t boot_lun_number[2];
328 uint8_t reserved_8[2];
329
330 uint8_t alt1_boot_port_name[8];
331 uint8_t alt1_boot_lun_number[2];
332 uint8_t reserved_9[2];
333
334 uint8_t alt2_boot_port_name[8];
335 uint8_t alt2_boot_lun_number[2];
336 uint8_t reserved_10[2];
337
338 uint8_t alt3_boot_port_name[8];
339 uint8_t alt3_boot_lun_number[2];
340 uint8_t reserved_11[2];
341
342 /*
343 * BIT 0 = Selective Login
344 * BIT 1 = Alt-Boot Enable
345 * BIT 2 = Reserved
346 * BIT 3 = Enable Boot Order List
347 * BIT 4 = Reserved
348 * BIT 5 = Enable Selective LUN
349 * BIT 6 = Reserved
350 * BIT 7-31 =
351 */
352 uint8_t efi_parameters[4];
353
354 uint8_t reset_delay;
355 uint8_t reserved_12;
356 uint8_t reserved_13[2];
357
358 uint8_t boot_id_number[2];
359 uint8_t reserved_14[2];
360
361 uint8_t max_luns_per_target[2];
362 uint8_t reserved_15[2];
363
364 uint8_t port_down_retry_count[2];
365 uint8_t link_down_timeout[2];
366
367 /*
368 * FCode parameters word (offset 344)
369 *
370 * BIT 0 = Enable BIOS pathname
371 * BIT 1 = fcode qlc
372 * BIT 2 = fcode host
373 * BIT 3-7 =
374 */
375 uint8_t fcode_p0;
376 uint8_t reserved_16[7];
377
378 /* Offset 352. */
379 uint8_t prev_drv_ver_major;
380 uint8_t prev_drv_ver_submajob;
381 uint8_t prev_drv_ver_minor;
382 uint8_t prev_drv_ver_subminor;
383
384 uint8_t prev_bios_ver_major[2];
385 uint8_t prev_bios_ver_minor[2];
386
387 uint8_t prev_efi_ver_major[2];
388 uint8_t prev_efi_ver_minor[2];
389
390 uint8_t prev_fw_ver_major[2];
391 uint8_t prev_fw_ver_minor;
392 uint8_t prev_fw_ver_subminor;
393
394 uint8_t reserved_17[16];
395
396 /* Offset 384. */
397 uint8_t def_port_name[8];
398 uint8_t def_node_name[8];
399
400 uint8_t reserved_18[16];
401
402 /* Offset 416. */
403 uint8_t reserved_19[32];
404
405 /* Offset 448. */
406 uint8_t reserved_20[28];
407
408 /* Offset 476. */
409 uint8_t fw_table_offset[2];
410 uint8_t fw_table_sig[2];
411
412 /* Offset 480. */
413 uint8_t model_name[8];
414
415 /* Offset 488. */
416 uint8_t power_table[16];
417
418 uint8_t subsystem_vendor_id[2];
419 uint8_t subsystem_device_id[2];
420
421 uint8_t checksum[4];
422 } qlt_nvram_t;
423
424 /* ISP81xx Extended Initialisation Control Block */
425 typedef struct qlt_ext_icb_81xx {
426
427 uint8_t version[2];
428 uint8_t fcf_vlan_match;
429 uint8_t reserved_6[3];
430 uint8_t fcf_vlan_id[2];
431 uint8_t fcf_fabric_name[8];
432 uint8_t reserved_7[14];
433 uint8_t spma_proposed_mac_address[6];
434 uint8_t reserved_8[28];
435
436 } qlt_ext_icb_81xx_t;
437
438 typedef struct qlt_nvram_81xx {
439 /* NVRAM header. */
440 uint8_t id[4];
441 uint8_t nvram_version[2];
442 uint8_t reserved_0[2];
443
444 /* Firmware Initialization Control Block. */
445 uint8_t version[2];
446 uint8_t reserved_1[2];
447 uint8_t max_frame_length[2];
448 uint8_t execution_throttle[2];
449 uint8_t exchange_count[2];
450 uint8_t reserved_2[2];
451 uint8_t port_name[8];
452 uint8_t node_name[8];
453 uint8_t login_retry_count[2];
454 uint8_t reserved_3[2];
455 uint8_t interrupt_delay_timer[2];
456 uint8_t login_timeout[2];
457
458 /*
459 * BIT 0 = Hard Assigned Loop ID
460 * BIT 1 = Enable Fairness
461 * BIT 2 = Enable Full-Duplex
462 * BIT 3 = Reserved
463 * BIT 4 = Target Mode Enable
464 * BIT 5 = Initiator Mode Disable
465 * BIT 6 = Reserved
466 * BIT 7 = Reserved
467 *
468 * BIT 8 = Reserved
469 * BIT 9 = Reserved
470 * BIT 10 = Reserved
471 * BIT 11 = Reserved
472 * BIT 12 = Reserved
473 * BIT 13 = Reserved
474 * BIT 14 = Node Name Option
475 * BIT 15-31 = Reserved
476 */
477 uint8_t firmware_options_1[4];
478
479 /*
480 * BIT 0 = Operation Mode bit 0
481 * BIT 1 = Operation Mode bit 1
482 * BIT 2 = Operation Mode bit 2
483 * BIT 3 = Operation Mode bit 3
484 * BIT 4 = Reserved
485 * BIT 5 = Reserved
486 * BIT 6 = Reserved
487 * BIT 7 = Reserved
488 *
489 * BIT 8 = Enable Class 2
490 * BIT 9 = Enable ACK0
491 * BIT 10 = Reserved
492 * BIT 11 = Enable FC-SP Security
493 * BIT 12 = FC Tape Enable
494 * BIT 13 = Reserved
495 * BIT 14 = Target PRLI Control
496 * BIT 15-31 = Reserved
497 */
498 uint8_t firmware_options_2[4];
499
500 /*
501 * BIT 0 = Reserved
502 * BIT 1 = Soft ID only
503 * BIT 2 = Reserved
504 * BIT 3 = Reserved
505 * BIT 4 = FCP RSP Payload bit 0
506 * BIT 5 = FCP RSP Payload bit 1
507 * BIT 6 = Enable Rec Out-of-Order data frame handling
508 * BIT 7 = Reserved
509 *
510 * BIT 8 = Reserved
511 * BIT 9 = Enable Out-of-Order FCP_XFER_RDY relative
512 * offset handling
513 * BIT 10 = Reserved
514 * BIT 11 = Reserved
515 * BIT 12 = Reserved
516 * BIT 13 = Reserved
517 * BIT 14 = Reserved
518 * BIT 15 = Reserved
519 * BIT 16 = Reserved
520 * BIT 17 = Enable Multiple FCFs
521 * BIT 18-20 = MAC Addressing Mode
522 * BIT 21-25 = Ethernet Data Rate
523 * BIT 26 = Enable Ethernet Header Receive ATIO_Q
524 * BIT 27 = Enable Ethernet Header Receive RSP_Q
525 * BIT 28-29 = SPMA Selection
526 * BIT 30-31 = Reserved
527 */
528 uint8_t firmware_options_3[4];
529
530 /* Offset 56 (38h). */
531 uint8_t reserved_4[8];
532
533 /* Offset 64 (40h). */
534 uint8_t enode_mac[6];
535
536 /* Offset 70 (46h). */
537 uint8_t reserved_5[26];
538
539 /* Offset 96 (60h). */
540 uint8_t oem_specific;
541 uint8_t reserved_6[15];
542
543 /* Offset 112 (70h). */
544 uint8_t reserved_7[16];
545
546 /* Offset 128 (80h). */
547 qlt_ext_icb_81xx_t ext_blk;
548
549 /* Offset 192. */
550 uint8_t reserved_8[32];
551
552 /* Offset 224. */
553 uint8_t reserved_9[32];
554
555 uint8_t host_p[4];
556
557 uint8_t alternate_port_name[8];
558 uint8_t alternate_name_name[8];
559
560 uint8_t boot_port_name[8];
561 uint8_t boot_lun_number[2];
562 uint8_t reserved_10[2];
563
564 uint8_t alt1_boot_port_name[8];
565 uint8_t alt1_boot_lun_number[2];
566 uint8_t reserved_11[2];
567
568 uint8_t alt2_boot_port_name[8];
569 uint8_t alt2_boot_lun_number[2];
570 uint8_t reserved_12[2];
571
572 uint8_t alt3_boot_port_name[8];
573 uint8_t alt3_boot_lun_number[2];
574 uint8_t reserved_13[2];
575
576 /*
577 * BIT 0 = Selective Login
578 * BIT 1 = Alt-Boot Enable
579 * BIT 2 = Reserved
580 * BIT 3 = Enable Boot Order List
581 * BIT 4 = Reserved
582 * BIT 5 = Enable Selective LUN
583 * BIT 6 = Reserved
584 * BIT 7-31 =
585 */
586 uint8_t efi_parameters[4];
587
588 uint8_t reset_delay;
589 uint8_t reserved_14;
590 uint8_t reserved_15[2];
591
592 uint8_t boot_id_number[2];
593 uint8_t reserved_16[2];
594
595 uint8_t max_luns_per_target[2];
596 uint8_t reserved_17[2];
597
598 uint8_t port_down_retry_count[2];
599 uint8_t link_down_timeout[2];
600
601 /*
602 * FCode parameters word (offset 344)
603 *
604 * BIT 0 = Enable BIOS pathname
605 * BIT 1 = fcode qlc
606 * BIT 2 = fcode host
607 * BIT 3-7 =
608 */
609 uint8_t fcode_parameter[2];
610 uint8_t reserved_18[6];
611
612 /* Offset 352. */
613 uint8_t reserved_19[4];
614 uint8_t reserved_20[10];
615 uint8_t reserved_21[2];
616 uint8_t reserved_22[16];
617
618 /* Offset 384. */
619 uint8_t reserved_23[16];
620 uint8_t reserved_24[16];
621
622 /* Offset 416. */
623 uint8_t reserved_25[64];
624
625 /* Offset 480. */
626 uint8_t model_name[16];
627
628 /* Offset 496. */
629 uint8_t feature_mask_l[2];
630 uint8_t feature_mask_h[2];
631 uint8_t reserved_26[4];
632
633 uint8_t subsystem_vendor_id[2];
634 uint8_t subsystem_device_id[2];
635
636 uint8_t checksum[4];
637
638 } qlt_nvram_81xx_t;
639
640 #ifdef __cplusplus
641 }
642 #endif
643
644 #endif /* _QLT_REGS_H */