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NEX-5733 cleanup qlt/qlc
Reviewed by: Yuri Pankov <yuri.pankov@nexenta.com>
Reviewed by: Alek Pinchuk <alek.pinchuk@nexenta.com>
NEX-5717 import QLogic 16G FC drivers
Reviewed by: Steve Peng <steve.peng@nexenta.com>
Reviewed by: Josef 'Jeff' Sipek <josef.sipek@nexenta.com>
Reviewed by: Yuri Pankov <yuri.pankov@nexenta.com>
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--- old/usr/src/cmd/mdb/common/modules/qlc/qlc.c
+++ new/usr/src/cmd/mdb/common/modules/qlc/qlc.c
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
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12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21
22 -/* Copyright 2010 QLogic Corporation */
22 +/* Copyright 2015 QLogic Corporation */
23 23
24 24 /*
25 25 * ISP2xxx Solaris Fibre Channel Adapter (FCA) qlc mdb source file.
26 26 *
27 27 * ***********************************************************************
28 28 * * **
29 29 * * NOTICE **
30 - * * COPYRIGHT (C) 1996-2010 QLOGIC CORPORATION **
30 + * * COPYRIGHT (C) 1996-2015 QLOGIC CORPORATION **
31 31 * * ALL RIGHTS RESERVED **
32 32 * * **
33 33 * ***********************************************************************
34 34 *
35 35 */
36 36
37 -#pragma ident "Copyright 2010 QLogic Corporation; ql_mdb.c"
37 +#pragma ident "Copyright 2015 QLogic Corporation; ql_mdb.c"
38 38
39 39 #include <sys/mdb_modapi.h>
40 40 #include <ql_apps.h>
41 41 #include <ql_api.h>
42 42 #include <ql_init.h>
43 -#include <ql_debug.h>
44 43
45 44 /*
46 45 * local prototypes
47 46 */
48 47 static int32_t ql_doprint(uintptr_t, int8_t *);
49 48 static void ql_dump_flags(uint64_t, int8_t **);
50 49 static int qlclinks_dcmd(uintptr_t, uint_t, int, const mdb_arg_t *);
51 50 static int qlcstate_dcmd(uintptr_t, uint_t, int, const mdb_arg_t *);
52 51 static int qlc_osc_dcmd(uintptr_t, uint_t, int, const mdb_arg_t *);
53 52 static int qlc_wdog_dcmd(uintptr_t, uint_t, int, const mdb_arg_t *);
54 53 static int qlc_getdump_dcmd(uintptr_t, uint_t, int, const mdb_arg_t *);
55 54 static int qlc_gettrace_dcmd(uintptr_t, uint_t, int, const mdb_arg_t *);
56 55 #if 0
57 56 static int qlc_triggerdump_dcmd(uintptr_t, uint_t, int, const mdb_arg_t *);
58 57 #endif
59 58 static int qlcver_dcmd(uintptr_t, uint_t, int, const mdb_arg_t *);
60 59 static int qlstates_walk_init(mdb_walk_state_t *);
61 60 static int qlstates_walk_step(mdb_walk_state_t *);
62 61 static void qlstates_walk_fini(mdb_walk_state_t *);
63 62 static int qlsrb_walk_init(mdb_walk_state_t *);
64 63 static int qlsrb_walk_step(mdb_walk_state_t *);
65 64 static void qlsrb_walk_fini(mdb_walk_state_t *);
66 65 static int get_next_link(ql_link_t *);
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67 66 static int get_first_link(ql_head_t *, ql_link_t *);
68 67
69 68 static int ql_24xx_dump_dcmd(ql_adapter_state_t *, uint_t, int,
70 69 const mdb_arg_t *);
71 70 static int ql_23xx_dump_dcmd(ql_adapter_state_t *, uint_t, int,
72 71 const mdb_arg_t *);
73 72 static int ql_25xx_dump_dcmd(ql_adapter_state_t *, uint_t, int,
74 73 const mdb_arg_t *);
75 74 static int ql_81xx_dump_dcmd(ql_adapter_state_t *, uint_t, int,
76 75 const mdb_arg_t *);
76 +static int ql_8021_dump_dcmd(ql_adapter_state_t *, uint_t, int,
77 + const mdb_arg_t *);
78 +static int ql_8300_dump_dcmd(ql_adapter_state_t *, uint_t, int,
79 + const mdb_arg_t *);
77 80 static void ql_elog_common(ql_adapter_state_t *, boolean_t);
78 81
79 82 /*
80 83 * local adapter state flags strings
81 84 */
82 85 int8_t *adapter_state_flags[] = {
83 86 "FCA_BOUND",
84 87 "QL_OPENED",
85 88 "ONLINE",
86 89 "INTERRUPTS_ENABLED",
87 90 "ABORT_CMDS_LOOP_DOWN_TMO",
88 91 "POINT_TO_POINT",
89 92 "IP_ENABLED",
90 93 "IP_INITIALIZED",
91 94 "MENLO_LOGIN_OPERATIONAL",
92 95 "ADAPTER_SUSPENDED",
93 - "ADAPTER_TIMER_BUSY",
96 + "FW_DUMP_NEEDED",
94 97 "PARITY_ERROR",
95 98 "FLASH_ERRLOG_MARKER",
96 99 "VP_ENABLED",
97 100 "FDISC_ENABLED",
98 - "FUNCTION_1",
101 + "MULTI_QUEUE",
99 102 "MPI_RESET_NEEDED",
103 + "VP_ID_NOT_ACQUIRED",
104 + "IDC_STALL_NEEDED",
105 + "POLL_INTR",
106 + "IDC_RESTART_NEEDED",
107 + "IDC_ACK_NEEDED",
108 + "LOOPBACK_ACTIVE",
109 + "QUEUE_SHADOW_PTRS",
110 + "NO_INTR_HANDSHAKE",
111 + "COMP_THD_TERMINATE",
112 + "DISABLE_NIC_FW_DMP",
113 + "MULTI_CHIP_ADAPTER",
100 114 NULL
101 115 };
102 116
103 117 int8_t *adapter_config_flags[] = {
104 - "ENABLE_HARD_ADDRESS",
118 + "CTRL_27XX",
105 119 "ENABLE_64BIT_ADDRESSING",
106 120 "ENABLE_LIP_RESET",
107 121 "ENABLE_FULL_LIP_LOGIN",
108 122 "ENABLE_TARGET_RESET",
109 123 "ENABLE_LINK_DOWN_REPORTING",
110 124 "DISABLE_EXTENDED_LOGGING_TRACE",
111 125 "ENABLE_FCP_2_SUPPORT",
112 - "MULTI_CHIP_ADAPTER",
126 + "CTRL_83XX",
113 127 "SBUS_CARD",
114 - "CTRL_2300",
115 - "CTRL_6322",
116 - "CTRL_2200",
117 - "CTRL_2422",
128 + "CTRL_23XX",
129 + "CTRL_63XX",
130 + "CTRL_22XX",
131 + "CTRL_24XX",
118 132 "CTRL_25XX",
119 133 "ENABLE_EXTENDED_LOGGING",
120 134 "DISABLE_RISC_CODE_LOAD",
121 135 "SET_CACHE_LINE_SIZE_1",
122 136 "CTRL_MENLO",
123 137 "EXT_FW_INTERFACE",
124 138 "LOAD_FLASH_FW",
125 139 "DUMP_MAILBOX_TIMEOUT",
126 140 "DUMP_ISP_SYSTEM_ERROR",
127 141 "DUMP_DRIVER_COMMAND_TIMEOUT",
128 142 "DUMP_LOOP_OFFLINE_TIMEOUT",
129 143 "ENABLE_FWEXTTRACE",
130 144 "ENABLE_FWFCETRACE",
131 - "FW_MISMATCH",
145 + "CTRL_80XX",
132 146 "CTRL_81XX",
133 - "CTRL_8021",
134 - "ENABLE_FAST_TIMEOUT",
147 + "CTRL_82XX",
148 + "FAST_TIMEOUT",
135 149 "LR_SUPPORT",
136 150 NULL
137 151 };
138 152
139 153 /*
140 154 * local task daemon flags strings
141 155 */
142 156 int8_t *task_daemon_flags[] = {
143 157 "TASK_DAEMON_STOP_FLG",
144 158 "TASK_DAEMON_SLEEPING_FLG",
145 159 "TASK_DAEMON_ALIVE_FLG",
146 160 "TASK_DAEMON_IDLE_CHK_FLG",
147 161 "SUSPENDED_WAKEUP_FLG",
148 162 "FC_STATE_CHANGE",
149 163 "NEED_UNSOLICITED_BUFFERS",
150 - "RESET_MARKER_NEEDED",
151 - "RESET_ACTIVE",
164 + "MARKER_NEEDED",
165 + "MARKER_ACTIVE",
152 166 "ISP_ABORT_NEEDED",
153 167 "ABORT_ISP_ACTIVE",
154 168 "LOOP_RESYNC_NEEDED",
155 169 "LOOP_RESYNC_ACTIVE",
156 170 "LOOP_DOWN",
157 171 "DRIVER_STALL",
158 172 "COMMAND_WAIT_NEEDED",
159 173 "COMMAND_WAIT_ACTIVE",
160 174 "STATE_ONLINE",
161 175 "ABORT_QUEUES_NEEDED",
162 176 "TASK_DAEMON_STALLED_FLG",
163 - "TASK_THREAD_CALLED",
177 + "SEND_PLOGI",
164 178 "FIRMWARE_UP",
165 - "LIP_RESET_PENDING",
179 + "IDC_POLL_NEEDED",
166 180 "FIRMWARE_LOADED",
167 181 "RSCN_UPDATE_NEEDED",
168 182 "HANDLE_PORT_BYPASS_CHANGE",
169 183 "PORT_RETRY_NEEDED",
170 184 "TASK_DAEMON_POWERING_DOWN",
171 185 "TD_IIDMA_NEEDED",
172 - "SEND_PLOGI",
173 - "IDC_EVENT",
186 + "WATCHDOG_NEEDED",
187 + "LED_BLINK",
174 188 NULL
175 189 };
176 190
177 191 /*
178 192 * local interrupt aif flags
179 193 */
180 194 int8_t *aif_flags[] = {
181 195 "IFLG_INTR_LEGACY",
182 196 "IFLG_INTR_FIXED",
183 197 "IFLG_INTR_MSI",
184 198 "IFLG_INTR_MSIX",
185 199 NULL
186 200 };
187 201
188 202 int8_t *qlsrb_flags[] = {
189 203 "SRB_ISP_STARTED",
190 204 "SRB_ISP_COMPLETED",
191 205 "SRB_RETRY",
192 206 "SRB_POLL",
193 207 "SRB_WATCHDOG_ENABLED",
194 208 "SRB_ABORT",
195 209 "SRB_UB_IN_FCA",
196 210 "SRB_UB_IN_ISP",
197 211 "SRB_UB_CALLBACK",
198 212 "SRB_UB_RSCN",
199 213 "SRB_UB_FCP",
200 214 "SRB_FCP_CMD_PKT",
201 215 "SRB_FCP_DATA_PKT",
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202 216 "SRB_FCP_RSP_PKT",
203 217 "SRB_IP_PKT",
204 218 "SRB_GENERIC_SERVICES_PKT",
205 219 "SRB_COMMAND_TIMEOUT",
206 220 "SRB_ABORTING",
207 221 "SRB_IN_DEVICE_QUEUE",
208 222 "SRB_IN_TOKEN_ARRAY",
209 223 "SRB_UB_FREE_REQUESTED",
210 224 "SRB_UB_ACQUIRED",
211 225 "SRB_MS_PKT",
226 + "SRB_ELS_PKT",
212 227 NULL
213 228 };
214 229
215 230 int8_t *qllun_flags[] = {
216 231 "LQF_UNTAGGED_PENDING",
217 232 NULL
218 233 };
219 234
220 235 int8_t *qltgt_flags[] = {
221 236 "TQF_TAPE_DEVICE",
222 237 "TQF_QUEUE_SUSPENDED",
223 238 "TQF_FABRIC_DEVICE",
224 239 "TQF_INITIATOR_DEVICE",
225 240 "TQF_RSCN_RCVD",
226 241 "TQF_NEED_AUTHENTICATION",
227 242 "TQF_PLOGI_PROGRS",
228 243 "TQF_IIDMA_NEEDED",
244 + "TQF_LOGIN_NEEDED",
229 245 NULL
230 246 };
231 247
232 248 int8_t *qldump_flags[] = {
233 249 "QL_DUMPING",
234 250 "QL_DUMP_VALID",
235 251 "QL_DUMP_UPLOADED",
236 252 NULL
237 253 };
238 254
239 255 /*
240 256 * qlclinks_dcmd
241 257 * mdb dcmd which prints out the ql_hba pointers
242 258 *
243 259 * Input:
244 260 * addr = User supplied address -- error if supplied.
245 261 * flags = mdb flags.
246 262 * argc = Number of user supplied args -- error if non-zero.
247 263 * argv = Arg array.
248 264 *
249 265 * Returns:
250 266 * DCMD_ERR, DCMD_USAGE, or DCMD_OK
251 267 *
252 268 * Context:
253 269 * User context.
254 270 *
255 271 */
256 272 /*ARGSUSED*/
257 273 static int
258 274 qlclinks_dcmd(uintptr_t addr, uint_t flags, int argc, const mdb_arg_t *argv)
259 275 {
260 276 ql_head_t ql_hba;
261 277 ql_adapter_state_t *qlstate;
262 278 uintptr_t hbaptr = NULL;
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263 279
264 280 if ((flags & DCMD_ADDRSPEC) || argc != 0) {
265 281 return (DCMD_USAGE);
266 282 }
267 283
268 284 if (mdb_readvar(&ql_hba, "ql_hba") == -1) {
269 285 mdb_warn("failed to read ql_hba structure");
270 286 return (DCMD_ERR);
271 287 }
272 288
273 - if (&ql_hba == NULL) {
289 + if (ql_hba.first == NULL) {
274 290 mdb_warn("failed to read ql_hba structure -- is qlc loaded?");
275 291 return (DCMD_ERR);
276 292 }
277 293
278 294 mdb_printf("\nqlc adapter state linkages (f=0x%llx, l=0x%llx)\n\n",
279 295 ql_hba.first, ql_hba.last);
280 296
281 297 if ((qlstate = (ql_adapter_state_t *)mdb_alloc(
282 298 sizeof (ql_adapter_state_t), UM_SLEEP)) == NULL) {
283 299 mdb_warn("Unable to allocate memory for ql_adapter_state\n");
284 300 return (DCMD_OK);
285 301 }
286 302
287 303 (void) mdb_inc_indent((ulong_t)4);
288 304 mdb_printf("%<u>%-?s\t%-45s%</u>\n\n", "baseaddr", "instance");
289 305
290 306 hbaptr = (uintptr_t)ql_hba.first;
291 307 while (hbaptr != NULL) {
292 308
293 309 if (mdb_vread(qlstate, sizeof (ql_adapter_state_t),
294 310 hbaptr) == -1) {
295 311 mdb_free(qlstate, sizeof (ql_adapter_state_t));
296 312 mdb_warn("failed to read ql_adapter_state at %p",
297 313 hbaptr);
298 314 return (DCMD_OK);
299 315 }
300 316
301 317 mdb_printf("%<b>0x%016p%t%d%</b>\n",
302 318 qlstate->hba.base_address, qlstate->instance);
303 319
304 320 /*
305 321 * If vp exists, loop through those
306 322 */
307 323
308 324 if ((qlstate->flags & VP_ENABLED) &&
309 325 (qlstate->vp_next != NULL)) {
310 326
311 327 ql_adapter_state_t *vqlstate;
312 328 uintptr_t vhbaptr = NULL;
313 329
314 330 vhbaptr = (uintptr_t)qlstate->vp_next;
315 331
316 332 if ((vqlstate = (ql_adapter_state_t *)mdb_alloc(
317 333 sizeof (ql_adapter_state_t), UM_SLEEP)) == NULL) {
318 334 mdb_warn("Unable to allocate memory for "
319 335 "ql_adapter_state vp\n");
320 336 mdb_free(qlstate, sizeof (ql_adapter_state_t));
321 337 return (DCMD_OK);
322 338 }
323 339
324 340 (void) mdb_inc_indent((ulong_t)30);
325 341
326 342 mdb_printf("%<u>vp baseaddr\t\tvp index%</u>\n");
327 343
328 344 while (vhbaptr != NULL) {
329 345
330 346 if (mdb_vread(vqlstate,
331 347 sizeof (ql_adapter_state_t), vhbaptr) ==
332 348 -1) {
333 349 mdb_free(vqlstate,
334 350 sizeof (ql_adapter_state_t));
335 351 mdb_free(qlstate,
336 352 sizeof (ql_adapter_state_t));
337 353 mdb_warn("failed to read vp "
338 354 "ql_adapter_state at %p", vhbaptr);
339 355 return (DCMD_OK);
340 356 }
341 357
342 358 mdb_printf("%<b>0x%016p%t%d%</b>\n",
343 359 vqlstate->hba.base_address,
344 360 vqlstate->vp_index);
345 361
346 362 vhbaptr = (uintptr_t)vqlstate->vp_next;
347 363 }
348 364
349 365 mdb_free(vqlstate, sizeof (ql_adapter_state_t));
350 366
351 367 (void) mdb_dec_indent((ulong_t)30);
352 368
353 369 mdb_printf("\n");
354 370 }
355 371
356 372 hbaptr = (uintptr_t)qlstate->hba.next;
357 373 }
358 374
359 375 (void) mdb_dec_indent((ulong_t)4);
360 376
361 377 mdb_free(qlstate, sizeof (ql_adapter_state_t));
362 378
363 379 return (DCMD_OK);
364 380 }
365 381
366 382 /*
367 383 * qlcver_dcmd
368 384 * mdb dcmd which prints out the qlc driver version the mdb
369 385 * module was compiled with, and the verison of qlc which is
370 386 * currently loaded on the machine.
371 387 *
372 388 * Input:
373 389 * addr = User supplied address -- error if supplied.
374 390 * flags = mdb flags.
375 391 * argc = Number of user supplied args -- error if non-zero.
376 392 * argv = Arg array.
377 393 *
378 394 * Returns:
379 395 * DCMD_USAGE, or DCMD_OK
380 396 *
381 397 * Context:
382 398 * User context.
383 399 *
384 400 */
385 401 /*ARGSUSED*/
386 402 static int
387 403 qlcver_dcmd(uintptr_t addr, uint_t flags, int argc, const mdb_arg_t *argv)
388 404 {
389 405 int8_t qlcversion[100];
390 406 struct fw_table fw_table[10], *fwt = NULL;
391 407 uint8_t *fwverptr = NULL;
392 408 ql_head_t ql_hba;
393 409 uint32_t found = 0;
394 410
395 411 if ((flags & DCMD_ADDRSPEC) || argc != 0) {
396 412 return (DCMD_USAGE);
397 413 }
398 414
399 415 if (mdb_readvar(&qlcversion, "qlc_driver_version") == -1) {
400 416 mdb_warn("unable to read qlc driver version\n");
401 417 } else {
402 418 mdb_printf("\n%s version currently loaded is: %s\n",
403 419 QL_NAME, qlcversion);
404 420 }
405 421
406 422 mdb_printf("qlc mdb library compiled with %s version: %s\n",
407 423 QL_NAME, QL_VERSION);
408 424
409 425 if ((fwverptr = (uint8_t *)(mdb_alloc(50, UM_SLEEP))) == NULL) {
410 426 mdb_warn("unable to alloc fwverptr\n");
411 427 return (DCMD_OK);
412 428 }
413 429
414 430 if (mdb_readvar(&fw_table, "fw_table") == -1) {
415 431 mdb_warn("unable to read firmware table\n");
416 432 } else {
417 433 ql_adapter_state_t *qlstate;
418 434 uintptr_t hbaptr = NULL;
419 435
420 436 if (mdb_readvar(&ql_hba, "ql_hba") == -1) {
421 437 mdb_warn("failed to read ql_hba structure");
422 438 return (DCMD_ERR);
423 439 }
424 440
425 441 if ((qlstate = (ql_adapter_state_t *)mdb_alloc(
426 442 sizeof (ql_adapter_state_t), UM_SLEEP)) == NULL) {
427 443 mdb_warn("Unable to allocate memory for "
428 444 "ql_adapter_state\n");
429 445 return (DCMD_OK);
430 446 }
431 447
432 448 mdb_printf("\n%-8s%-11s%s\n", "f/w", "compiled", "loaded");
433 449 mdb_printf("%<u>%-8s%-11s%-13s%s%</u>\n\n", "class", "version",
434 450 "version", "instance list");
435 451
436 452 for (fwt = &fw_table[0]; fwt->fw_class; fwt++) {
437 453
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438 454 if (mdb_vread(fwverptr, sizeof (void *),
439 455 (uintptr_t)fwt->fw_version) == -1) {
440 456 mdb_warn("unable to read fwverptr\n");
441 457 mdb_free(fwverptr, sizeof (void *));
442 458 mdb_free(qlstate, sizeof (ql_adapter_state_t));
443 459 return (DCMD_OK);
444 460 }
445 461
446 462 mdb_printf("%x\t%-11s", fwt->fw_class, fwverptr);
447 463
448 - if (&ql_hba == NULL) {
464 + if (ql_hba.first == NULL) {
449 465 mdb_warn("failed to read ql_hba structure");
450 466 hbaptr = NULL;
451 467 } else {
452 468 hbaptr = (uintptr_t)ql_hba.first;
453 469 }
454 470
455 471 found = 0;
456 472 while (hbaptr != NULL) {
457 473
458 474 if (mdb_vread(qlstate,
459 475 sizeof (ql_adapter_state_t), hbaptr) ==
460 476 -1) {
461 477 mdb_warn("failed to read "
462 478 "ql_adapter_state at %p", hbaptr);
463 479 break;
464 480 }
465 481
466 482 if (qlstate->fw_class == fwt->fw_class) {
467 483 if (found == 0) {
468 484 mdb_printf("%x.%02x.%02x\t",
469 485 qlstate->fw_major_version,
470 486 qlstate->fw_minor_version,
471 487 qlstate->
472 488 fw_subminor_version);
473 489 mdb_printf("%d",
474 490 qlstate->instance);
475 491 } else {
476 492 mdb_printf(", %d",
477 493 qlstate->instance);
478 494 }
479 495 found = 1;
480 496 }
481 497
482 498 hbaptr = (uintptr_t)qlstate->hba.next;
483 499 }
484 500
485 501 if (found == 1) {
486 502 mdb_printf("\n");
487 503 } else {
488 504 mdb_printf("not loaded\n");
489 505 }
490 506 }
491 507
492 508 mdb_free(qlstate, sizeof (ql_adapter_state_t));
493 509 mdb_free(fwverptr, sizeof (void *));
494 510 }
495 511
496 512 return (DCMD_OK);
497 513 }
498 514
499 515 /*
500 516 * qlc_el_dcmd
501 517 * mdb dcmd which turns the extended logging bit on or off
502 518 * for the specificed qlc instance(s).
503 519 *
504 520 * Input:
505 521 * addr = User supplied address -- error if supplied.
506 522 * flags = mdb flags.
507 523 * argc = Number of user supplied args -- error if non-zero.
508 524 * argv = Arg array.
509 525 *
510 526 * Returns:
511 527 * DCMD_USAGE, or DCMD_OK
512 528 *
513 529 * Context:
514 530 * User context.
515 531 *
516 532 */
517 533 /*ARGSUSED*/
518 534 static int
519 535 qlc_el_dcmd(uintptr_t addr, uint_t flags, int argc, const mdb_arg_t *argv)
520 536 {
521 537 int8_t qlcversion[100];
522 538 boolean_t elswitch;
523 539 uint32_t argcnt;
524 540 int mdbs;
525 541 uint32_t instance;
526 542 uint32_t qlsize = sizeof (ql_adapter_state_t);
527 543 ql_adapter_state_t *qlstate;
528 544 uintptr_t hbaptr = NULL;
529 545 ql_head_t ql_hba;
530 546
531 547 if ((mdbs = mdb_get_state()) == MDB_STATE_DEAD) {
532 548 mdb_warn("Cannot change core file data (state=%xh)\n", mdbs);
533 549 return (DCMD_OK);
534 550 }
535 551
536 552 if ((flags & DCMD_ADDRSPEC) || argc < 2) {
537 553 return (DCMD_USAGE);
538 554 }
539 555
540 556 /*
541 557 * Check and make sure the driver version and the mdb versions
542 558 * match so all the structures and flags line up
543 559 */
544 560
545 561 if (mdb_readvar(&qlcversion, "qlc_driver_version") == -1) {
546 562 mdb_warn("unable to read qlc driver version\n");
547 563 return (DCMD_OK);
548 564 }
549 565
550 566 if ((strcmp(QL_VERSION, (const char *)&qlcversion)) != 0) {
551 567 mdb_warn("Error: qlc driver/qlc mdb version mismatch\n");
552 568 mdb_printf("\tqlc mdb library compiled version is: %s\n",
553 569 QL_VERSION);
554 570 mdb_printf("\tqlc driver version is: %s\n", qlcversion);
555 571
556 572 return (DCMD_OK);
557 573 }
558 574
559 575 if ((strcasecmp(argv[0].a_un.a_str, "on")) == 0) {
560 576 elswitch = TRUE;
561 577 } else if ((strcasecmp(argv[0].a_un.a_str, "off")) == 0) {
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562 578 elswitch = FALSE;
563 579 } else {
564 580 return (DCMD_USAGE);
565 581 }
566 582
567 583 if (mdb_readvar(&ql_hba, "ql_hba") == -1) {
568 584 mdb_warn("failed to read ql_hba structure");
569 585 return (DCMD_ERR);
570 586 }
571 587
572 - if (&ql_hba == NULL) {
588 + if (ql_hba.first == NULL) {
573 589 mdb_warn("failed to read ql_hba structure - is qlc loaded?");
574 590 return (DCMD_ERR);
575 591 }
576 592
577 593 if ((qlstate = (ql_adapter_state_t *)mdb_alloc(qlsize,
578 594 UM_SLEEP)) == NULL) {
579 595 mdb_warn("Unable to allocate memory for "
580 596 "ql_adapter_state\n");
581 597 return (DCMD_OK);
582 598 }
583 599
584 600 if ((strcasecmp(argv[1].a_un.a_str, "all")) == 0) {
585 601
586 602 if (argc != 2) {
587 603 mdb_free(qlstate, qlsize);
588 604 return (DCMD_USAGE);
589 605 }
590 606
591 607 hbaptr = (uintptr_t)ql_hba.first;
592 608
593 609 while (hbaptr != NULL) {
594 610
595 611 if (mdb_vread(qlstate, qlsize, hbaptr) == -1) {
596 612 mdb_free(qlstate, qlsize);
597 613 mdb_warn("failed to read ql_adapter_state "
598 614 "at %p", hbaptr);
599 615 return (DCMD_OK);
600 616 }
601 617
602 618 ql_elog_common(qlstate, elswitch);
603 619
604 620 hbaptr = (uintptr_t)qlstate->hba.next;
605 621 }
606 622 } else {
607 623 for (argcnt = 1; argcnt < argc; argcnt++) {
608 624
609 625 instance = (uint32_t)mdb_strtoull(
610 626 argv[argcnt].a_un.a_str);
611 627
612 628 /* find the correct instance to change */
613 629 hbaptr = (uintptr_t)ql_hba.first;
614 630 while (hbaptr != NULL) {
615 631
616 632 if (mdb_vread(qlstate, qlsize, hbaptr) == -1) {
617 633 mdb_free(qlstate, qlsize);
618 634 mdb_warn("failed to read "
619 635 "ql_adapter_state at %p", hbaptr);
620 636 return (DCMD_OK);
621 637 }
622 638
623 639 if (qlstate->instance == instance) {
624 640 break;
625 641 }
626 642
627 643 hbaptr = (uintptr_t)qlstate->hba.next;
628 644 }
629 645
630 646 if (hbaptr == NULL) {
631 647 mdb_printf("instance %d is not loaded",
632 648 instance);
633 649 continue;
634 650 }
635 651
636 652 ql_elog_common(qlstate, elswitch);
637 653 }
638 654 }
639 655
640 656 mdb_free(qlstate, qlsize);
641 657
642 658 return (DCMD_OK);
643 659 }
644 660
645 661 /*
646 662 * qlc_elog_common
647 663 * mdb helper function which set/resets the extended logging bit
648 664 *
649 665 * Input:
650 666 * qlstate = adapter state structure
651 667 * elswitch = boolean which specifies to reset (0) or set (1) the
652 668 * extended logging bit.
653 669 *
654 670 * Returns:
655 671 *
656 672 * Context:
657 673 * User context.
658 674 *
659 675 */
660 676 static void
661 677 ql_elog_common(ql_adapter_state_t *qlstate, boolean_t elswitch)
662 678 {
663 679 uintptr_t hbaptr = (uintptr_t)qlstate->hba.base_address;
664 680 size_t qlsize = sizeof (ql_adapter_state_t);
665 681
666 682 if (elswitch) {
667 683 if ((qlstate->cfg_flags & CFG_ENABLE_EXTENDED_LOGGING) == 0) {
668 684
669 685 qlstate->cfg_flags |= CFG_ENABLE_EXTENDED_LOGGING;
670 686
671 687 if ((mdb_vwrite((const void *)qlstate, qlsize,
672 688 hbaptr)) != (ssize_t)qlsize) {
673 689 mdb_warn("instance %d - unable to update",
674 690 qlstate->instance);
675 691 } else {
676 692 mdb_printf("instance %d extended logging is "
677 693 "now on\n", qlstate->instance);
678 694 }
679 695 } else {
680 696 mdb_printf("instance %d extended logging is "
681 697 "already on\n", qlstate->instance);
682 698 }
683 699 } else {
684 700 if ((qlstate->cfg_flags & CFG_ENABLE_EXTENDED_LOGGING) != 0) {
685 701
686 702 qlstate->cfg_flags &= ~CFG_ENABLE_EXTENDED_LOGGING;
687 703
688 704 if ((mdb_vwrite((const void *)qlstate, qlsize,
689 705 hbaptr)) != (ssize_t)qlsize) {
690 706 mdb_warn("instance %d - unable to update",
691 707 qlstate->instance);
692 708 } else {
693 709 mdb_printf("instance %d extended logging is "
694 710 "now off\n", qlstate->instance);
695 711 }
696 712 } else {
697 713 mdb_printf("instance %d extended logging is "
698 714 "already off\n", qlstate->instance);
699 715 }
700 716 }
701 717 }
702 718
703 719 /*
704 720 * qlc_ocs_dcmd
705 721 * mdb dcmd which prints out the outstanding command array using
706 722 * caller supplied address (which sb the ha structure).
707 723 *
708 724 * Input:
709 725 * addr = User supplied ha address.
710 726 * flags = mdb flags.
711 727 * argc = Number of user supplied args.
712 728 * argv = Arg array.
713 729 *
714 730 * Returns:
715 731 * DCMD_USAGE, or DCMD_OK
716 732 *
717 733 * Context:
718 734 * User context.
719 735 *
720 736 *
721 737 */
722 738 static int
723 739 /*ARGSUSED*/
724 740 qlc_osc_dcmd(uintptr_t addr, uint_t flags, int argc, const mdb_arg_t *argv)
725 741 {
726 742 ql_adapter_state_t *qlstate;
727 743 uintptr_t qlosc, ptr1;
728 744 uint32_t indx, found = 0;
729 745 ql_srb_t *qlsrb;
730 746
731 747 if (!(flags & DCMD_ADDRSPEC)) {
732 748 return (DCMD_USAGE);
733 749 }
734 750
735 751 if ((qlstate = (ql_adapter_state_t *)
736 752 mdb_alloc(sizeof (ql_adapter_state_t), UM_SLEEP)) == NULL) {
737 753 mdb_warn("Unable to allocate memory for ql_adapter_state\n");
738 754 return (DCMD_OK);
739 755 }
740 756 if (mdb_vread(qlstate, sizeof (ql_adapter_state_t), addr) == -1) {
741 757 mdb_free(qlstate, sizeof (ql_adapter_state_t));
742 758 mdb_warn("failed to read ql_adapter_state at %p", addr);
743 759 return (DCMD_OK);
744 760 }
745 761
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746 762 qlosc = (uintptr_t)qlstate->outstanding_cmds;
747 763 mdb_printf("qlc instance: %d, base addr = %llx, osc base = %p\n",
748 764 qlstate->instance, qlstate->hba.base_address, qlosc);
749 765
750 766 if ((qlsrb = (ql_srb_t *)mdb_alloc(sizeof (ql_srb_t), UM_SLEEP)) ==
751 767 NULL) {
752 768 mdb_free(qlstate, sizeof (ql_adapter_state_t));
753 769 mdb_warn("failed to allocate space for srb_t\n");
754 770 return (DCMD_OK);
755 771 }
756 - for (indx = 0; indx < MAX_OUTSTANDING_COMMANDS; indx++, qlosc += 8) {
772 + for (indx = 0; indx < qlstate->osc_max_cnt; indx++, qlosc += 8) {
757 773 if (mdb_vread(&ptr1, 8, qlosc) == -1) {
758 774 mdb_warn("failed to read ptr1, indx=%d", indx);
759 775 break;
760 776 }
761 777 if (ptr1 == 0) {
762 778 continue;
763 779 }
764 780
765 781 mdb_printf("osc ptr = %p, indx = %xh\n", ptr1, indx);
766 782
767 783 if (mdb_vread(qlsrb, sizeof (ql_srb_t), ptr1) == -1) {
768 784 mdb_warn("failed to read ql_srb_t at %p", ptr1);
769 785 break;
770 786 }
771 787 (void) ql_doprint(ptr1, "struct ql_srb");
772 788 found++;
773 789 }
774 790
775 791 mdb_free(qlsrb, sizeof (ql_srb_t));
776 792 mdb_free(qlstate, sizeof (ql_adapter_state_t));
777 793
778 794 mdb_printf("number of outstanding command srb's is: %d\n", found);
779 795
780 796 return (DCMD_OK);
781 797 }
782 798
783 799 /*
784 800 * qlc_wdog_dcmd
785 801 * mdb dcmd which prints out the commands which are linked
786 802 * on the watchdog linked list. Caller supplied address (which
787 803 * sb the ha structure).
788 804 *
789 805 * Input:
790 806 * addr = User supplied ha address.
791 807 * flags = mdb flags.
792 808 * argc = Number of user supplied args.
793 809 * argv = Arg array.
794 810 *
795 811 * Returns:
796 812 * DCMD_USAGE, or DCMD_OK
797 813 *
798 814 * Context:
799 815 * User context.
800 816 *
801 817 *
802 818 */
803 819 static int
804 820 /*ARGSUSED*/
805 821 qlc_wdog_dcmd(uintptr_t addr, uint_t flags, int argc, const mdb_arg_t *argv)
806 822 {
807 823 ql_adapter_state_t *qlstate;
808 824 uint16_t index, count;
809 825 ql_head_t *dev;
810 826 ql_srb_t *srb;
811 827 ql_tgt_t *tq;
812 828 ql_lun_t *lq;
813 829 ql_link_t *tqlink, *srblink, *lqlink;
814 830 int nextlink;
815 831
816 832 if (!(flags & DCMD_ADDRSPEC)) {
817 833 mdb_warn("Address required\n", addr);
818 834 return (DCMD_USAGE);
819 835 }
820 836
821 837 if ((qlstate = (ql_adapter_state_t *)
822 838 mdb_alloc(sizeof (ql_adapter_state_t), UM_SLEEP)) == NULL) {
823 839 mdb_warn("Unable to allocate memory for ql_adapter_state\n");
824 840 return (DCMD_OK);
825 841 }
826 842
827 843 if (mdb_vread(qlstate, sizeof (ql_adapter_state_t), addr) == -1) {
828 844 mdb_free(qlstate, sizeof (ql_adapter_state_t));
829 845 mdb_warn("failed to read ql_adapter_state at %p", addr);
830 846 return (DCMD_OK);
831 847 }
832 848
833 849 /*
834 850 * Read in the device array
835 851 */
836 852 dev = (ql_head_t *)
837 853 mdb_alloc(sizeof (ql_head_t) * DEVICE_HEAD_LIST_SIZE, UM_SLEEP);
838 854
839 855 if (mdb_vread(dev, sizeof (ql_head_t) * DEVICE_HEAD_LIST_SIZE,
840 856 (uintptr_t)qlstate->dev) == -1) {
841 857 mdb_warn("failed to read ql_head_t (dev) at %p", qlstate->dev);
842 858 mdb_free(qlstate, sizeof (ql_adapter_state_t));
843 859 mdb_free(dev, sizeof (ql_head_t) * DEVICE_HEAD_LIST_SIZE);
844 860 return (DCMD_OK);
845 861 }
846 862
847 863 tqlink = (ql_link_t *)mdb_alloc(sizeof (ql_link_t), UM_SLEEP);
848 864 tq = (ql_tgt_t *)mdb_alloc(sizeof (ql_tgt_t), UM_SLEEP);
849 865 lqlink = (ql_link_t *)mdb_alloc(sizeof (ql_link_t), UM_SLEEP);
850 866 lq = (ql_lun_t *)mdb_alloc(sizeof (ql_lun_t), UM_SLEEP);
851 867 srblink = (ql_link_t *)mdb_alloc(sizeof (ql_link_t), UM_SLEEP);
852 868 srb = (ql_srb_t *)mdb_alloc(sizeof (ql_srb_t), UM_SLEEP);
853 869
854 870 /*
855 871 * Validate the devices watchdog queue
856 872 */
857 873 for (index = 0; index < DEVICE_HEAD_LIST_SIZE; index++) {
858 874
859 875 /* Skip empty ones */
860 876 if (dev[index].first == NULL) {
861 877 continue;
862 878 }
863 879
864 880 mdb_printf("dev array index = %x\n", index);
865 881
866 882 /* Loop through targets on device linked list */
867 883 /* get the first link */
868 884
869 885 nextlink = get_first_link(&dev[index], tqlink);
870 886
871 887 /*
872 888 * traverse the targets linked list at this device array index.
873 889 */
874 890 while (nextlink == DCMD_OK) {
875 891 /* Get the target */
876 892 if (mdb_vread(tq, sizeof (ql_tgt_t),
877 893 (uintptr_t)(tqlink->base_address)) == -1) {
878 894 mdb_warn("failed to read ql_tgt at %p",
879 895 tqlink->base_address);
880 896 break;
881 897 }
882 898 mdb_printf("tgt q base = %llx, ",
883 899 tqlink->base_address);
884 900
885 901 mdb_printf("flags: (%xh)", tq->flags);
886 902
887 903 if (tq->flags) {
888 904 ql_dump_flags((uint64_t)tq->flags, qltgt_flags);
889 905 }
890 906
891 907 mdb_printf("tgt: %02x%02x%02x%02x%02x%02x%02x%02x ",
892 908 tq->node_name[0], tq->node_name[1],
893 909 tq->node_name[2], tq->node_name[3],
894 910 tq->node_name[4], tq->node_name[5],
895 911 tq->node_name[6], tq->node_name[7]);
896 912
897 913 /*
898 914 * Loop through commands on this targets watchdog queue.
899 915 */
900 916
901 917 /* Get the first link on the targets cmd wdg q. */
902 918 if (tq->wdg.first == NULL) {
903 919 mdb_printf(" watchdog list empty ");
904 920 break;
905 921 } else {
906 922 if (mdb_vread(srblink, sizeof (ql_link_t),
907 923 (uintptr_t)tq->wdg.first) == -1) {
908 924 mdb_warn("failed to read ql_link_t"
909 925 " at %p", tq->wdg.first);
910 926 break;
911 927 }
912 928 /* There is aleast one. */
913 929 count = 1;
914 930 /*
915 931 * Count the remaining items in the
916 932 * cmd watchdog list.
917 933 */
918 934 while (srblink->next != NULL) {
919 935 /* Read in the next ql_link_t header */
920 936 if (mdb_vread(srblink,
921 937 sizeof (ql_link_t),
922 938 (uintptr_t)srblink->next) == -1) {
923 939 mdb_warn("failed to read"
924 940 " ql_link_t next at %p",
925 941 srblink->next);
926 942 break;
927 943 }
928 944 count = (uint16_t)(count + 1);
929 945 }
930 946 mdb_printf(" watchdog list: %d entries\n",
931 947 count);
932 948 /* get the first one again */
933 949 if (mdb_vread(srblink, sizeof (ql_link_t),
934 950 (uintptr_t)tq->wdg.first) == -1) {
935 951 mdb_warn("failed to read ql_link_t"
936 952 " at %p", tq->wdg.first);
937 953 break;
938 954 }
939 955 }
940 956 /*
941 957 * Traverse the targets cmd watchdog linked list
942 958 * verifying srb's from the list are on a lun cmd list.
943 959 */
944 960 while (nextlink == DCMD_OK) {
945 961 int found = 0;
946 962 /* get the srb */
947 963 if (mdb_vread(srb, sizeof (ql_srb_t),
948 964 (uintptr_t)srblink->base_address) == -1) {
949 965 mdb_warn("failed to read ql_srb_t"
950 966 " at %p", srblink->base_address);
951 967 break;
952 968 }
953 969 mdb_printf("ql_srb %llx ",
954 970 srblink->base_address);
955 971
956 972 /*
957 973 * Get the lun q the srb is on
958 974 */
959 975 if (mdb_vread(lq, sizeof (ql_lun_t),
960 976 (uintptr_t)srb->lun_queue) == -1) {
961 977 mdb_warn("failed to read ql_srb_t"
962 978 " at %p", srb->lun_queue);
963 979 break;
964 980 }
965 981 nextlink = get_first_link(&lq->cmd, lqlink);
966 982 /*
967 983 * traverse the lun cmd linked list looking
968 984 * for the srb from the targets watchdog list
969 985 */
970 986 while (nextlink == DCMD_OK) {
971 987 if (srblink->base_address ==
972 988 lqlink->base_address) {
973 989 mdb_printf("on lun %d cmd q\n",
974 990 lq->lun_no);
975 991 found = 1;
976 992 break;
977 993 }
978 994 /* get next item on lun cmd list */
979 995 nextlink = get_next_link(lqlink);
980 996 }
981 997 if (!found) {
982 998 mdb_printf("not found on lun cmd q\n");
983 999 }
984 1000 /* get next item in the watchdog list */
985 1001 nextlink = get_next_link(srblink);
986 1002 } /* End targets command watchdog list */
987 1003 /* get next item in this target list */
988 1004 nextlink = get_next_link(tqlink);
989 1005 } /* End traverse the device targets linked list */
990 1006 mdb_printf("\n");
991 1007 } /* End device array */
992 1008
993 1009 mdb_free(tq, sizeof (ql_tgt_t));
994 1010 mdb_free(lq, sizeof (ql_lun_t));
995 1011 mdb_free(srb, sizeof (ql_srb_t));
996 1012 mdb_free(tqlink, sizeof (ql_link_t));
997 1013 mdb_free(srblink, sizeof (ql_link_t));
998 1014 mdb_free(lqlink, sizeof (ql_link_t));
999 1015 mdb_free(qlstate, sizeof (ql_adapter_state_t));
1000 1016 mdb_free(dev, sizeof (ql_head_t)*DEVICE_HEAD_LIST_SIZE);
1001 1017
1002 1018 return (DCMD_OK);
1003 1019 }
1004 1020
1005 1021 /*
1006 1022 * get_first_link
1007 1023 * Gets the first ql_link_t header on ql_head.
1008 1024 *
1009 1025 * Input:
1010 1026 * ql_head = pointer to a ql_head_t structure.
1011 1027 * ql_link = pointer to a ql_link_t structure.
1012 1028 *
1013 1029 * Returns:
1014 1030 * DCMD_ABORT, or DCMD_OK
1015 1031 *
1016 1032 * Context:
1017 1033 * User context.
1018 1034 *
1019 1035 */
1020 1036 static int
1021 1037 get_first_link(ql_head_t *qlhead, ql_link_t *qllink)
1022 1038 {
1023 1039 int rval = DCMD_ABORT;
1024 1040
1025 1041 if (qlhead != NULL) {
1026 1042 if (qlhead->first != NULL) {
1027 1043 /* Read in the first ql_link_t header */
1028 1044 if (mdb_vread(qllink, sizeof (ql_link_t),
1029 1045 (uintptr_t)(qlhead->first)) == -1) {
1030 1046 mdb_warn("failed to read ql_link_t "
1031 1047 "next at %p", qlhead->first);
1032 1048 } else {
1033 1049 rval = DCMD_OK;
1034 1050 }
1035 1051 }
1036 1052 }
1037 1053 return (rval);
1038 1054 }
1039 1055
1040 1056 /*
1041 1057 * get_next_link
1042 1058 * Gets the next ql_link_t structure.
1043 1059 *
1044 1060 * Input:
1045 1061 * ql_link = pointer to a ql_link_t structure.
1046 1062 *
1047 1063 * Returns:
1048 1064 * DCMD_ABORT, or DCMD_OK
1049 1065 *
1050 1066 * Context:
1051 1067 * User context.
1052 1068 *
1053 1069 */
1054 1070 static int
1055 1071 get_next_link(ql_link_t *qllink)
1056 1072 {
1057 1073 int rval = DCMD_ABORT;
1058 1074
1059 1075 if (qllink != NULL) {
1060 1076 if (qllink->next != NULL) {
1061 1077 /* Read in the next ql_link_t header */
1062 1078 if (mdb_vread(qllink, sizeof (ql_link_t),
1063 1079 (uintptr_t)(qllink->next)) == -1) {
1064 1080 mdb_warn("failed to read ql_link_t "
1065 1081 "next at %p", qllink->next);
1066 1082 } else {
1067 1083 rval = DCMD_OK;
1068 1084 }
1069 1085 }
1070 1086 }
1071 1087 return (rval);
1072 1088 }
1073 1089
1074 1090 /*
1075 1091 * qlcstate_dcmd
1076 1092 * mdb dcmd which prints out the ql_state info using
1077 1093 * caller supplied address.
1078 1094 *
1079 1095 * Input:
1080 1096 * addr = User supplied address.
1081 1097 * flags = mdb flags.
1082 1098 * argc = Number of user supplied args.
1083 1099 * argv = Arg array.
1084 1100 *
1085 1101 * Returns:
1086 1102 * DCMD_USAGE, or DCMD_OK
1087 1103 *
1088 1104 * Context:
1089 1105 * User context.
1090 1106 *
1091 1107 */
1092 1108 static int
1093 1109 qlcstate_dcmd(uintptr_t addr, uint_t flags, int argc, const mdb_arg_t *argv)
1094 1110 {
1095 1111 ql_adapter_state_t *qlstate;
1096 1112 int verbose = 0;
1097 1113
1098 1114 if (!(flags & DCMD_ADDRSPEC)) {
1099 1115 return (DCMD_USAGE);
1100 1116 }
1101 1117
1102 1118 if (mdb_getopts(argc, argv, 'v', MDB_OPT_SETBITS, TRUE, &verbose) !=
1103 1119 argc) {
1104 1120 return (DCMD_USAGE);
1105 1121 }
1106 1122
1107 1123 if ((qlstate = (ql_adapter_state_t *)
1108 1124 mdb_alloc(sizeof (ql_adapter_state_t), UM_SLEEP)) == NULL) {
1109 1125 mdb_warn("failed to allocate memory for ql_adapter_state\n");
1110 1126 return (DCMD_OK);
1111 1127 }
1112 1128 if (mdb_vread(qlstate, sizeof (ql_adapter_state_t), addr) == -1) {
1113 1129 mdb_free(qlstate, sizeof (ql_adapter_state_t));
1114 1130 mdb_warn("failed to read ql_adapter_state at %p", addr);
1115 1131 return (DCMD_OK);
1116 1132 }
1117 1133
1118 1134 mdb_printf("qlc instance: %d, base addr = %llx\n", qlstate->instance,
1119 1135 addr);
1120 1136
1121 1137 mdb_printf("\nadapter state flags:\n");
1122 1138 ql_dump_flags((uint64_t)qlstate->flags, adapter_state_flags);
1123 1139 mdb_printf("\nadapter cfg flags:\n");
1124 1140 ql_dump_flags((uint64_t)qlstate->cfg_flags, adapter_config_flags);
1125 1141 mdb_printf("\ntask daemon state flags:\n");
1126 1142 ql_dump_flags((uint64_t)qlstate->task_daemon_flags,
1127 1143 task_daemon_flags);
1128 1144
1129 1145 if (verbose) {
1130 1146 (void) ql_doprint(addr, "struct ql_adapter_state");
1131 1147 }
1132 1148
1133 1149 mdb_free(qlstate, sizeof (ql_adapter_state_t));
1134 1150
1135 1151 return (DCMD_OK);
1136 1152 }
1137 1153
1138 1154 /*
1139 1155 * qlcstates_walk_init
1140 1156 * mdb walker init which prints out all qlc states info.
1141 1157 *
1142 1158 * Input:
1143 1159 * wsp - Pointer to walker state struct
1144 1160 *
1145 1161 * Returns:
1146 1162 * WALK_ERR, or WALK_NEXT
1147 1163 *
1148 1164 * Context:
1149 1165 * User context.
1150 1166 *
1151 1167 */
1152 1168 static int
1153 1169 qlstates_walk_init(mdb_walk_state_t *wsp)
1154 1170 {
1155 1171 ql_head_t ql_hba;
1156 1172
1157 1173 if (wsp->walk_addr == NULL) {
1158 1174 if ((mdb_readvar(&ql_hba, "ql_hba") == -1) ||
1159 1175 (&ql_hba == NULL)) {
1160 1176 mdb_warn("failed to read ql_hba structure");
1161 1177 return (WALK_ERR);
1162 1178 }
1163 1179
1164 1180 wsp->walk_addr = (uintptr_t)ql_hba.first;
1165 1181 wsp->walk_data = mdb_alloc(sizeof (ql_adapter_state_t),
1166 1182 UM_SLEEP);
1167 1183 return (WALK_NEXT);
1168 1184 } else {
1169 1185 return (ql_doprint(wsp->walk_addr, "struct ql_adapter_state"));
1170 1186 }
1171 1187 }
1172 1188
1173 1189 /*
1174 1190 * qlstates_walk_step
1175 1191 * mdb walker step which prints out all qlc states info.
1176 1192 *
1177 1193 * Input:
1178 1194 * wsp - Pointer to walker state struct
1179 1195 *
1180 1196 * Returns:
1181 1197 * WALK_DONE, or WALK_NEXT
1182 1198 *
1183 1199 * Context:
1184 1200 * User context.
1185 1201 *
1186 1202 */
1187 1203 static int
1188 1204 qlstates_walk_step(mdb_walk_state_t *wsp)
1189 1205 {
1190 1206 ql_adapter_state_t *qlstate;
1191 1207
1192 1208 if (wsp->walk_addr == NULL) {
1193 1209 return (WALK_DONE);
1194 1210 }
1195 1211
1196 1212 if (mdb_vread(wsp->walk_data, sizeof (ql_adapter_state_t),
1197 1213 wsp->walk_addr) == -1) {
1198 1214 mdb_warn("failed to read ql_adapter_state at %p",
1199 1215 wsp->walk_addr);
1200 1216 return (WALK_DONE);
1201 1217 }
1202 1218
1203 1219 qlstate = (ql_adapter_state_t *)(wsp->walk_data);
1204 1220 mdb_printf("qlc instance: %d, base addr = %llx\n",
1205 1221 qlstate->instance, wsp->walk_addr);
1206 1222
1207 1223 mdb_printf("\nadapter state flags:\n");
1208 1224 ql_dump_flags((uint64_t)qlstate->flags, adapter_state_flags);
1209 1225 mdb_printf("\nadapter cfg flags:\n");
1210 1226 ql_dump_flags((uint64_t)qlstate->cfg_flags, adapter_config_flags);
1211 1227 mdb_printf("\ntask daemon state flags:\n");
1212 1228 ql_dump_flags((uint64_t)qlstate->task_daemon_flags,
1213 1229 task_daemon_flags);
1214 1230
1215 1231 mdb_printf("\nadapter state:\n");
1216 1232 (void) ql_doprint(wsp->walk_addr, "struct ql_adapter_state");
1217 1233
1218 1234 mdb_printf("\n");
1219 1235
1220 1236 wsp->walk_addr = (uintptr_t)
1221 1237 (((ql_adapter_state_t *)wsp->walk_data)->hba.next);
1222 1238
1223 1239 return (WALK_NEXT);
1224 1240 }
1225 1241
1226 1242 /*
1227 1243 * qlstates_walk_fini
1228 1244 * mdb walker fini which wraps up the walker
1229 1245 *
1230 1246 * Input:
1231 1247 * wsp - Pointer to walker state struct
1232 1248 *
1233 1249 * Returns:
1234 1250 *
1235 1251 * Context:
1236 1252 * User context.
1237 1253 *
1238 1254 */
1239 1255 static void
1240 1256 qlstates_walk_fini(mdb_walk_state_t *wsp)
1241 1257 {
1242 1258 mdb_free(wsp->walk_data, sizeof (ql_adapter_state_t));
1243 1259 }
1244 1260
1245 1261 /*
1246 1262 * qlsrb_walk_init
1247 1263 * mdb walker init which prints out linked srb's
1248 1264 *
1249 1265 * Input:
1250 1266 * wsp - Pointer to walker ql_srb struct
1251 1267 *
1252 1268 * Returns:
1253 1269 * WALK_ERR, or WALK_NEXT
1254 1270 *
1255 1271 * Context:
1256 1272 * User context.
1257 1273 *
1258 1274 */
1259 1275 static int
1260 1276 qlsrb_walk_init(mdb_walk_state_t *wsp)
1261 1277 {
1262 1278 if (wsp->walk_addr == NULL) {
1263 1279 mdb_warn("failed to read ql_srb addr at %p",
1264 1280 wsp->walk_addr);
1265 1281 return (WALK_ERR);
1266 1282 }
1267 1283
1268 1284 wsp->walk_data = mdb_alloc(sizeof (ql_srb_t), UM_SLEEP);
1269 1285
1270 1286 return (WALK_NEXT);
1271 1287 }
1272 1288
1273 1289 /*
1274 1290 * qlcsrb_walk_step
1275 1291 * mdb walker step which prints out linked ql_srb structures
1276 1292 *
1277 1293 * Input:
1278 1294 * wsp - Pointer to walker srb struct
1279 1295 *
1280 1296 * Returns:
1281 1297 * WALK_DONE, or WALK_NEXT
1282 1298 *
1283 1299 * Context:
1284 1300 * User context.
1285 1301 *
1286 1302 */
1287 1303 static int
1288 1304 qlsrb_walk_step(mdb_walk_state_t *wsp)
1289 1305 {
1290 1306 ql_srb_t *qlsrb;
1291 1307
1292 1308 if (wsp->walk_addr == NULL)
1293 1309 return (WALK_DONE);
1294 1310
1295 1311 if (mdb_vread(wsp->walk_data, sizeof (ql_srb_t),
1296 1312 wsp->walk_addr) == -1) {
1297 1313 mdb_warn("failed to read ql_srb at %p", wsp->walk_addr);
1298 1314 return (WALK_DONE);
1299 1315 }
1300 1316
1301 1317 qlsrb = (ql_srb_t *)(wsp->walk_data);
1302 1318 mdb_printf("ql_srb base addr = %llx\n", wsp->walk_addr);
1303 1319
1304 1320 mdb_printf("\nql_srb flags:\n");
1305 1321 ql_dump_flags((uint64_t)qlsrb->flags, qlsrb_flags);
1306 1322
1307 1323 mdb_printf("\nql_srb:\n");
1308 1324 (void) ql_doprint(wsp->walk_addr, "struct ql_srb");
1309 1325
1310 1326 mdb_printf("\n");
1311 1327
1312 1328 wsp->walk_addr = (uintptr_t)
1313 1329 (((ql_srb_t *)wsp->walk_data)->cmd.next);
1314 1330
1315 1331 return (WALK_NEXT);
1316 1332 }
1317 1333
1318 1334 /*
1319 1335 * qlsrb_walk_fini
1320 1336 * mdb walker fini which wraps up the walker
1321 1337 *
1322 1338 * Input:
1323 1339 * wsp - Pointer to walker state struct
1324 1340 *
1325 1341 * Returns:
1326 1342 *
1327 1343 * Context:
1328 1344 * User context.
1329 1345 *
1330 1346 */
1331 1347 static void
1332 1348 qlsrb_walk_fini(mdb_walk_state_t *wsp)
1333 1349 {
1334 1350 mdb_free(wsp->walk_data, sizeof (ql_srb_t));
1335 1351 }
1336 1352
1337 1353 /*
1338 1354 * qllunq_dcmd
1339 1355 * mdb walker which prints out lun q's
1340 1356 *
1341 1357 * Input:
1342 1358 * wsp - Pointer to walker ql_lun struct
1343 1359 *
1344 1360 * Returns:
1345 1361 * WALK_ERR, or WALK_NEXT
1346 1362 *
1347 1363 * Context:
1348 1364 * User context.
1349 1365 *
1350 1366 */
1351 1367 static int
1352 1368 qllunq_walk_init(mdb_walk_state_t *wsp)
1353 1369 {
1354 1370 if (wsp->walk_addr == NULL) {
1355 1371 mdb_warn("failed to read ql_lun addr at %p",
1356 1372 wsp->walk_addr);
1357 1373 return (WALK_ERR);
1358 1374 }
1359 1375
1360 1376 wsp->walk_data = mdb_alloc(sizeof (ql_lun_t), UM_SLEEP);
1361 1377
1362 1378 return (WALK_NEXT);
1363 1379 }
1364 1380
1365 1381 /*
1366 1382 * qlclunq_walk_step
1367 1383 * mdb walker step which prints out linked ql_lun structures
1368 1384 *
1369 1385 * Input:
1370 1386 * wsp - Pointer to walker srb struct
1371 1387 *
1372 1388 * Returns:
1373 1389 * WALK_DONE, or WALK_NEXT
1374 1390 *
1375 1391 * Context:
1376 1392 * User context.
1377 1393 *
1378 1394 */
1379 1395 static int
1380 1396 qllunq_walk_step(mdb_walk_state_t *wsp)
1381 1397 {
1382 1398 ql_lun_t *qllun;
1383 1399 ql_link_t ql_link;
1384 1400 ql_link_t *qllink;
1385 1401
1386 1402 if (wsp->walk_addr == NULL)
1387 1403 return (WALK_DONE);
1388 1404
1389 1405 if (mdb_vread(wsp->walk_data, sizeof (ql_lun_t),
1390 1406 wsp->walk_addr) == -1) {
1391 1407 mdb_warn("failed to read ql_lun at %p", wsp->walk_addr);
1392 1408 return (WALK_DONE);
1393 1409 }
1394 1410
1395 1411 qllun = (ql_lun_t *)(wsp->walk_data);
1396 1412 mdb_printf("ql_lun base addr = %llx\n", wsp->walk_addr);
1397 1413
1398 1414 mdb_printf("\nql_lun flags:\n");
1399 1415 ql_dump_flags((uint64_t)qllun->flags, qllun_flags);
1400 1416
1401 1417 mdb_printf("\nql_lun:\n");
1402 1418 (void) ql_doprint(wsp->walk_addr, "struct ql_lun");
1403 1419
1404 1420 mdb_printf("\n");
1405 1421
1406 1422 qllink = (ql_link_t *)
1407 1423 (((ql_lun_t *)wsp->walk_data)->link.next);
1408 1424
1409 1425 if (qllink == NULL) {
1410 1426 return (WALK_DONE);
1411 1427 } else {
1412 1428 /*
1413 1429 * Read in the next link_t header
1414 1430 */
1415 1431 if (mdb_vread(&ql_link, sizeof (ql_link_t),
1416 1432 (uintptr_t)qllink) == -1) {
1417 1433 mdb_warn("failed to read ql_link_t "
1418 1434 "next at %p", qllink->next);
1419 1435 return (WALK_DONE);
1420 1436 }
1421 1437 qllink = &ql_link;
1422 1438 }
1423 1439
1424 1440 wsp->walk_addr = (uintptr_t)qllink->base_address;
1425 1441
1426 1442 return (WALK_NEXT);
1427 1443 }
1428 1444
1429 1445 /*
1430 1446 * qllunq_walk_fini
1431 1447 * mdb walker fini which wraps up the walker
1432 1448 *
1433 1449 * Input:
1434 1450 * wsp - Pointer to walker state struct
1435 1451 *
1436 1452 * Returns:
1437 1453 *
1438 1454 * Context:
1439 1455 * User context.
1440 1456 *
1441 1457 */
1442 1458 static void
1443 1459 qllunq_walk_fini(mdb_walk_state_t *wsp)
1444 1460 {
1445 1461 mdb_free(wsp->walk_data, sizeof (ql_lun_t));
1446 1462 }
1447 1463
1448 1464 /*
1449 1465 * qltgtq_dcmd
1450 1466 * mdb dcmd which prints out an hs's tq struct info.
1451 1467 *
1452 1468 * Input:
1453 1469 * addr = User supplied address. (NB: nust be an ha)
1454 1470 * flags = mdb flags.
1455 1471 * argc = Number of user supplied args.
1456 1472 * argv = Arg array.
1457 1473 *
1458 1474 * Returns:
1459 1475 * DCMD_USAGE, or DCMD_OK
1460 1476 *
1461 1477 * Context:
1462 1478 * User context.
1463 1479 *
1464 1480 */
1465 1481 /*ARGSUSED*/
1466 1482 static int
1467 1483 qltgtq_dcmd(uintptr_t addr, uint_t flags, int argc, const mdb_arg_t *argv)
1468 1484 {
1469 1485 ql_adapter_state_t *ha;
1470 1486 ql_link_t *link;
1471 1487 ql_tgt_t *tq;
1472 1488 uint32_t index;
1473 1489 ql_head_t *dev;
1474 1490
1475 1491 if ((!(flags & DCMD_ADDRSPEC)) || addr == NULL) {
1476 1492 mdb_warn("ql_hba structure addr is required");
1477 1493 return (DCMD_USAGE);
1478 1494 }
1479 1495
1480 1496 /*
1481 1497 * Get the adapter state struct which was passed
1482 1498 */
1483 1499
1484 1500 ha = (ql_adapter_state_t *)mdb_alloc(sizeof (ql_adapter_state_t),
1485 1501 UM_SLEEP);
1486 1502
1487 1503 if (mdb_vread(ha, sizeof (ql_adapter_state_t), addr) == -1) {
1488 1504 mdb_warn("failed to read ql_adapter_state at %p", addr);
1489 1505 mdb_free(ha, sizeof (ql_adapter_state_t));
1490 1506 return (DCMD_OK);
1491 1507 }
1492 1508
1493 1509 if (ha->dev == NULL) {
1494 1510 mdb_warn("dev ptr is NULL for ha: %p", addr);
1495 1511 mdb_free(ha, sizeof (ql_adapter_state_t));
1496 1512 return (DCMD_OK);
1497 1513 }
1498 1514
1499 1515 /*
1500 1516 * Read in the device array
1501 1517 */
1502 1518 dev = (ql_head_t *)
1503 1519 mdb_alloc(sizeof (ql_head_t) * DEVICE_HEAD_LIST_SIZE, UM_SLEEP);
1504 1520
1505 1521 if (mdb_vread(dev, sizeof (ql_head_t) * DEVICE_HEAD_LIST_SIZE,
1506 1522 (uintptr_t)ha->dev) == -1) {
1507 1523 mdb_warn("failed to read ql_head_t (dev) at %p", ha->dev);
1508 1524 mdb_free(ha, sizeof (ql_adapter_state_t));
1509 1525 mdb_free(dev, sizeof (ql_head_t) * DEVICE_HEAD_LIST_SIZE);
1510 1526 }
1511 1527
1512 1528 tq = (ql_tgt_t *)mdb_alloc(sizeof (ql_tgt_t), UM_SLEEP);
1513 1529 link = (ql_link_t *)mdb_alloc(sizeof (ql_link_t), UM_SLEEP);
1514 1530
1515 1531 for (index = 0; index < DEVICE_HEAD_LIST_SIZE; index++) {
1516 1532
1517 1533 if (dev[index].first == NULL) {
1518 1534 continue;
1519 1535 }
1520 1536
1521 1537 if (mdb_vread(link, sizeof (ql_link_t),
1522 1538 (uintptr_t)dev[index].first) == -1) {
1523 1539 mdb_warn("failed to read ql_link_t at %p",
1524 1540 dev[index].first);
1525 1541 break;
1526 1542 }
1527 1543
1528 1544 while (link != NULL) {
1529 1545 if (mdb_vread(tq, sizeof (ql_tgt_t),
1530 1546 (uintptr_t)(link->base_address)) == -1) {
1531 1547 mdb_warn("failed to read ql_tgt at %p",
1532 1548 link->base_address);
1533 1549 break;
1534 1550 }
1535 1551
1536 1552 mdb_printf("tgt queue base addr = %llx\n",
1537 1553 link->base_address);
1538 1554
1539 1555 mdb_printf("\ntgt queue flags: (%xh)\n", tq->flags);
1540 1556 ql_dump_flags((uint64_t)tq->flags, qltgt_flags);
1541 1557
1542 1558 mdb_printf("\ntgt queue:\n");
1543 1559
1544 1560 (void) ql_doprint((uintptr_t)link->base_address,
1545 1561 "struct ql_target");
1546 1562
1547 1563 mdb_printf("\n");
1548 1564
1549 1565 if (get_next_link(link) != DCMD_OK) {
1550 1566 break;
1551 1567 }
1552 1568 }
1553 1569 }
1554 1570
1555 1571 mdb_free(ha, sizeof (ql_adapter_state_t));
1556 1572 mdb_free(tq, sizeof (ql_tgt_t));
1557 1573 mdb_free(link, sizeof (ql_link_t));
1558 1574 mdb_free(dev, sizeof (ql_head_t)*DEVICE_HEAD_LIST_SIZE);
1559 1575
1560 1576 return (DCMD_OK);
1561 1577 }
1562 1578
1563 1579 /*
1564 1580 * ql_triggerdump_dcmd
1565 1581 * Triggers the driver to take a firmware dump
1566 1582 *
1567 1583 * Input:
1568 1584 * addr = User supplied address (optional)
1569 1585 * flags = mdb flags.
1570 1586 * argc = Number of user supplied args.
1571 1587 * argv = Arg array (instance #, optional).
1572 1588 *
1573 1589 * Returns:
1574 1590 * DCMD_OK or DCMD_ERR
1575 1591 *
1576 1592 * Context:
1577 1593 * User context.
1578 1594 *
1579 1595 */
1580 1596
1581 1597 #if 0
1582 1598
1583 1599 /*ARGSUSED*/
1584 1600 static int
1585 1601 qlc_triggerdump_dcmd(uintptr_t addr, uint_t flags, int argc,
1586 1602 const mdb_arg_t *argv)
1587 1603 {
1588 1604 ql_adapter_state_t *qlstate;
1589 1605 uintptr_t hbaptr = NULL;
1590 1606 ql_head_t ql_hba;
1591 1607 uint32_t qlsize = sizeof (ql_adapter_state_t);
1592 1608 int mdbs;
1593 1609
1594 1610 if ((mdbs = mdb_get_state()) == MDB_STATE_DEAD) {
1595 1611 mdb_warn("Cannot change core file data (state=%xh)\n", mdbs);
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1596 1612 return (DCMD_OK);
1597 1613 }
1598 1614
1599 1615 if ((qlstate = (ql_adapter_state_t *)mdb_alloc(qlsize,
1600 1616 UM_SLEEP)) == NULL) {
1601 1617 mdb_warn("Unable to allocate memory for ql_adapter_state\n");
1602 1618 return (DCMD_OK);
1603 1619 }
1604 1620
1605 1621 if (addr == NULL) {
1606 - char *tptr;
1607 1622 uint32_t instance;
1608 1623
1609 1624 if (argc == 0) {
1610 1625 mdb_warn("must specify either the ha addr or "
1611 1626 "the instance number\n");
1612 1627 mdb_free(qlstate, qlsize);
1613 1628 return (DCMD_OK);
1614 1629 }
1615 1630
1616 1631 /*
1617 1632 * find the specified instance in the ha list
1618 1633 */
1619 1634
1620 - instance = (uint32_t)strtol(argv[1].a_un.a_str, &tptr, 16);
1621 - if (tptr == argv[1].a_un.a_str) {
1622 - mdb_printf("instance # is illegal: '%s'\n",
1623 - argv[1].a_un.a_str);
1624 - mdb_free(qlstate, qlsize);
1625 - return (DCMD_OK);
1626 - }
1635 + instance = (uint32_t)mdb_strtoull(argv[1].a_un.a_str);
1627 1636
1628 1637 if (mdb_readvar(&ql_hba, "ql_hba") == -1) {
1629 1638 mdb_warn("failed to read ql_hba structure");
1630 1639 mdb_free(qlstate, qlsize);
1631 1640 return (DCMD_ERR);
1632 1641 }
1633 1642
1634 1643 if (&ql_hba == NULL) {
1635 1644 mdb_warn("failed to read ql_hba structure - "
1636 1645 "is qlc loaded?");
1637 1646 mdb_free(qlstate, qlsize);
1638 1647 return (DCMD_ERR);
1639 1648 }
1640 1649
1641 1650 hbaptr = (uintptr_t)ql_hba.first;
1642 1651 while (hbaptr != NULL) {
1643 1652
1644 1653 if (mdb_vread(qlstate, qlsize, hbaptr) == -1) {
1645 1654 mdb_free(qlstate, qlsize);
1646 1655 mdb_warn("failed to read "
1647 1656 "ql_adapter_state at %p", hbaptr);
1648 1657 return (DCMD_OK);
1649 1658 }
1650 1659
1651 1660 if (qlstate->instance == instance) {
1652 1661 break;
1653 1662 }
1654 1663
1655 1664 hbaptr = (uintptr_t)qlstate->hba.next;
1656 1665 }
1657 1666 } else {
1658 1667
1659 1668 /*
1660 1669 * verify the addr specified
1661 1670 */
1662 1671
1663 1672 if (mdb_readvar(&ql_hba, "ql_hba") == -1) {
1664 1673 mdb_warn("failed to read ql_hba structure");
1665 1674 mdb_free(qlstate, qlsize);
1666 1675 return (DCMD_ERR);
1667 1676 }
1668 1677
1669 1678 if (&ql_hba == NULL) {
1670 1679 mdb_warn("failed to read ql_hba structure - "
1671 1680 "is qlc loaded?");
1672 1681 mdb_free(qlstate, qlsize);
1673 1682 return (DCMD_ERR);
1674 1683 }
1675 1684
1676 1685 hbaptr = (uintptr_t)ql_hba.first;
1677 1686 while (hbaptr != NULL) {
1678 1687
1679 1688 if (mdb_vread(qlstate, qlsize, hbaptr) == -1) {
1680 1689 mdb_free(qlstate, qlsize);
1681 1690 mdb_warn("failed to read "
1682 1691 "ql_adapter_state at %p", hbaptr);
1683 1692 return (DCMD_OK);
1684 1693 }
1685 1694
1686 1695 if (hbaptr == addr) {
1687 1696 break;
1688 1697 }
1689 1698
1690 1699 hbaptr = (uintptr_t)qlstate->hba.next;
1691 1700 }
1692 1701 }
1693 1702
1694 1703 if (hbaptr == NULL) {
1695 1704 mdb_free(qlstate, qlsize);
1696 1705 if (argc == 0) {
1697 1706 mdb_warn("addr specified is not in the hba list\n");
1698 1707 } else {
1699 1708 mdb_warn("instance specified does not exist\n");
1700 1709 }
1701 1710 return (DCMD_OK);
1702 1711 }
1703 1712
1704 1713 if (((qlstate->ql_dump_state & QL_DUMP_VALID) != 0) ||
1705 1714 (qlstate->ql_dump_ptr != NULL)) {
1706 1715 mdb_warn("instance %d already has a valid dump\n",
1707 1716 qlstate->instance);
1708 1717 mdb_free(qlstate, qlsize);
1709 1718 return (DCMD_OK);
1710 1719 }
1711 1720 }
1712 1721 #endif
1713 1722
1714 1723 /*
1715 1724 * ql_getdump_dcmd
1716 1725 * prints out the firmware dump buffer
1717 1726 *
1718 1727 * Input:
1719 1728 * addr = User supplied address. (NB: must be an ha)
1720 1729 * flags = mdb flags.
1721 1730 * argc = Number of user supplied args.
1722 1731 * argv = Arg array.
1723 1732 *
1724 1733 * Returns:
1725 1734 * DCMD_OK or DCMD_ERR
1726 1735 *
1727 1736 * Context:
1728 1737 * User context.
1729 1738 *
1730 1739 */
1731 1740 static int
1732 1741 qlc_getdump_dcmd(uintptr_t addr, uint_t flags, int argc, const mdb_arg_t *argv)
1733 1742 {
1734 1743 ql_adapter_state_t *ha;
1735 1744 ql_head_t ql_hba;
1736 1745 uintptr_t hbaptr = NULL;
1737 1746 int verbose = 0;
1738 1747
1739 1748 if ((!(flags & DCMD_ADDRSPEC)) || addr == NULL) {
1740 1749 mdb_warn("ql_adapter_state structure addr is required");
1741 1750 return (DCMD_USAGE);
1742 1751 }
1743 1752
1744 1753 if (mdb_getopts(argc, argv, 'v', MDB_OPT_SETBITS, TRUE, &verbose) !=
1745 1754 argc) {
1746 1755 return (DCMD_USAGE);
1747 1756 }
1748 1757
1749 1758 /*
1750 1759 * Get the adapter state struct which was passed
1751 1760 */
1752 1761 if ((ha = (ql_adapter_state_t *)mdb_alloc(sizeof (ql_adapter_state_t),
1753 1762 UM_SLEEP)) == NULL) {
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1754 1763 mdb_warn("failed to allocate memory for ql_adapter_state\n");
1755 1764 return (DCMD_OK);
1756 1765 }
1757 1766
1758 1767 /*
1759 1768 * show user which instances have valid f/w dumps available if
1760 1769 * user has specified verbose option
1761 1770 */
1762 1771 if (mdb_readvar(&ql_hba, "ql_hba") == -1) {
1763 1772 mdb_warn("failed to read ql_hba structure");
1764 - } else if (&ql_hba == NULL) {
1773 + } else if (ql_hba.first == NULL) {
1765 1774 mdb_warn("failed to read ql_hba structure -- is qlc loaded?");
1766 1775 } else if (verbose) {
1767 1776 hbaptr = (uintptr_t)ql_hba.first;
1768 1777 while (hbaptr != NULL) {
1769 1778
1770 1779 if (mdb_vread(ha, sizeof (ql_adapter_state_t),
1771 1780 hbaptr) == -1) {
1772 1781 mdb_free(ha, sizeof (ql_adapter_state_t));
1773 1782 mdb_warn("failed read ql_adapter_state at %p",
1774 1783 hbaptr);
1775 1784 return (DCMD_OK);
1776 1785 }
1777 1786
1778 1787 mdb_printf("instance %d:\n", ha->instance);
1779 1788 (void) mdb_inc_indent((ulong_t)4);
1780 1789
1781 1790 if (ha->ql_dump_state == 0) {
1782 1791 mdb_printf("no dump flags\n");
1783 1792 } else {
1784 1793 ql_dump_flags((uint64_t)ha->ql_dump_state,
1785 1794 qldump_flags);
1786 1795 }
1787 1796
1788 1797 if (ha->ql_dump_ptr == NULL) {
1789 1798 mdb_printf("no dump address\n");
1790 1799 } else {
1791 1800 mdb_printf("dump address is: %p\n",
1792 1801 ha->ql_dump_ptr);
1793 1802 }
1794 1803
1795 1804 (void) mdb_dec_indent((ulong_t)4);
1796 1805
1797 1806 hbaptr = (uintptr_t)ha->hba.next;
1798 1807 }
1799 1808 mdb_printf("\n");
1800 1809 }
1801 1810
1802 1811 if (mdb_vread(ha, sizeof (ql_adapter_state_t), addr) == -1) {
1803 1812 mdb_warn("failed to read ql_adapter_state at %p", addr);
1804 1813 mdb_free(ha, sizeof (ql_adapter_state_t));
1805 1814 return (DCMD_OK);
1806 1815 }
1807 1816
1808 1817 /*
1809 1818 * If its not a valid dump or there's not a f/w dump binary (???)
|
↓ open down ↓ |
35 lines elided |
↑ open up ↑ |
1810 1819 * then bail out
1811 1820 */
1812 1821 if (((ha->ql_dump_state & QL_DUMP_VALID) == 0) ||
1813 1822 (ha->ql_dump_ptr == NULL)) {
1814 1823 mdb_warn("dump does not exist for instance %d (%x, %p)\n",
1815 1824 ha->instance, ha->ql_dump_state, ha->ql_dump_ptr);
1816 1825 mdb_free(ha, sizeof (ql_adapter_state_t));
1817 1826 return (DCMD_OK);
1818 1827 }
1819 1828
1820 - if (CFG_IST(ha, CFG_CTRL_2422)) {
1829 + if (CFG_IST(ha, CFG_CTRL_24XX)) {
1821 1830 (void) ql_24xx_dump_dcmd(ha, flags, argc, argv);
1822 - } else if (CFG_IST(ha, CFG_CTRL_25XX)) {
1831 + } else if (CFG_IST(ha, CFG_CTRL_25XX)) {
1823 1832 (void) ql_25xx_dump_dcmd(ha, flags, argc, argv);
1824 - } else if (CFG_IST(ha, CFG_CTRL_81XX)) {
1833 + } else if (CFG_IST(ha, CFG_CTRL_81XX)) {
1825 1834 (void) ql_81xx_dump_dcmd(ha, flags, argc, argv);
1826 - } else if (!(CFG_IST(ha, CFG_CTRL_8021))) {
1835 + } else if (CFG_IST(ha, CFG_CTRL_82XX | CFG_CTRL_27XX)) {
1836 + (void) ql_8021_dump_dcmd(ha, flags, argc, argv);
1837 + } else if (CFG_IST(ha, CFG_CTRL_83XX)) {
1838 + (void) ql_8300_dump_dcmd(ha, flags, argc, argv);
1839 + } else {
1827 1840 (void) ql_23xx_dump_dcmd(ha, flags, argc, argv);
1828 1841 }
1829 1842
1830 1843 mdb_free(ha, sizeof (ql_adapter_state_t));
1831 1844
1832 1845 return (DCMD_OK);
1833 1846 }
1834 1847
1835 1848 /*
1849 + * ql_8021_dump_dcmd
1850 + * prints out a firmware dump buffer
1851 + *
1852 + * Input:
1853 + * addr = User supplied address. (NB: nust be an ha)
1854 + * flags = mdb flags.
1855 + * argc = Number of user supplied args.
1856 + * argv = Arg array.
1857 + *
1858 + * Returns:
1859 + * DCMD_OK or DCMD_ERR
1860 + *
1861 + * Context:
1862 + * User context.
1863 + *
1864 + */
1865 +/*ARGSUSED*/
1866 +static int
1867 +ql_8021_dump_dcmd(ql_adapter_state_t *ha, uint_t flags, int argc,
1868 + const mdb_arg_t *argv)
1869 +{
1870 + uint8_t *fw, *bp;
1871 + uint32_t cnt = 0;
1872 +
1873 + bp = fw = (uint8_t *)mdb_alloc(ha->ql_dump_size, UM_SLEEP);
1874 +
1875 + if (mdb_vread(fw, ha->ql_dump_size,
1876 + (uintptr_t)ha->ql_dump_ptr) == -1) {
1877 + mdb_warn("failed to read ql_dump_ptr (no f/w dump active?)");
1878 + mdb_free(fw, ha->ql_dump_size);
1879 + return (DCMD_OK);
1880 + }
1881 +
1882 + while (cnt < ha->ql_dump_size) {
1883 + mdb_printf("%02x ", *bp++);
1884 + if (++cnt % 16 == 0) {
1885 + mdb_printf("\n");
1886 + }
1887 + }
1888 + if (cnt % 16 != 0) {
1889 + mdb_printf("\n");
1890 + }
1891 +
1892 + mdb_free(fw, ha->ql_dump_size);
1893 +
1894 + return (DCMD_OK);
1895 +}
1896 +
1897 +/*
1898 + * ql_83xx_dump_dcmd
1899 + * prints out a firmware dump buffer
1900 + *
1901 + * Input:
1902 + * addr = User supplied address. (NB: must be an ha)
1903 + * flags = mdb flags.
1904 + * argc = Number of user supplied args.
1905 + * argv = Arg array.
1906 + *
1907 + * Returns:
1908 + * DCMD_OK or DCMD_ERR
1909 + *
1910 + * Context:
1911 + * User context.
1912 + *
1913 + */
1914 +/*ARGSUSED*/
1915 +static int
1916 +ql_8300_dump_dcmd(ql_adapter_state_t *ha, uint_t flags, int argc,
1917 + const mdb_arg_t *argv)
1918 +{
1919 + ql_83xx_fw_dump_t *fw;
1920 + ql_response_q_t **rsp_queues, *rsp_q;
1921 + uint32_t cnt, cnt1, *dp, *dp2;
1922 +
1923 + fw = mdb_alloc(ha->ql_dump_size, UM_SLEEP);
1924 + rsp_queues = mdb_alloc(ha->rsp_queues_cnt *
1925 + sizeof (ql_response_q_t *), UM_SLEEP);
1926 + rsp_q = mdb_alloc(sizeof (ql_response_q_t), UM_SLEEP);
1927 +
1928 + if (mdb_vread(fw, ha->ql_dump_size,
1929 + (uintptr_t)ha->ql_dump_ptr) == -1 ||
1930 + mdb_vread(rsp_queues, ha->rsp_queues_cnt *
1931 + sizeof (ql_response_q_t *), (uintptr_t)ha->rsp_queues) == -1) {
1932 + mdb_warn("failed to read fw_dump_buffer (no f/w dump active?)");
1933 + mdb_free(rsp_q, sizeof (ql_response_q_t));
1934 + mdb_free(rsp_queues, ha->rsp_queues_cnt *
1935 + sizeof (ql_response_q_t *));
1936 + mdb_free(fw, ha->ql_dump_size);
1937 + return (DCMD_OK);
1938 + }
1939 +
1940 + mdb_printf("\nISP FW Version %d.%02d.%02d Attributes %X\n",
1941 + ha->fw_major_version, ha->fw_minor_version,
1942 + ha->fw_subminor_version, ha->fw_attributes);
1943 +
1944 + mdb_printf("\nHCCR Register\n%08x\n", fw->hccr);
1945 +
1946 + mdb_printf("\nR2H Status Register\n%08x\n", fw->r2h_status);
1947 +
1948 + mdb_printf("\nAER Uncorrectable Error Status Register\n%08x\n",
1949 + fw->aer_ues);
1950 +
1951 + mdb_printf("\nHostRisc Registers");
1952 + for (cnt = 0; cnt < sizeof (fw->hostrisc_reg) / 4; cnt++) {
1953 + if (cnt % 8 == 0) {
1954 + mdb_printf("\n");
1955 + }
1956 + mdb_printf("%08x ", fw->hostrisc_reg[cnt]);
1957 + }
1958 +
1959 + mdb_printf("\n\nPCIe Registers");
1960 + for (cnt = 0; cnt < sizeof (fw->pcie_reg) / 4; cnt++) {
1961 + if (cnt % 8 == 0) {
1962 + mdb_printf("\n");
1963 + }
1964 + mdb_printf("%08x ", fw->pcie_reg[cnt]);
1965 + }
1966 +
1967 + dp = fw->req_rsp_ext_mem;
1968 + for (cnt = 0; cnt < ha->rsp_queues_cnt; cnt++) {
1969 + mdb_printf("\n\nQueue Pointers #%d:\n", cnt);
1970 + for (cnt1 = 0; cnt1 < 4; cnt1++) {
1971 + mdb_printf("%08x ", *dp++);
1972 + }
1973 + }
1974 +
1975 + mdb_printf("\n\nHost Interface Registers");
1976 + for (cnt = 0; cnt < sizeof (fw->host_reg) / 4; cnt++) {
1977 + if (cnt % 8 == 0) {
1978 + mdb_printf("\n");
1979 + }
1980 + mdb_printf("%08x ", fw->host_reg[cnt]);
1981 + }
1982 +
1983 + mdb_printf("\n\nShadow Registers");
1984 + for (cnt = 0; cnt < sizeof (fw->shadow_reg) / 4; cnt++) {
1985 + if (cnt % 8 == 0) {
1986 + mdb_printf("\n");
1987 + }
1988 + mdb_printf("%08x ", fw->shadow_reg[cnt]);
1989 + }
1990 +
1991 + mdb_printf("\n\nRISC IO Register\n%08x", fw->risc_io);
1992 +
1993 + mdb_printf("\n\nMailbox Registers");
1994 + for (cnt = 0; cnt < sizeof (fw->mailbox_reg) / 2; cnt++) {
1995 + if (cnt % 16 == 0) {
1996 + mdb_printf("\n");
1997 + }
1998 + mdb_printf("%04x ", fw->mailbox_reg[cnt]);
1999 + }
2000 +
2001 + mdb_printf("\n\nXSEQ GP Registers");
2002 + for (cnt = 0; cnt < sizeof (fw->xseq_gp_reg) / 4; cnt++) {
2003 + if (cnt % 8 == 0) {
2004 + mdb_printf("\n");
2005 + }
2006 + mdb_printf("%08x ", fw->xseq_gp_reg[cnt]);
2007 + }
2008 +
2009 + mdb_printf("\n\nXSEQ-0 Registers");
2010 + for (cnt = 0; cnt < sizeof (fw->xseq_0_reg) / 4; cnt++) {
2011 + if (cnt % 8 == 0) {
2012 + mdb_printf("\n");
2013 + }
2014 + mdb_printf("%08x ", fw->xseq_0_reg[cnt]);
2015 + }
2016 +
2017 + mdb_printf("\n\nXSEQ-1 Registers");
2018 + for (cnt = 0; cnt < sizeof (fw->xseq_1_reg) / 4; cnt++) {
2019 + if (cnt % 8 == 0) {
2020 + mdb_printf("\n");
2021 + }
2022 + mdb_printf("%08x ", fw->xseq_1_reg[cnt]);
2023 + }
2024 +
2025 + mdb_printf("\n\nXSEQ-2 Registers");
2026 + for (cnt = 0; cnt < sizeof (fw->xseq_2_reg) / 4; cnt++) {
2027 + if (cnt % 8 == 0) {
2028 + mdb_printf("\n");
2029 + }
2030 + mdb_printf("%08x ", fw->xseq_2_reg[cnt]);
2031 + }
2032 +
2033 + mdb_printf("\n\nRSEQ GP Registers");
2034 + for (cnt = 0; cnt < sizeof (fw->rseq_gp_reg) / 4; cnt++) {
2035 + if (cnt % 8 == 0) {
2036 + mdb_printf("\n");
2037 + }
2038 + mdb_printf("%08x ", fw->rseq_gp_reg[cnt]);
2039 + }
2040 +
2041 + mdb_printf("\n\nRSEQ-0 Registers");
2042 + for (cnt = 0; cnt < sizeof (fw->rseq_0_reg) / 4; cnt++) {
2043 + if (cnt % 8 == 0) {
2044 + mdb_printf("\n");
2045 + }
2046 + mdb_printf("%08x ", fw->rseq_0_reg[cnt]);
2047 + }
2048 +
2049 + mdb_printf("\n\nRSEQ-1 Registers");
2050 + for (cnt = 0; cnt < sizeof (fw->rseq_1_reg) / 4; cnt++) {
2051 + if (cnt % 8 == 0) {
2052 + mdb_printf("\n");
2053 + }
2054 + mdb_printf("%08x ", fw->rseq_1_reg[cnt]);
2055 + }
2056 +
2057 + mdb_printf("\n\nRSEQ-2 Registers");
2058 + for (cnt = 0; cnt < sizeof (fw->rseq_2_reg) / 4; cnt++) {
2059 + if (cnt % 8 == 0) {
2060 + mdb_printf("\n");
2061 + }
2062 + mdb_printf("%08x ", fw->rseq_2_reg[cnt]);
2063 + }
2064 +
2065 + mdb_printf("\n\nRSEQ-3 Registers");
2066 + for (cnt = 0; cnt < sizeof (fw->rseq_3_reg) / 4; cnt++) {
2067 + if (cnt % 8 == 0) {
2068 + mdb_printf("\n");
2069 + }
2070 + mdb_printf("%08x ", fw->rseq_3_reg[cnt]);
2071 + }
2072 +
2073 + mdb_printf("\n\nASEQ GP Registers");
2074 + for (cnt = 0; cnt < sizeof (fw->aseq_gp_reg) / 4; cnt++) {
2075 + if (cnt % 8 == 0) {
2076 + mdb_printf("\n");
2077 + }
2078 + mdb_printf("%08x ", fw->aseq_gp_reg[cnt]);
2079 + }
2080 +
2081 + mdb_printf("\n\nASEQ-0 Registers");
2082 + for (cnt = 0; cnt < sizeof (fw->aseq_0_reg) / 4; cnt++) {
2083 + if (cnt % 8 == 0) {
2084 + mdb_printf("\n");
2085 + }
2086 + mdb_printf("%08x ", fw->aseq_0_reg[cnt]);
2087 + }
2088 +
2089 + mdb_printf("\n\nASEQ-1 Registers");
2090 + for (cnt = 0; cnt < sizeof (fw->aseq_1_reg) / 4; cnt++) {
2091 + if (cnt % 8 == 0) {
2092 + mdb_printf("\n");
2093 + }
2094 + mdb_printf("%08x ", fw->aseq_1_reg[cnt]);
2095 + }
2096 +
2097 + mdb_printf("\n\nASEQ-2 Registers");
2098 + for (cnt = 0; cnt < sizeof (fw->aseq_2_reg) / 4; cnt++) {
2099 + if (cnt % 8 == 0) {
2100 + mdb_printf("\n");
2101 + }
2102 + mdb_printf("%08x ", fw->aseq_2_reg[cnt]);
2103 + }
2104 +
2105 + mdb_printf("\n\nASEQ-3 Registers");
2106 + for (cnt = 0; cnt < sizeof (fw->aseq_3_reg) / 4; cnt++) {
2107 + if (cnt % 8 == 0) {
2108 + mdb_printf("\n");
2109 + }
2110 + mdb_printf("%08x ", fw->aseq_3_reg[cnt]);
2111 + }
2112 +
2113 + mdb_printf("\n\nCommand DMA Registers");
2114 + for (cnt = 0; cnt < sizeof (fw->cmd_dma_reg) / 4; cnt++) {
2115 + if (cnt % 8 == 0) {
2116 + mdb_printf("\n");
2117 + }
2118 + mdb_printf("%08x ", fw->cmd_dma_reg[cnt]);
2119 + }
2120 +
2121 + mdb_printf("\n\nRequest0 Queue DMA Channel Registers");
2122 + for (cnt = 0; cnt < sizeof (fw->req0_dma_reg) / 4; cnt++) {
2123 + if (cnt % 8 == 0) {
2124 + mdb_printf("\n");
2125 + }
2126 + mdb_printf("%08x ", fw->req0_dma_reg[cnt]);
2127 + }
2128 +
2129 + mdb_printf("\n\nResponse0 Queue DMA Channel Registers");
2130 + for (cnt = 0; cnt < sizeof (fw->resp0_dma_reg) / 4; cnt++) {
2131 + if (cnt % 8 == 0) {
2132 + mdb_printf("\n");
2133 + }
2134 + mdb_printf("%08x ", fw->resp0_dma_reg[cnt]);
2135 + }
2136 +
2137 + mdb_printf("\n\nRequest1 Queue DMA Channel Registers");
2138 + for (cnt = 0; cnt < sizeof (fw->req1_dma_reg) / 4; cnt++) {
2139 + if (cnt % 8 == 0) {
2140 + mdb_printf("\n");
2141 + }
2142 + mdb_printf("%08x ", fw->req1_dma_reg[cnt]);
2143 + }
2144 +
2145 + mdb_printf("\n\nXMT0 Data DMA Registers");
2146 + for (cnt = 0; cnt < sizeof (fw->xmt0_dma_reg) / 4; cnt++) {
2147 + if (cnt % 8 == 0) {
2148 + mdb_printf("\n");
2149 + }
2150 + mdb_printf("%08x ", fw->xmt0_dma_reg[cnt]);
2151 + }
2152 +
2153 + mdb_printf("\n\nXMT1 Data DMA Registers");
2154 + for (cnt = 0; cnt < sizeof (fw->xmt1_dma_reg) / 4; cnt++) {
2155 + if (cnt % 8 == 0) {
2156 + mdb_printf("\n");
2157 + }
2158 + mdb_printf("%08x ", fw->xmt1_dma_reg[cnt]);
2159 + }
2160 +
2161 + mdb_printf("\n\nXMT2 Data DMA Registers");
2162 + for (cnt = 0; cnt < sizeof (fw->xmt2_dma_reg) / 4; cnt++) {
2163 + if (cnt % 8 == 0) {
2164 + mdb_printf("\n");
2165 + }
2166 + mdb_printf("%08x ", fw->xmt2_dma_reg[cnt]);
2167 + }
2168 +
2169 + mdb_printf("\n\nXMT3 Data DMA Registers");
2170 + for (cnt = 0; cnt < sizeof (fw->xmt3_dma_reg) / 4; cnt++) {
2171 + if (cnt % 8 == 0) {
2172 + mdb_printf("\n");
2173 + }
2174 + mdb_printf("%08x ", fw->xmt3_dma_reg[cnt]);
2175 + }
2176 +
2177 + mdb_printf("\n\nXMT4 Data DMA Registers");
2178 + for (cnt = 0; cnt < sizeof (fw->xmt4_dma_reg) / 4; cnt++) {
2179 + if (cnt % 8 == 0) {
2180 + mdb_printf("\n");
2181 + }
2182 + mdb_printf("%08x ", fw->xmt4_dma_reg[cnt]);
2183 + }
2184 +
2185 + mdb_printf("\n\nXMT Data DMA Common Registers");
2186 + for (cnt = 0; cnt < sizeof (fw->xmt_data_dma_reg) / 4; cnt++) {
2187 + if (cnt % 8 == 0) {
2188 + mdb_printf("\n");
2189 + }
2190 + mdb_printf("%08x ", fw->xmt_data_dma_reg[cnt]);
2191 + }
2192 +
2193 + mdb_printf("\n\nRCV Thread 0 Data DMA Registers");
2194 + for (cnt = 0; cnt < sizeof (fw->rcvt0_data_dma_reg) / 4; cnt++) {
2195 + if (cnt % 8 == 0) {
2196 + mdb_printf("\n");
2197 + }
2198 + mdb_printf("%08x ", fw->rcvt0_data_dma_reg[cnt]);
2199 + }
2200 +
2201 + mdb_printf("\n\nRCV Thread 1 Data DMA Registers");
2202 + for (cnt = 0; cnt < sizeof (fw->rcvt1_data_dma_reg) / 4; cnt++) {
2203 + if (cnt % 8 == 0) {
2204 + mdb_printf("\n");
2205 + }
2206 + mdb_printf("%08x ", fw->rcvt1_data_dma_reg[cnt]);
2207 + }
2208 +
2209 + mdb_printf("\n\nRISC GP Registers");
2210 + for (cnt = 0; cnt < sizeof (fw->risc_gp_reg) / 4; cnt++) {
2211 + if (cnt % 8 == 0) {
2212 + mdb_printf("\n");
2213 + }
2214 + mdb_printf("%08x ", fw->risc_gp_reg[cnt]);
2215 + }
2216 +
2217 + mdb_printf("\n\nLMC Registers");
2218 + for (cnt = 0; cnt < sizeof (fw->lmc_reg) / 4; cnt++) {
2219 + if (cnt % 8 == 0) {
2220 + mdb_printf("\n");
2221 + }
2222 + mdb_printf("%08x ", fw->lmc_reg[cnt]);
2223 + }
2224 +
2225 + mdb_printf("\n\nFPM Hardware Registers");
2226 + for (cnt = 0; cnt < sizeof (fw->fpm_hdw_reg) / 4; cnt++) {
2227 + if (cnt % 8 == 0) {
2228 + mdb_printf("\n");
2229 + }
2230 + mdb_printf("%08x ", fw->fpm_hdw_reg[cnt]);
2231 + }
2232 +
2233 + mdb_printf("\n\nRQ0 Array Registers");
2234 + for (cnt = 0; cnt < sizeof (fw->rq0_array_reg) / 4; cnt++) {
2235 + if (cnt % 8 == 0) {
2236 + mdb_printf("\n");
2237 + }
2238 + mdb_printf("%08x ", fw->rq0_array_reg[cnt]);
2239 + }
2240 +
2241 + mdb_printf("\n\nRQ1 Array Registers");
2242 + for (cnt = 0; cnt < sizeof (fw->rq1_array_reg) / 4; cnt++) {
2243 + if (cnt % 8 == 0) {
2244 + mdb_printf("\n");
2245 + }
2246 + mdb_printf("%08x ", fw->rq1_array_reg[cnt]);
2247 + }
2248 +
2249 + mdb_printf("\n\nRP0 Array Registers");
2250 + for (cnt = 0; cnt < sizeof (fw->rp0_array_reg) / 4; cnt++) {
2251 + if (cnt % 8 == 0) {
2252 + mdb_printf("\n");
2253 + }
2254 + mdb_printf("%08x ", fw->rp0_array_reg[cnt]);
2255 + }
2256 +
2257 + mdb_printf("\n\nRP1 Array Registers");
2258 + for (cnt = 0; cnt < sizeof (fw->rp1_array_reg) / 4; cnt++) {
2259 + if (cnt % 8 == 0) {
2260 + mdb_printf("\n");
2261 + }
2262 + mdb_printf("%08x ", fw->rp1_array_reg[cnt]);
2263 + }
2264 +
2265 + mdb_printf("\n\nAT0 Array Registers");
2266 + for (cnt = 0; cnt < sizeof (fw->ato_array_reg) / 4; cnt++) {
2267 + if (cnt % 8 == 0) {
2268 + mdb_printf("\n");
2269 + }
2270 + mdb_printf("%08x ", fw->ato_array_reg[cnt]);
2271 + }
2272 +
2273 + mdb_printf("\n\nQueue Control Registers");
2274 + for (cnt = 0; cnt < sizeof (fw->queue_control_reg) / 4; cnt++) {
2275 + if (cnt % 8 == 0) {
2276 + mdb_printf("\n");
2277 + }
2278 + mdb_printf("%08x ", fw->queue_control_reg[cnt]);
2279 + }
2280 +
2281 + mdb_printf("\n\nFB Hardware Registers");
2282 + for (cnt = 0; cnt < sizeof (fw->fb_hdw_reg) / 4; cnt++) {
2283 + if (cnt % 8 == 0) {
2284 + mdb_printf("\n");
2285 + }
2286 + mdb_printf("%08x ", fw->fb_hdw_reg[cnt]);
2287 + }
2288 +
2289 + mdb_printf("\n\nCode RAM");
2290 + for (cnt = 0; cnt < sizeof (fw->code_ram) / 4; cnt++) {
2291 + if (cnt % 8 == 0) {
2292 + mdb_printf("\n%08x: ", cnt + 0x20000);
2293 + }
2294 + mdb_printf("%08x ", fw->code_ram[cnt]);
2295 + }
2296 +
2297 + mdb_printf("\n\nExternal Memory");
2298 + dp = (uint32_t *)(void *)((caddr_t)fw->req_rsp_ext_mem +
2299 + fw->req_q_size[0] + fw->req_q_size[1] + fw->rsp_q_size +
2300 + (ha->rsp_queues_cnt * 16));
2301 + for (cnt = 0; cnt < ha->fw_ext_memory_size / 4; cnt++) {
2302 + if (cnt % 8 == 0) {
2303 + mdb_printf("\n%08x: ", cnt + 0x100000);
2304 + }
2305 + mdb_printf("%08x ", *dp++);
2306 + }
2307 +
2308 + mdb_printf("\n\n[<==END] ISP Debug Dump");
2309 +
2310 + dp = fw->req_rsp_ext_mem + (ha->rsp_queues_cnt * 4);
2311 + for (cnt = 0; cnt < 2 && fw->req_q_size[cnt]; cnt++) {
2312 + dp2 = dp;
2313 + for (cnt1 = 0; cnt1 < fw->req_q_size[cnt] / 4; cnt1++) {
2314 + if (*dp2++) {
2315 + break;
2316 + }
2317 + }
2318 + if (cnt1 == fw->req_q_size[cnt] / 4) {
2319 + dp = dp2;
2320 + continue;
2321 + }
2322 + mdb_printf("\n\nRequest Queue\nQueue 0%d:", cnt);
2323 + for (cnt1 = 0; cnt1 < fw->req_q_size[cnt] / 4; cnt1++) {
2324 + if (cnt1 % 8 == 0) {
2325 + mdb_printf("\n%08x: ", cnt1);
2326 + }
2327 + mdb_printf("%08x ", *dp++);
2328 + }
2329 + }
2330 +
2331 + for (cnt = 0; cnt < ha->rsp_queues_cnt; cnt++) {
2332 + if (mdb_vread(rsp_q, sizeof (ql_response_q_t),
2333 + (uintptr_t)rsp_queues[cnt]) == -1) {
2334 + mdb_warn("failed to read ha->rsp_queues[%d]", cnt);
2335 + break;
2336 + }
2337 + dp2 = dp;
2338 + for (cnt1 = 0; cnt1 < rsp_q->rsp_ring.size / 4; cnt1++) {
2339 + if (*dp2++) {
2340 + break;
2341 + }
2342 + }
2343 + if (cnt1 == rsp_q->rsp_ring.size / 4) {
2344 + dp = dp2;
2345 + continue;
2346 + }
2347 + mdb_printf("\n\nResponse Queue\nQueue 0%d:", cnt);
2348 +
2349 + for (cnt1 = 0; cnt1 < rsp_q->rsp_ring.size / 4; cnt1++) {
2350 + if (cnt1 % 8 == 0) {
2351 + mdb_printf("\n%08x: ", cnt1);
2352 + }
2353 + mdb_printf("%08x ", *dp++);
2354 + }
2355 + }
2356 +
2357 + if (ha->fwexttracebuf.dma_handle != NULL) {
2358 + uint32_t cnt_b;
2359 + uint32_t *w32 = ha->fwexttracebuf.bp;
2360 +
2361 + mdb_printf("\n\nExtended Trace Buffer Memory");
2362 + /* show data address as a byte address, data as long words */
2363 + for (cnt = 0; cnt < FWEXTSIZE / 4; cnt++) {
2364 + cnt_b = cnt * 4;
2365 + if (cnt_b % 32 == 0) {
2366 + mdb_printf("\n%08x: ", w32 + cnt_b);
2367 + }
2368 + mdb_printf("%08x ", fw->ext_trace_buf[cnt]);
2369 + }
2370 + }
2371 +
2372 + if (ha->fwfcetracebuf.dma_handle != NULL) {
2373 + uint32_t cnt_b;
2374 + uint32_t *w32 = ha->fwfcetracebuf.bp;
2375 +
2376 + mdb_printf("\n\nFC Event Trace Buffer Memory");
2377 + /* show data address as a byte address, data as long words */
2378 + for (cnt = 0; cnt < FWFCESIZE / 4; cnt++) {
2379 + cnt_b = cnt * 4;
2380 + if (cnt_b % 32 == 0) {
2381 + mdb_printf("\n%08x: ", w32 + cnt_b);
2382 + }
2383 + mdb_printf("%08x ", fw->fce_trace_buf[cnt]);
2384 + }
2385 + }
2386 +
2387 + mdb_free(rsp_q, sizeof (ql_response_q_t));
2388 + mdb_free(rsp_queues, ha->rsp_queues_cnt * sizeof (ql_response_q_t *));
2389 + mdb_free(fw, ha->ql_dump_size);
2390 +
2391 + mdb_printf("\n\nreturn exit\n");
2392 +
2393 + return (DCMD_OK);
2394 +}
2395 +
2396 +/*
1836 2397 * ql_23xx_dump_dcmd
1837 2398 * prints out a firmware dump buffer
1838 2399 *
1839 2400 * Input:
1840 2401 * addr = User supplied address. (NB: nust be an ha)
1841 2402 * flags = mdb flags.
1842 2403 * argc = Number of user supplied args.
1843 2404 * argv = Arg array.
1844 2405 *
1845 2406 * Returns:
1846 2407 * DCMD_OK or DCMD_ERR
1847 2408 *
1848 2409 * Context:
1849 2410 * User context.
1850 2411 *
1851 2412 */
1852 2413 /*ARGSUSED*/
1853 2414 static int
1854 2415 ql_23xx_dump_dcmd(ql_adapter_state_t *ha, uint_t flags, int argc,
1855 2416 const mdb_arg_t *argv)
1856 2417 {
1857 2418 ql_fw_dump_t *fw;
1858 2419 uint32_t cnt = 0;
1859 2420 int mbox_cnt;
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1860 2421
1861 2422 fw = (ql_fw_dump_t *)mdb_alloc(ha->ql_dump_size, UM_SLEEP);
1862 2423
1863 2424 if (mdb_vread(fw, ha->ql_dump_size,
1864 2425 (uintptr_t)ha->ql_dump_ptr) == -1) {
1865 2426 mdb_warn("failed to read ql_dump_ptr (no f/w dump active?)");
1866 2427 mdb_free(fw, ha->ql_dump_size);
1867 2428 return (DCMD_OK);
1868 2429 }
1869 2430
1870 - if (ha->cfg_flags & CFG_CTRL_2300) {
2431 + if (ha->cfg_flags & CFG_CTRL_23XX) {
1871 2432 mdb_printf("\nISP 2300IP ");
1872 - } else if (ha->cfg_flags & CFG_CTRL_6322) {
1873 - mdb_printf("\nISP 6322FLX ");
2433 + } else if (ha->cfg_flags & CFG_CTRL_63XX) {
2434 + mdb_printf("\nISP 2322/6322FLX ");
1874 2435 } else {
1875 2436 mdb_printf("\nISP 2200IP ");
1876 2437 }
1877 2438
1878 2439 mdb_printf("Firmware Version %d.%d.%d\n",
1879 2440 ha->fw_major_version, ha->fw_minor_version,
1880 2441 ha->fw_subminor_version);
1881 2442
1882 2443 mdb_printf("\nPBIU Registers:");
1883 2444 for (cnt = 0; cnt < sizeof (fw->pbiu_reg) / 2; cnt++) {
1884 2445 if (cnt % 8 == 0) {
1885 2446 mdb_printf("\n");
1886 2447 }
1887 2448 mdb_printf("%04x ", fw->pbiu_reg[cnt]);
1888 2449 }
1889 2450
1890 - if (ha->cfg_flags & (CFG_CTRL_2300 | CFG_CTRL_6322)) {
2451 + if (ha->cfg_flags & CFG_CTRL_2363) {
1891 2452 mdb_printf("\n\nReqQ-RspQ-Risc2Host Status registers:");
1892 2453 for (cnt = 0; cnt < sizeof (fw->risc_host_reg) / 2; cnt++) {
1893 2454 if (cnt % 8 == 0) {
1894 2455 mdb_printf("\n");
1895 2456 }
1896 2457 mdb_printf("%04x ", fw->risc_host_reg[cnt]);
1897 2458 }
1898 2459 }
1899 2460
1900 2461 mdb_printf("\n\nMailbox Registers:");
1901 - mbox_cnt = (ha->cfg_flags & (CFG_CTRL_2300 | CFG_CTRL_6322)) ? 16 : 8;
2462 + mbox_cnt = ha->cfg_flags & CFG_CTRL_2363 ? 16 : 8;
1902 2463 for (cnt = 0; cnt < mbox_cnt; cnt++) {
1903 2464 if (cnt % 8 == 0) {
1904 2465 mdb_printf("\n");
1905 2466 }
1906 2467 mdb_printf("%04x ", fw->mailbox_reg[cnt]);
1907 2468 }
1908 2469
1909 - if (ha->cfg_flags & (CFG_CTRL_2300 | CFG_CTRL_6322)) {
2470 + if (ha->cfg_flags & CFG_CTRL_2363) {
1910 2471 mdb_printf("\n\nAuto Request Response DMA Registers:");
1911 2472 for (cnt = 0; cnt < sizeof (fw->resp_dma_reg) / 2; cnt++) {
1912 2473 if (cnt % 8 == 0) {
1913 2474 mdb_printf("\n");
1914 2475 }
1915 2476 mdb_printf("%04x ", fw->resp_dma_reg[cnt]);
1916 2477 }
1917 2478 }
1918 2479
1919 2480 mdb_printf("\n\nDMA Registers:");
1920 2481 for (cnt = 0; cnt < sizeof (fw->dma_reg) / 2; cnt++) {
1921 2482 if (cnt % 8 == 0) {
1922 2483 mdb_printf("\n");
1923 2484 }
1924 2485 mdb_printf("%04x ", fw->dma_reg[cnt]);
1925 2486 }
1926 2487
1927 2488 mdb_printf("\n\nRISC Hardware Registers:");
1928 2489 for (cnt = 0; cnt < sizeof (fw->risc_hdw_reg) / 2; cnt++) {
1929 2490 if (cnt % 8 == 0) {
1930 2491 mdb_printf("\n");
1931 2492 }
1932 2493 mdb_printf("%04x ", fw->risc_hdw_reg[cnt]);
1933 2494 }
1934 2495
1935 2496 mdb_printf("\n\nRISC GP0 Registers:");
1936 2497 for (cnt = 0; cnt < sizeof (fw->risc_gp0_reg) / 2; cnt++) {
1937 2498 if (cnt % 8 == 0) {
1938 2499 mdb_printf("\n");
1939 2500 }
1940 2501 mdb_printf("%04x ", fw->risc_gp0_reg[cnt]);
1941 2502 }
1942 2503
1943 2504 mdb_printf("\n\nRISC GP1 Registers:");
1944 2505 for (cnt = 0; cnt < sizeof (fw->risc_gp1_reg) / 2; cnt++) {
1945 2506 if (cnt % 8 == 0) {
1946 2507 mdb_printf("\n");
1947 2508 }
1948 2509 mdb_printf("%04x ", fw->risc_gp1_reg[cnt]);
1949 2510 }
1950 2511
1951 2512 mdb_printf("\n\nRISC GP2 Registers:");
1952 2513 for (cnt = 0; cnt < sizeof (fw->risc_gp2_reg) / 2; cnt++) {
1953 2514 if (cnt % 8 == 0) {
1954 2515 mdb_printf("\n");
1955 2516 }
1956 2517 mdb_printf("%04x ", fw->risc_gp2_reg[cnt]);
1957 2518 }
1958 2519
1959 2520 mdb_printf("\n\nRISC GP3 Registers:");
1960 2521 for (cnt = 0; cnt < sizeof (fw->risc_gp3_reg) / 2; cnt++) {
1961 2522 if (cnt % 8 == 0) {
1962 2523 mdb_printf("\n");
1963 2524 }
1964 2525 mdb_printf("%04x ", fw->risc_gp3_reg[cnt]);
1965 2526 }
1966 2527
1967 2528 mdb_printf("\n\nRISC GP4 Registers:");
1968 2529 for (cnt = 0; cnt < sizeof (fw->risc_gp4_reg) / 2; cnt++) {
1969 2530 if (cnt % 8 == 0) {
1970 2531 mdb_printf("\n");
1971 2532 }
1972 2533 mdb_printf("%04x ", fw->risc_gp4_reg[cnt]);
1973 2534 }
1974 2535
1975 2536 mdb_printf("\n\nRISC GP5 Registers:");
1976 2537 for (cnt = 0; cnt < sizeof (fw->risc_gp5_reg) / 2; cnt++) {
1977 2538 if (cnt % 8 == 0) {
1978 2539 mdb_printf("\n");
1979 2540 }
1980 2541 mdb_printf("%04x ", fw->risc_gp5_reg[cnt]);
1981 2542 }
1982 2543
1983 2544 mdb_printf("\n\nRISC GP6 Registers:");
1984 2545 for (cnt = 0; cnt < sizeof (fw->risc_gp6_reg) / 2; cnt++) {
1985 2546 if (cnt % 8 == 0) {
1986 2547 mdb_printf("\n");
1987 2548 }
1988 2549 mdb_printf("%04x ", fw->risc_gp6_reg[cnt]);
1989 2550 }
1990 2551
1991 2552 mdb_printf("\n\nRISC GP7 Registers:");
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1992 2553 for (cnt = 0; cnt < sizeof (fw->risc_gp7_reg) / 2; cnt++) {
1993 2554 if (cnt % 8 == 0) {
1994 2555 mdb_printf("\n");
1995 2556 }
1996 2557 mdb_printf("%04x ", fw->risc_gp7_reg[cnt]);
1997 2558 }
1998 2559
1999 2560 mdb_printf("\n\nFrame Buffer Hardware Registers:");
2000 2561 for (cnt = 0; cnt < sizeof (fw->frame_buf_hdw_reg) / 2; cnt++) {
2001 2562 if ((cnt == 16) &&
2002 - ((ha->cfg_flags & (CFG_CTRL_2300 | CFG_CTRL_6322)) == 0)) {
2563 + ((ha->cfg_flags & CFG_CTRL_2363) == 0)) {
2003 2564 break;
2004 2565 }
2005 2566 if (cnt % 8 == 0) {
2006 2567 mdb_printf("\n");
2007 2568 }
2008 2569 mdb_printf("%04x ", fw->frame_buf_hdw_reg[cnt]);
2009 2570 }
2010 2571
2011 2572 mdb_printf("\n\nFPM B0 Registers:");
2012 2573 for (cnt = 0; cnt < sizeof (fw->fpm_b0_reg) / 2; cnt++) {
2013 2574 if (cnt % 8 == 0) {
2014 2575 mdb_printf("\n");
2015 2576 }
2016 2577 mdb_printf("%04x ", fw->fpm_b0_reg[cnt]);
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2017 2578 }
2018 2579
2019 2580 mdb_printf("\n\nFPM B1 Registers:");
2020 2581 for (cnt = 0; cnt < sizeof (fw->fpm_b1_reg) / 2; cnt++) {
2021 2582 if (cnt % 8 == 0) {
2022 2583 mdb_printf("\n");
2023 2584 }
2024 2585 mdb_printf("%04x ", fw->fpm_b1_reg[cnt]);
2025 2586 }
2026 2587
2027 - if (ha->cfg_flags & (CFG_CTRL_2300 | CFG_CTRL_6322)) {
2588 + if (ha->cfg_flags & CFG_CTRL_2363) {
2028 2589 mdb_printf("\n\nCode RAM Dump:");
2029 2590 for (cnt = 0; cnt < sizeof (fw->risc_ram) / 2; cnt++) {
2030 2591 if (cnt % 8 == 0) {
2031 2592 mdb_printf("\n%05x: ", cnt + 0x0800);
2032 2593 }
2033 2594 mdb_printf("%04x ", fw->risc_ram[cnt]);
2034 2595 }
2035 2596
2036 2597 mdb_printf("\n\nStack RAM Dump:");
2037 2598 for (cnt = 0; cnt < sizeof (fw->stack_ram) / 2; cnt++) {
2038 2599 if (cnt % 8 == 0) {
2039 2600 mdb_printf("\n%05x: ", cnt + 0x010000);
2040 2601 }
2041 2602 mdb_printf("%04x ", fw->stack_ram[cnt]);
2042 2603 }
2043 2604
2044 2605 mdb_printf("\n\nData RAM Dump:");
2045 2606 for (cnt = 0; cnt < sizeof (fw->data_ram) / 2; cnt++) {
2046 2607 if (cnt % 8 == 0) {
2047 2608 mdb_printf("\n%05x: ", cnt + 0x010800);
2048 2609 }
2049 2610 mdb_printf("%04x ", fw->data_ram[cnt]);
2050 2611 }
2051 2612
2052 2613 mdb_printf("\n\n[<==END] ISP Debug Dump.\n");
2053 2614
2054 2615 mdb_printf("\n\nRequest Queue");
2055 2616
2056 2617 for (cnt = 0; cnt < REQUEST_QUEUE_SIZE / 4; cnt++) {
2057 2618 if (cnt % 8 == 0) {
2058 2619 mdb_printf("\n%08x: ", cnt);
2059 2620 }
2060 2621 mdb_printf("%08x ", fw->req_q[cnt]);
2061 2622 }
2062 2623
2063 2624 mdb_printf("\n\nResponse Queue");
2064 2625
2065 2626 for (cnt = 0; cnt < RESPONSE_QUEUE_SIZE / 4; cnt++) {
2066 2627 if (cnt % 8 == 0) {
2067 2628 mdb_printf("\n%08x: ", cnt);
2068 2629 }
2069 2630 mdb_printf("%08x ", fw->rsp_q[cnt]);
2070 2631 }
2071 2632
2072 2633 mdb_printf("\n");
2073 2634
2074 2635 } else {
2075 2636 mdb_printf("\n\nRISC SRAM:");
2076 2637 for (cnt = 0; cnt < 0xf000; cnt++) {
2077 2638 if (cnt % 8 == 0) {
2078 2639 mdb_printf("\n%04x: ", cnt + 0x1000);
2079 2640 }
2080 2641 mdb_printf("%04x ", fw->risc_ram[cnt]);
2081 2642 }
2082 2643 }
2083 2644
2084 2645 mdb_free(fw, ha->ql_dump_size);
2085 2646
2086 2647 return (DCMD_OK);
2087 2648 }
2088 2649
2089 2650 /*
2090 2651 * ql_24xx_dump_dcmd
2091 2652 * prints out a firmware dump buffer
2092 2653 *
2093 2654 * Input:
2094 2655 * addr = User supplied address. (NB: nust be an ha)
2095 2656 * flags = mdb flags.
2096 2657 * argc = Number of user supplied args.
2097 2658 * argv = Arg array.
2098 2659 *
2099 2660 * Returns:
2100 2661 * DCMD_OK or DCMD_ERR
2101 2662 *
2102 2663 * Context:
2103 2664 * User context.
2104 2665 *
2105 2666 */
2106 2667 /*ARGSUSED*/
2107 2668 static int
2108 2669 ql_24xx_dump_dcmd(ql_adapter_state_t *ha, uint_t flags, int argc,
2109 2670 const mdb_arg_t *argv)
2110 2671 {
2111 2672 ql_24xx_fw_dump_t *fw;
2112 2673 uint32_t cnt = 0;
2113 2674
2114 2675 fw = (ql_24xx_fw_dump_t *)mdb_alloc(ha->ql_dump_size, UM_SLEEP);
2115 2676
2116 2677 if (mdb_vread(fw, ha->ql_dump_size,
2117 2678 (uintptr_t)ha->ql_dump_ptr) == -1) {
2118 2679 mdb_warn("failed to read ql_dump_ptr (no f/w dump active?)");
2119 2680 mdb_free(fw, ha->ql_dump_size);
2120 2681 return (DCMD_OK);
2121 2682 }
2122 2683
2123 2684 mdb_printf("ISP FW Version %d.%02d.%02d Attributes %X\n",
2124 2685 ha->fw_major_version, ha->fw_minor_version,
2125 2686 ha->fw_subminor_version, ha->fw_attributes);
2126 2687
2127 2688 mdb_printf("\nHCCR Register\n%08x\n", fw->hccr);
2128 2689
2129 2690 mdb_printf("\nHost Interface Registers");
2130 2691 for (cnt = 0; cnt < sizeof (fw->host_reg) / 4; cnt++) {
2131 2692 if (cnt % 8 == 0) {
2132 2693 mdb_printf("\n");
2133 2694 }
2134 2695 mdb_printf("%08x ", fw->host_reg[cnt]);
2135 2696 }
2136 2697
2137 2698 mdb_printf("\n\nMailbox Registers");
2138 2699 for (cnt = 0; cnt < sizeof (fw->mailbox_reg) / 2; cnt++) {
2139 2700 if (cnt % 16 == 0) {
2140 2701 mdb_printf("\n");
2141 2702 }
2142 2703 mdb_printf("%04x ", fw->mailbox_reg[cnt]);
2143 2704 }
2144 2705
2145 2706 mdb_printf("\n\nXSEQ GP Registers");
2146 2707 for (cnt = 0; cnt < sizeof (fw->xseq_gp_reg) / 4; cnt++) {
2147 2708 if (cnt % 8 == 0) {
2148 2709 mdb_printf("\n");
2149 2710 }
2150 2711 mdb_printf("%08x ", fw->xseq_gp_reg[cnt]);
2151 2712 }
2152 2713
2153 2714 mdb_printf("\n\nXSEQ-0 Registers");
2154 2715 for (cnt = 0; cnt < sizeof (fw->xseq_0_reg) / 4; cnt++) {
2155 2716 if (cnt % 8 == 0) {
2156 2717 mdb_printf("\n");
2157 2718 }
2158 2719 mdb_printf("%08x ", fw->xseq_0_reg[cnt]);
2159 2720 }
2160 2721
2161 2722 mdb_printf("\n\nXSEQ-1 Registers");
2162 2723 for (cnt = 0; cnt < sizeof (fw->xseq_1_reg) / 4; cnt++) {
2163 2724 if (cnt % 8 == 0) {
2164 2725 mdb_printf("\n");
2165 2726 }
2166 2727 mdb_printf("%08x ", fw->xseq_1_reg[cnt]);
2167 2728 }
2168 2729
2169 2730 mdb_printf("\n\nRSEQ GP Registers");
2170 2731 for (cnt = 0; cnt < sizeof (fw->rseq_gp_reg) / 4; cnt++) {
2171 2732 if (cnt % 8 == 0) {
2172 2733 mdb_printf("\n");
2173 2734 }
2174 2735 mdb_printf("%08x ", fw->rseq_gp_reg[cnt]);
2175 2736 }
2176 2737
2177 2738 mdb_printf("\n\nRSEQ-0 Registers");
2178 2739 for (cnt = 0; cnt < sizeof (fw->rseq_0_reg) / 4; cnt++) {
2179 2740 if (cnt % 8 == 0) {
2180 2741 mdb_printf("\n");
2181 2742 }
2182 2743 mdb_printf("%08x ", fw->rseq_0_reg[cnt]);
2183 2744 }
2184 2745
2185 2746 mdb_printf("\n\nRSEQ-1 Registers");
2186 2747 for (cnt = 0; cnt < sizeof (fw->rseq_1_reg) / 4; cnt++) {
2187 2748 if (cnt % 8 == 0) {
2188 2749 mdb_printf("\n");
2189 2750 }
2190 2751 mdb_printf("%08x ", fw->rseq_1_reg[cnt]);
2191 2752 }
2192 2753
2193 2754 mdb_printf("\n\nRSEQ-2 Registers");
2194 2755 for (cnt = 0; cnt < sizeof (fw->rseq_2_reg) / 4; cnt++) {
2195 2756 if (cnt % 8 == 0) {
2196 2757 mdb_printf("\n");
2197 2758 }
2198 2759 mdb_printf("%08x ", fw->rseq_2_reg[cnt]);
2199 2760 }
2200 2761
2201 2762 mdb_printf("\n\nCommand DMA Registers");
2202 2763 for (cnt = 0; cnt < sizeof (fw->cmd_dma_reg) / 4; cnt++) {
2203 2764 if (cnt % 8 == 0) {
2204 2765 mdb_printf("\n");
2205 2766 }
2206 2767 mdb_printf("%08x ", fw->cmd_dma_reg[cnt]);
2207 2768 }
2208 2769
2209 2770 mdb_printf("\n\nRequest0 Queue DMA Channel Registers");
2210 2771 for (cnt = 0; cnt < sizeof (fw->req0_dma_reg) / 4; cnt++) {
2211 2772 if (cnt % 8 == 0) {
2212 2773 mdb_printf("\n");
2213 2774 }
2214 2775 mdb_printf("%08x ", fw->req0_dma_reg[cnt]);
2215 2776 }
2216 2777
2217 2778 mdb_printf("\n\nResponse0 Queue DMA Channel Registers");
2218 2779 for (cnt = 0; cnt < sizeof (fw->resp0_dma_reg) / 4; cnt++) {
2219 2780 if (cnt % 8 == 0) {
2220 2781 mdb_printf("\n");
2221 2782 }
2222 2783 mdb_printf("%08x ", fw->resp0_dma_reg[cnt]);
2223 2784 }
2224 2785
2225 2786 mdb_printf("\n\nRequest1 Queue DMA Channel Registers");
2226 2787 for (cnt = 0; cnt < sizeof (fw->req1_dma_reg) / 4; cnt++) {
2227 2788 if (cnt % 8 == 0) {
2228 2789 mdb_printf("\n");
2229 2790 }
2230 2791 mdb_printf("%08x ", fw->req1_dma_reg[cnt]);
2231 2792 }
2232 2793
2233 2794 mdb_printf("\n\nXMT0 Data DMA Registers");
2234 2795 for (cnt = 0; cnt < sizeof (fw->xmt0_dma_reg) / 4; cnt++) {
2235 2796 if (cnt % 8 == 0) {
2236 2797 mdb_printf("\n");
2237 2798 }
2238 2799 mdb_printf("%08x ", fw->xmt0_dma_reg[cnt]);
2239 2800 }
2240 2801
2241 2802 mdb_printf("\n\nXMT1 Data DMA Registers");
2242 2803 for (cnt = 0; cnt < sizeof (fw->xmt1_dma_reg) / 4; cnt++) {
2243 2804 if (cnt % 8 == 0) {
2244 2805 mdb_printf("\n");
2245 2806 }
2246 2807 mdb_printf("%08x ", fw->xmt1_dma_reg[cnt]);
2247 2808 }
2248 2809
2249 2810 mdb_printf("\n\nXMT2 Data DMA Registers");
2250 2811 for (cnt = 0; cnt < sizeof (fw->xmt2_dma_reg) / 4; cnt++) {
2251 2812 if (cnt % 8 == 0) {
2252 2813 mdb_printf("\n");
2253 2814 }
2254 2815 mdb_printf("%08x ", fw->xmt2_dma_reg[cnt]);
2255 2816 }
2256 2817
2257 2818 mdb_printf("\n\nXMT3 Data DMA Registers");
2258 2819 for (cnt = 0; cnt < sizeof (fw->xmt3_dma_reg) / 4; cnt++) {
2259 2820 if (cnt % 8 == 0) {
2260 2821 mdb_printf("\n");
2261 2822 }
2262 2823 mdb_printf("%08x ", fw->xmt3_dma_reg[cnt]);
2263 2824 }
2264 2825
2265 2826 mdb_printf("\n\nXMT4 Data DMA Registers");
2266 2827 for (cnt = 0; cnt < sizeof (fw->xmt4_dma_reg) / 4; cnt++) {
2267 2828 if (cnt % 8 == 0) {
2268 2829 mdb_printf("\n");
2269 2830 }
2270 2831 mdb_printf("%08x ", fw->xmt4_dma_reg[cnt]);
2271 2832 }
2272 2833
2273 2834 mdb_printf("\n\nXMT Data DMA Common Registers");
2274 2835 for (cnt = 0; cnt < sizeof (fw->xmt_data_dma_reg) / 4; cnt++) {
2275 2836 if (cnt % 8 == 0) {
2276 2837 mdb_printf("\n");
2277 2838 }
2278 2839 mdb_printf("%08x ", fw->xmt_data_dma_reg[cnt]);
2279 2840 }
2280 2841
2281 2842 mdb_printf("\n\nRCV Thread 0 Data DMA Registers");
2282 2843 for (cnt = 0; cnt < sizeof (fw->rcvt0_data_dma_reg) / 4; cnt++) {
2283 2844 if (cnt % 8 == 0) {
2284 2845 mdb_printf("\n");
2285 2846 }
2286 2847 mdb_printf("%08x ", fw->rcvt0_data_dma_reg[cnt]);
2287 2848 }
2288 2849
2289 2850 mdb_printf("\n\nRCV Thread 1 Data DMA Registers");
2290 2851 for (cnt = 0; cnt < sizeof (fw->rcvt1_data_dma_reg) / 4; cnt++) {
2291 2852 if (cnt % 8 == 0) {
2292 2853 mdb_printf("\n");
2293 2854 }
2294 2855 mdb_printf("%08x ", fw->rcvt1_data_dma_reg[cnt]);
2295 2856 }
2296 2857
2297 2858 mdb_printf("\n\nRISC GP Registers");
2298 2859 for (cnt = 0; cnt < sizeof (fw->risc_gp_reg) / 4; cnt++) {
2299 2860 if (cnt % 8 == 0) {
2300 2861 mdb_printf("\n");
2301 2862 }
2302 2863 mdb_printf("%08x ", fw->risc_gp_reg[cnt]);
2303 2864 }
2304 2865
2305 2866 mdb_printf("\n\nShadow Registers");
2306 2867 for (cnt = 0; cnt < sizeof (fw->shadow_reg) / 4; cnt++) {
2307 2868 if (cnt % 8 == 0) {
2308 2869 mdb_printf("\n");
2309 2870 }
2310 2871 mdb_printf("%08x ", fw->shadow_reg[cnt]);
2311 2872 }
2312 2873
2313 2874 mdb_printf("\n\nLMC Registers");
2314 2875 for (cnt = 0; cnt < sizeof (fw->lmc_reg) / 4; cnt++) {
2315 2876 if (cnt % 8 == 0) {
2316 2877 mdb_printf("\n");
2317 2878 }
2318 2879 mdb_printf("%08x ", fw->lmc_reg[cnt]);
2319 2880 }
2320 2881
2321 2882 mdb_printf("\n\nFPM Hardware Registers");
2322 2883 for (cnt = 0; cnt < sizeof (fw->fpm_hdw_reg) / 4; cnt++) {
2323 2884 if (cnt % 8 == 0) {
2324 2885 mdb_printf("\n");
2325 2886 }
2326 2887 mdb_printf("%08x ", fw->fpm_hdw_reg[cnt]);
2327 2888 }
2328 2889
2329 2890 mdb_printf("\n\nFB Hardware Registers");
2330 2891 for (cnt = 0; cnt < sizeof (fw->fb_hdw_reg) / 4; cnt++) {
2331 2892 if (cnt % 8 == 0) {
2332 2893 mdb_printf("\n");
2333 2894 }
2334 2895 mdb_printf("%08x ", fw->fb_hdw_reg[cnt]);
2335 2896 }
2336 2897
2337 2898 mdb_printf("\n\nCode RAM");
2338 2899 for (cnt = 0; cnt < sizeof (fw->code_ram) / 4; cnt++) {
2339 2900 if (cnt % 8 == 0) {
2340 2901 mdb_printf("\n%08x: ", cnt + 0x20000);
2341 2902 }
2342 2903 mdb_printf("%08x ", fw->code_ram[cnt]);
2343 2904 }
2344 2905
2345 2906 mdb_printf("\n\nExternal Memory");
2346 2907 for (cnt = 0; cnt < ha->fw_ext_memory_size / 4; cnt++) {
2347 2908 if (cnt % 8 == 0) {
2348 2909 mdb_printf("\n%08x: ", cnt + 0x100000);
2349 2910 }
2350 2911 mdb_printf("%08x ", fw->ext_mem[cnt]);
2351 2912 }
2352 2913
2353 2914 mdb_printf("\n[<==END] ISP Debug Dump");
2354 2915
2355 2916 mdb_printf("\n\nRequest Queue");
2356 2917
2357 2918 for (cnt = 0; cnt < REQUEST_QUEUE_SIZE / 4; cnt++) {
2358 2919 if (cnt % 8 == 0) {
2359 2920 mdb_printf("\n%08x: ", cnt);
2360 2921 }
2361 2922 mdb_printf("%08x ", fw->req_q[cnt]);
2362 2923 }
2363 2924
2364 2925 mdb_printf("\n\nResponse Queue");
2365 2926
2366 2927 for (cnt = 0; cnt < RESPONSE_QUEUE_SIZE / 4; cnt++) {
2367 2928 if (cnt % 8 == 0) {
2368 2929 mdb_printf("\n%08x: ", cnt);
2369 2930 }
2370 2931 mdb_printf("%08x ", fw->rsp_q[cnt]);
2371 2932 }
2372 2933
2373 2934 if ((ha->cfg_flags & CFG_ENABLE_FWEXTTRACE) &&
2374 2935 (ha->fwexttracebuf.bp != NULL)) {
2375 2936 uint32_t cnt_b = 0;
2376 2937 uint32_t *w32 = ha->fwexttracebuf.bp;
2377 2938
2378 2939 mdb_printf("\n\nExtended Trace Buffer Memory");
2379 2940 /* show data address as a byte address, data as long words */
2380 2941 for (cnt = 0; cnt < FWEXTSIZE / 4; cnt++) {
2381 2942 cnt_b = cnt * 4;
2382 2943 if (cnt_b % 32 == 0) {
2383 2944 mdb_printf("\n%08x: ", w32 + cnt_b);
2384 2945 }
2385 2946 mdb_printf("%08x ", fw->ext_trace_buf[cnt]);
2386 2947 }
2387 2948 }
2388 2949
2389 2950 if ((ha->cfg_flags & CFG_ENABLE_FWFCETRACE) &&
2390 2951 (ha->fwfcetracebuf.bp != NULL)) {
2391 2952 uint32_t cnt_b = 0;
2392 2953 uint32_t *w32 = ha->fwfcetracebuf.bp;
2393 2954
2394 2955 mdb_printf("\n\nFC Event Trace Buffer Memory");
2395 2956 /* show data address as a byte address, data as long words */
2396 2957 for (cnt = 0; cnt < FWFCESIZE / 4; cnt++) {
2397 2958 cnt_b = cnt * 4;
2398 2959 if (cnt_b % 32 == 0) {
2399 2960 mdb_printf("\n%08x: ", w32 + cnt_b);
2400 2961 }
2401 2962 mdb_printf("%08x ", fw->fce_trace_buf[cnt]);
2402 2963 }
2403 2964 }
2404 2965 mdb_free(fw, ha->ql_dump_size);
2405 2966
2406 2967 return (DCMD_OK);
2407 2968 }
2408 2969
2409 2970 /*
2410 2971 * ql_25xx_dump_dcmd
2411 2972 * prints out a firmware dump buffer
2412 2973 *
2413 2974 * Input:
2414 2975 * addr = User supplied address. (NB: nust be an ha)
2415 2976 * flags = mdb flags.
2416 2977 * argc = Number of user supplied args.
2417 2978 * argv = Arg array.
2418 2979 *
2419 2980 * Returns:
2420 2981 * DCMD_OK or DCMD_ERR
2421 2982 *
|
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2422 2983 * Context:
2423 2984 * User context.
2424 2985 *
2425 2986 */
2426 2987 /*ARGSUSED*/
2427 2988 static int
2428 2989 ql_25xx_dump_dcmd(ql_adapter_state_t *ha, uint_t flags, int argc,
2429 2990 const mdb_arg_t *argv)
2430 2991 {
2431 2992 ql_25xx_fw_dump_t *fw;
2432 - uint32_t cnt = 0;
2993 + ql_response_q_t **rsp_queues, *rsp_q;
2994 + uint32_t cnt, cnt1, *dp, *dp2;
2433 2995
2434 2996 fw = (ql_25xx_fw_dump_t *)mdb_alloc(ha->ql_dump_size, UM_SLEEP);
2997 + rsp_queues = mdb_alloc(ha->rsp_queues_cnt *
2998 + sizeof (ql_response_q_t *), UM_SLEEP);
2999 + rsp_q = mdb_alloc(sizeof (ql_response_q_t), UM_SLEEP);
2435 3000
2436 3001 if (mdb_vread(fw, ha->ql_dump_size,
2437 - (uintptr_t)ha->ql_dump_ptr) == -1) {
3002 + (uintptr_t)ha->ql_dump_ptr) == -1 ||
3003 + mdb_vread(rsp_queues, ha->rsp_queues_cnt *
3004 + sizeof (ql_response_q_t *), (uintptr_t)ha->rsp_queues) == -1) {
2438 3005 mdb_warn("failed to read ql_dump_ptr (no f/w dump active?)");
3006 + mdb_free(rsp_q, sizeof (ql_response_q_t));
3007 + mdb_free(rsp_queues, ha->rsp_queues_cnt *
3008 + sizeof (ql_response_q_t *));
2439 3009 mdb_free(fw, ha->ql_dump_size);
2440 3010 return (DCMD_OK);
2441 3011 }
2442 3012
2443 3013 mdb_printf("\nISP FW Version %d.%02d.%02d Attributes %X\n",
2444 3014 ha->fw_major_version, ha->fw_minor_version,
2445 3015 ha->fw_subminor_version, ha->fw_attributes);
2446 3016
3017 + mdb_printf("\nHCCR Register\n%08x\n", fw->hccr);
2447 3018 mdb_printf("\nR2H Register\n%08x\n", fw->r2h_status);
3019 + mdb_printf("\nAER Uncorrectable Error Status Register\n%08x\n",
3020 + fw->aer_ues);
2448 3021
2449 3022 mdb_printf("\n\nHostRisc Registers");
2450 3023 for (cnt = 0; cnt < sizeof (fw->hostrisc_reg) / 4; cnt++) {
2451 3024 if (cnt % 8 == 0) {
2452 3025 mdb_printf("\n");
2453 3026 }
2454 3027 mdb_printf("%08x ", fw->hostrisc_reg[cnt]);
2455 3028 }
2456 3029
2457 3030 mdb_printf("\n\nPCIe Registers");
2458 3031 for (cnt = 0; cnt < sizeof (fw->pcie_reg) / 4; cnt++) {
2459 3032 if (cnt % 8 == 0) {
2460 3033 mdb_printf("\n");
2461 3034 }
2462 3035 mdb_printf("%08x ", fw->pcie_reg[cnt]);
2463 3036 }
2464 3037
2465 3038 mdb_printf("\n\nHost Interface Registers");
2466 3039 for (cnt = 0; cnt < sizeof (fw->host_reg) / 4; cnt++) {
2467 3040 if (cnt % 8 == 0) {
2468 3041 mdb_printf("\n");
2469 3042 }
2470 3043 mdb_printf("%08x ", fw->host_reg[cnt]);
2471 3044 }
2472 3045
2473 3046 mdb_printf("\n\nShadow Registers");
2474 3047 for (cnt = 0; cnt < sizeof (fw->shadow_reg) / 4; cnt++) {
2475 3048 if (cnt % 8 == 0) {
2476 3049 mdb_printf("\n");
2477 3050 }
2478 3051
2479 3052 mdb_printf("%08x ", fw->shadow_reg[cnt]);
2480 3053 }
2481 3054
2482 3055 mdb_printf("\n\nMailbox Registers");
2483 3056 for (cnt = 0; cnt < sizeof (fw->mailbox_reg) / 2; cnt++) {
2484 3057 if (cnt % 16 == 0) {
2485 3058 mdb_printf("\n");
2486 3059 }
2487 3060 mdb_printf("%04x ", fw->mailbox_reg[cnt]);
2488 3061 }
2489 3062
2490 3063 mdb_printf("\n\nXSEQ GP Registers");
2491 3064 for (cnt = 0; cnt < sizeof (fw->xseq_gp_reg) / 4; cnt++) {
2492 3065 if (cnt % 8 == 0) {
2493 3066 mdb_printf("\n");
2494 3067 }
2495 3068 mdb_printf("%08x ", fw->xseq_gp_reg[cnt]);
2496 3069 }
2497 3070
2498 3071 mdb_printf("\n\nXSEQ-0 Registers");
2499 3072 for (cnt = 0; cnt < sizeof (fw->xseq_0_reg) / 4; cnt++) {
2500 3073 if (cnt % 8 == 0) {
2501 3074 mdb_printf("\n");
2502 3075 }
2503 3076 mdb_printf("%08x ", fw->xseq_0_reg[cnt]);
2504 3077 }
2505 3078
2506 3079 mdb_printf("\n\nXSEQ-1 Registers");
2507 3080 for (cnt = 0; cnt < sizeof (fw->xseq_1_reg) / 4; cnt++) {
2508 3081 if (cnt % 8 == 0) {
2509 3082 mdb_printf("\n");
2510 3083 }
2511 3084 mdb_printf("%08x ", fw->xseq_1_reg[cnt]);
2512 3085 }
2513 3086
2514 3087 mdb_printf("\n\nRSEQ GP Registers");
2515 3088 for (cnt = 0; cnt < sizeof (fw->rseq_gp_reg) / 4; cnt++) {
2516 3089 if (cnt % 8 == 0) {
2517 3090 mdb_printf("\n");
2518 3091 }
2519 3092 mdb_printf("%08x ", fw->rseq_gp_reg[cnt]);
2520 3093 }
2521 3094
2522 3095 mdb_printf("\n\nRSEQ-0 Registers");
2523 3096 for (cnt = 0; cnt < sizeof (fw->rseq_0_reg) / 4; cnt++) {
2524 3097 if (cnt % 8 == 0) {
2525 3098 mdb_printf("\n");
2526 3099 }
2527 3100 mdb_printf("%08x ", fw->rseq_0_reg[cnt]);
2528 3101 }
2529 3102
2530 3103 mdb_printf("\n\nRSEQ-1 Registers");
2531 3104 for (cnt = 0; cnt < sizeof (fw->rseq_1_reg) / 4; cnt++) {
2532 3105 if (cnt % 8 == 0) {
2533 3106 mdb_printf("\n");
2534 3107 }
2535 3108 mdb_printf("%08x ", fw->rseq_1_reg[cnt]);
2536 3109 }
2537 3110
2538 3111 mdb_printf("\n\nRSEQ-2 Registers");
2539 3112 for (cnt = 0; cnt < sizeof (fw->rseq_2_reg) / 4; cnt++) {
2540 3113 if (cnt % 8 == 0) {
2541 3114 mdb_printf("\n");
2542 3115 }
2543 3116 mdb_printf("%08x ", fw->rseq_2_reg[cnt]);
2544 3117 }
2545 3118
2546 3119 mdb_printf("\n\nASEQ GP Registers");
2547 3120 for (cnt = 0; cnt < sizeof (fw->aseq_gp_reg) / 4; cnt++) {
2548 3121 if (cnt % 8 == 0) {
2549 3122 mdb_printf("\n");
2550 3123 }
2551 3124 mdb_printf("%08x ", fw->aseq_gp_reg[cnt]);
2552 3125 }
2553 3126
2554 3127 mdb_printf("\n\nASEQ-0 GP Registers");
2555 3128 for (cnt = 0; cnt < sizeof (fw->aseq_0_reg) / 4; cnt++) {
2556 3129 if (cnt % 8 == 0) {
2557 3130 mdb_printf("\n");
2558 3131 }
2559 3132
2560 3133 mdb_printf("%08x ", fw->aseq_0_reg[cnt]);
2561 3134 }
2562 3135
2563 3136 mdb_printf("\n\nASEQ-1 GP Registers");
2564 3137 for (cnt = 0; cnt < sizeof (fw->aseq_1_reg) / 4; cnt++) {
2565 3138 if (cnt % 8 == 0) {
2566 3139 mdb_printf("\n");
2567 3140 }
2568 3141
2569 3142 mdb_printf("%08x ", fw->aseq_1_reg[cnt]);
2570 3143 }
2571 3144
2572 3145 mdb_printf("\n\nASEQ-2 GP Registers");
2573 3146 for (cnt = 0; cnt < sizeof (fw->aseq_2_reg) / 4; cnt++) {
2574 3147 if (cnt % 8 == 0) {
2575 3148 mdb_printf("\n");
2576 3149 }
2577 3150 mdb_printf("%08x ", fw->aseq_2_reg[cnt]);
2578 3151 }
2579 3152
2580 3153 mdb_printf("\n\nCommand DMA Registers");
2581 3154 for (cnt = 0; cnt < sizeof (fw->cmd_dma_reg) / 4; cnt++) {
2582 3155 if (cnt % 8 == 0) {
2583 3156 mdb_printf("\n");
2584 3157 }
2585 3158 mdb_printf("%08x ", fw->cmd_dma_reg[cnt]);
2586 3159 }
2587 3160
2588 3161 mdb_printf("\n\nRequest0 Queue DMA Channel Registers");
2589 3162 for (cnt = 0; cnt < sizeof (fw->req0_dma_reg) / 4; cnt++) {
2590 3163 if (cnt % 8 == 0) {
2591 3164 mdb_printf("\n");
2592 3165 }
2593 3166 mdb_printf("%08x ", fw->req0_dma_reg[cnt]);
2594 3167 }
2595 3168
2596 3169 mdb_printf("\n\nResponse0 Queue DMA Channel Registers");
2597 3170 for (cnt = 0; cnt < sizeof (fw->resp0_dma_reg) / 4; cnt++) {
2598 3171 if (cnt % 8 == 0) {
2599 3172 mdb_printf("\n");
2600 3173 }
2601 3174 mdb_printf("%08x ", fw->resp0_dma_reg[cnt]);
2602 3175 }
2603 3176
2604 3177 mdb_printf("\n\nRequest1 Queue DMA Channel Registers");
2605 3178 for (cnt = 0; cnt < sizeof (fw->req1_dma_reg) / 4; cnt++) {
2606 3179 if (cnt % 8 == 0) {
2607 3180 mdb_printf("\n");
2608 3181 }
2609 3182 mdb_printf("%08x ", fw->req1_dma_reg[cnt]);
2610 3183 }
2611 3184
2612 3185 mdb_printf("\n\nXMT0 Data DMA Registers");
2613 3186 for (cnt = 0; cnt < sizeof (fw->xmt0_dma_reg) / 4; cnt++) {
2614 3187 if (cnt % 8 == 0) {
2615 3188 mdb_printf("\n");
2616 3189 }
2617 3190 mdb_printf("%08x ", fw->xmt0_dma_reg[cnt]);
2618 3191 }
2619 3192
2620 3193 mdb_printf("\n\nXMT1 Data DMA Registers");
2621 3194 for (cnt = 0; cnt < sizeof (fw->xmt1_dma_reg) / 4; cnt++) {
2622 3195 if (cnt % 8 == 0) {
2623 3196 mdb_printf("\n");
2624 3197 }
2625 3198 mdb_printf("%08x ", fw->xmt1_dma_reg[cnt]);
2626 3199 }
2627 3200
2628 3201 mdb_printf("\n\nXMT2 Data DMA Registers");
2629 3202 for (cnt = 0; cnt < sizeof (fw->xmt2_dma_reg) / 4; cnt++) {
2630 3203 if (cnt % 8 == 0) {
2631 3204 mdb_printf("\n");
2632 3205 }
2633 3206 mdb_printf("%08x ", fw->xmt2_dma_reg[cnt]);
2634 3207 }
2635 3208
2636 3209 mdb_printf("\n\nXMT3 Data DMA Registers");
2637 3210 for (cnt = 0; cnt < sizeof (fw->xmt3_dma_reg) / 4; cnt++) {
2638 3211 if (cnt % 8 == 0) {
2639 3212 mdb_printf("\n");
2640 3213 }
2641 3214 mdb_printf("%08x ", fw->xmt3_dma_reg[cnt]);
2642 3215 }
2643 3216
2644 3217 mdb_printf("\n\nXMT4 Data DMA Registers");
2645 3218 for (cnt = 0; cnt < sizeof (fw->xmt4_dma_reg) / 4; cnt++) {
2646 3219 if (cnt % 8 == 0) {
2647 3220 mdb_printf("\n");
2648 3221 }
2649 3222 mdb_printf("%08x ", fw->xmt4_dma_reg[cnt]);
2650 3223 }
2651 3224
2652 3225 mdb_printf("\n\nXMT Data DMA Common Registers");
2653 3226 for (cnt = 0; cnt < sizeof (fw->xmt_data_dma_reg) / 4; cnt++) {
2654 3227 if (cnt % 8 == 0) {
2655 3228 mdb_printf("\n");
2656 3229 }
2657 3230 mdb_printf("%08x ", fw->xmt_data_dma_reg[cnt]);
2658 3231 }
2659 3232
2660 3233 mdb_printf("\n\nRCV Thread 0 Data DMA Registers");
2661 3234 for (cnt = 0; cnt < sizeof (fw->rcvt0_data_dma_reg) / 4; cnt++) {
2662 3235 if (cnt % 8 == 0) {
2663 3236 mdb_printf("\n");
2664 3237 }
2665 3238 mdb_printf("%08x ", fw->rcvt0_data_dma_reg[cnt]);
2666 3239 }
2667 3240
2668 3241 mdb_printf("\n\nRCV Thread 1 Data DMA Registers");
2669 3242 for (cnt = 0; cnt < sizeof (fw->rcvt1_data_dma_reg) / 4; cnt++) {
2670 3243 if (cnt % 8 == 0) {
2671 3244 mdb_printf("\n");
2672 3245 }
2673 3246 mdb_printf("%08x ", fw->rcvt1_data_dma_reg[cnt]);
2674 3247 }
2675 3248
2676 3249 mdb_printf("\n\nRISC GP Registers");
2677 3250 for (cnt = 0; cnt < sizeof (fw->risc_gp_reg) / 4; cnt++) {
2678 3251 if (cnt % 8 == 0) {
2679 3252 mdb_printf("\n");
2680 3253 }
2681 3254 mdb_printf("%08x ", fw->risc_gp_reg[cnt]);
2682 3255 }
2683 3256
2684 3257 mdb_printf("\n\nRISC IO Register\n%08x", fw->risc_io);
2685 3258
2686 3259 mdb_printf("\n\nLMC Registers");
2687 3260 for (cnt = 0; cnt < sizeof (fw->lmc_reg) / 4; cnt++) {
2688 3261 if (cnt % 8 == 0) {
2689 3262 mdb_printf("\n");
2690 3263 }
2691 3264 mdb_printf("%08x ", fw->lmc_reg[cnt]);
2692 3265 }
2693 3266
2694 3267 mdb_printf("\n\nFPM Hardware Registers");
2695 3268 for (cnt = 0; cnt < sizeof (fw->fpm_hdw_reg) / 4; cnt++) {
2696 3269 if (cnt % 8 == 0) {
2697 3270 mdb_printf("\n");
2698 3271 }
2699 3272 mdb_printf("%08x ", fw->fpm_hdw_reg[cnt]);
2700 3273 }
2701 3274
2702 3275 mdb_printf("\n\nFB Hardware Registers");
2703 3276 for (cnt = 0; cnt < sizeof (fw->fb_hdw_reg) / 4; cnt++) {
2704 3277 if (cnt % 8 == 0) {
2705 3278 mdb_printf("\n");
2706 3279 }
2707 3280 mdb_printf("%08x ", fw->fb_hdw_reg[cnt]);
2708 3281 }
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2709 3282
2710 3283 mdb_printf("\n\nCode RAM");
2711 3284 for (cnt = 0; cnt < sizeof (fw->code_ram) / 4; cnt++) {
2712 3285 if (cnt % 8 == 0) {
2713 3286 mdb_printf("\n%08x: ", cnt + 0x20000);
2714 3287 }
2715 3288 mdb_printf("%08x ", fw->code_ram[cnt]);
2716 3289 }
2717 3290
2718 3291 mdb_printf("\n\nExternal Memory");
3292 + dp = (uint32_t *)(void *)((caddr_t)fw->req_rsp_ext_mem +
3293 + fw->req_q_size[0] + fw->req_q_size[1] + fw->rsp_q_size +
3294 + (ha->rsp_queues_cnt * 16));
2719 3295 for (cnt = 0; cnt < ha->fw_ext_memory_size / 4; cnt++) {
2720 3296 if (cnt % 8 == 0) {
2721 3297 mdb_printf("\n%08x: ", cnt + 0x100000);
2722 3298 }
2723 - mdb_printf("%08x ", fw->ext_mem[cnt]);
3299 + mdb_printf("%08x ", *dp++);
2724 3300 }
2725 3301
2726 3302 mdb_printf("\n[<==END] ISP Debug Dump");
2727 3303
2728 3304 mdb_printf("\n\nRequest Queue");
2729 3305
2730 - for (cnt = 0; cnt < REQUEST_QUEUE_SIZE / 4; cnt++) {
2731 - if (cnt % 8 == 0) {
2732 - mdb_printf("\n%08x: ", cnt);
3306 + dp = fw->req_rsp_ext_mem + (ha->rsp_queues_cnt * 4);
3307 + for (cnt = 0; cnt < 2 && fw->req_q_size[cnt]; cnt++) {
3308 + dp2 = dp;
3309 + for (cnt1 = 0; cnt1 < fw->req_q_size[cnt] / 4; cnt1++) {
3310 + if (*dp2++) {
3311 + break;
3312 + }
2733 3313 }
2734 - mdb_printf("%08x ", fw->req_q[cnt]);
3314 + if (cnt1 == fw->req_q_size[cnt] / 4) {
3315 + dp = dp2;
3316 + continue;
3317 + }
3318 + mdb_printf("\n\nRequest Queue\nQueue 0%d:", cnt);
3319 + for (cnt1 = 0; cnt1 < fw->req_q_size[cnt] / 4; cnt1++) {
3320 + if (cnt1 % 8 == 0) {
3321 + mdb_printf("\n%08x: ", cnt1);
3322 + }
3323 + mdb_printf("%08x ", *dp++);
3324 + }
2735 3325 }
2736 3326
2737 - mdb_printf("\n\nResponse Queue");
3327 + for (cnt = 0; cnt < ha->rsp_queues_cnt; cnt++) {
3328 + if (mdb_vread(rsp_q, sizeof (ql_response_q_t),
3329 + (uintptr_t)rsp_queues[cnt]) == -1) {
3330 + mdb_warn("failed to read ha->rsp_queues[%d]", cnt);
3331 + break;
3332 + }
3333 + dp2 = dp;
3334 + for (cnt1 = 0; cnt1 < rsp_q->rsp_ring.size / 4; cnt1++) {
3335 + if (*dp2++) {
3336 + break;
3337 + }
3338 + }
3339 + if (cnt1 == rsp_q->rsp_ring.size / 4) {
3340 + dp = dp2;
3341 + continue;
3342 + }
3343 + mdb_printf("\n\nResponse Queue\nQueue 0%d:", cnt);
2738 3344
2739 - for (cnt = 0; cnt < RESPONSE_QUEUE_SIZE / 4; cnt++) {
2740 - if (cnt % 8 == 0) {
2741 - mdb_printf("\n%08x: ", cnt);
3345 + for (cnt1 = 0; cnt1 < rsp_q->rsp_ring.size / 4; cnt1++) {
3346 + if (cnt1 % 8 == 0) {
3347 + mdb_printf("\n%08x: ", cnt1);
3348 + }
3349 + mdb_printf("%08x ", *dp++);
2742 3350 }
2743 - mdb_printf("%08x ", fw->rsp_q[cnt]);
2744 3351 }
2745 3352
2746 3353 if ((ha->cfg_flags & CFG_ENABLE_FWEXTTRACE) &&
2747 3354 (ha->fwexttracebuf.bp != NULL)) {
2748 3355 uint32_t cnt_b = 0;
2749 3356 uint32_t *w32 = ha->fwexttracebuf.bp;
2750 3357
2751 3358 mdb_printf("\n\nExtended Trace Buffer Memory");
2752 3359 /* show data address as a byte address, data as long words */
2753 3360 for (cnt = 0; cnt < FWEXTSIZE / 4; cnt++) {
2754 3361 cnt_b = cnt * 4;
2755 3362 if (cnt_b % 32 == 0) {
2756 3363 mdb_printf("\n%08x: ", w32 + cnt_b);
2757 3364 }
2758 3365 mdb_printf("%08x ", fw->ext_trace_buf[cnt]);
2759 3366 }
2760 3367 }
2761 3368
2762 3369 if ((ha->cfg_flags & CFG_ENABLE_FWFCETRACE) &&
2763 3370 (ha->fwfcetracebuf.bp != NULL)) {
2764 3371 uint32_t cnt_b = 0;
2765 3372 uint32_t *w32 = ha->fwfcetracebuf.bp;
2766 3373
2767 3374 mdb_printf("\n\nFC Event Trace Buffer Memory");
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2768 3375 /* show data address as a byte address, data as long words */
2769 3376 for (cnt = 0; cnt < FWFCESIZE / 4; cnt++) {
2770 3377 cnt_b = cnt * 4;
2771 3378 if (cnt_b % 32 == 0) {
2772 3379 mdb_printf("\n%08x: ", w32 + cnt_b);
2773 3380 }
2774 3381 mdb_printf("%08x ", fw->fce_trace_buf[cnt]);
2775 3382 }
2776 3383 }
2777 3384
3385 + mdb_free(rsp_q, sizeof (ql_response_q_t));
3386 + mdb_free(rsp_queues, ha->rsp_queues_cnt * sizeof (ql_response_q_t *));
2778 3387 mdb_free(fw, ha->ql_dump_size);
2779 3388
2780 3389 mdb_printf("\n\nreturn exit\n");
2781 3390
2782 3391 return (DCMD_OK);
2783 3392 }
2784 3393
2785 3394 /*
2786 3395 * ql_81xx_dump_dcmd
2787 3396 * prints out a firmware dump buffer
2788 3397 *
2789 3398 * Input:
2790 3399 * addr = User supplied address. (NB: nust be an ha)
2791 3400 * flags = mdb flags.
2792 3401 * argc = Number of user supplied args.
2793 3402 * argv = Arg array.
2794 3403 *
2795 3404 * Returns:
2796 3405 * DCMD_OK or DCMD_ERR
2797 3406 *
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2798 3407 * Context:
2799 3408 * User context.
2800 3409 *
2801 3410 */
2802 3411 /*ARGSUSED*/
2803 3412 static int
2804 3413 ql_81xx_dump_dcmd(ql_adapter_state_t *ha, uint_t flags, int argc,
2805 3414 const mdb_arg_t *argv)
2806 3415 {
2807 3416 ql_81xx_fw_dump_t *fw;
2808 - uint32_t cnt = 0;
3417 + ql_response_q_t **rsp_queues, *rsp_q;
3418 + uint32_t cnt, cnt1, *dp, *dp2;
2809 3419
2810 3420 fw = (ql_81xx_fw_dump_t *)mdb_alloc(ha->ql_dump_size, UM_SLEEP);
3421 + rsp_queues = mdb_alloc(ha->rsp_queues_cnt *
3422 + sizeof (ql_response_q_t *), UM_SLEEP);
3423 + rsp_q = mdb_alloc(sizeof (ql_response_q_t), UM_SLEEP);
2811 3424
2812 3425 if (mdb_vread(fw, ha->ql_dump_size,
2813 - (uintptr_t)ha->ql_dump_ptr) == -1) {
3426 + (uintptr_t)ha->ql_dump_ptr) == -1 ||
3427 + mdb_vread(rsp_queues, ha->rsp_queues_cnt *
3428 + sizeof (ql_response_q_t *), (uintptr_t)ha->rsp_queues) == -1) {
2814 3429 mdb_warn("failed to read ql_dump_ptr (no f/w dump active?)");
3430 + mdb_free(rsp_q, sizeof (ql_response_q_t));
3431 + mdb_free(rsp_queues, ha->rsp_queues_cnt *
3432 + sizeof (ql_response_q_t *));
2815 3433 mdb_free(fw, ha->ql_dump_size);
2816 3434 return (DCMD_OK);
2817 3435 }
2818 3436
2819 3437 mdb_printf("\nISP FW Version %d.%02d.%02d Attributes %X\n",
2820 3438 ha->fw_major_version, ha->fw_minor_version,
2821 3439 ha->fw_subminor_version, ha->fw_attributes);
2822 3440
3441 + mdb_printf("\nHCCR Register\n%08x\n", fw->hccr);
3442 +
2823 3443 mdb_printf("\nR2H Register\n%08x\n", fw->r2h_status);
2824 3444
3445 + mdb_printf("\nAER Uncorrectable Error Status Register\n%08x\n",
3446 + fw->aer_ues);
3447 +
2825 3448 mdb_printf("\n\nHostRisc Registers");
2826 3449 for (cnt = 0; cnt < sizeof (fw->hostrisc_reg) / 4; cnt++) {
2827 3450 if (cnt % 8 == 0) {
2828 3451 mdb_printf("\n");
2829 3452 }
2830 3453 mdb_printf("%08x ", fw->hostrisc_reg[cnt]);
2831 3454 }
2832 3455
2833 3456 mdb_printf("\n\nPCIe Registers");
2834 3457 for (cnt = 0; cnt < sizeof (fw->pcie_reg) / 4; cnt++) {
2835 3458 if (cnt % 8 == 0) {
2836 3459 mdb_printf("\n");
2837 3460 }
2838 3461 mdb_printf("%08x ", fw->pcie_reg[cnt]);
2839 3462 }
2840 3463
2841 3464 mdb_printf("\n\nHost Interface Registers");
2842 3465 for (cnt = 0; cnt < sizeof (fw->host_reg) / 4; cnt++) {
2843 3466 if (cnt % 8 == 0) {
2844 3467 mdb_printf("\n");
2845 3468 }
2846 3469 mdb_printf("%08x ", fw->host_reg[cnt]);
2847 3470 }
2848 3471
2849 3472 mdb_printf("\n\nShadow Registers");
2850 3473 for (cnt = 0; cnt < sizeof (fw->shadow_reg) / 4; cnt++) {
2851 3474 if (cnt % 8 == 0) {
2852 3475 mdb_printf("\n");
2853 3476 }
2854 3477
2855 3478 mdb_printf("%08x ", fw->shadow_reg[cnt]);
2856 3479 }
2857 3480
2858 3481 mdb_printf("\n\nMailbox Registers");
2859 3482 for (cnt = 0; cnt < sizeof (fw->mailbox_reg) / 2; cnt++) {
2860 3483 if (cnt % 16 == 0) {
2861 3484 mdb_printf("\n");
2862 3485 }
2863 3486 mdb_printf("%04x ", fw->mailbox_reg[cnt]);
2864 3487 }
2865 3488
2866 3489 mdb_printf("\n\nXSEQ GP Registers");
2867 3490 for (cnt = 0; cnt < sizeof (fw->xseq_gp_reg) / 4; cnt++) {
2868 3491 if (cnt % 8 == 0) {
2869 3492 mdb_printf("\n");
2870 3493 }
2871 3494 mdb_printf("%08x ", fw->xseq_gp_reg[cnt]);
2872 3495 }
2873 3496
2874 3497 mdb_printf("\n\nXSEQ-0 Registers");
2875 3498 for (cnt = 0; cnt < sizeof (fw->xseq_0_reg) / 4; cnt++) {
2876 3499 if (cnt % 8 == 0) {
2877 3500 mdb_printf("\n");
2878 3501 }
2879 3502 mdb_printf("%08x ", fw->xseq_0_reg[cnt]);
2880 3503 }
2881 3504
2882 3505 mdb_printf("\n\nXSEQ-1 Registers");
2883 3506 for (cnt = 0; cnt < sizeof (fw->xseq_1_reg) / 4; cnt++) {
2884 3507 if (cnt % 8 == 0) {
2885 3508 mdb_printf("\n");
2886 3509 }
2887 3510 mdb_printf("%08x ", fw->xseq_1_reg[cnt]);
2888 3511 }
2889 3512
2890 3513 mdb_printf("\n\nRSEQ GP Registers");
2891 3514 for (cnt = 0; cnt < sizeof (fw->rseq_gp_reg) / 4; cnt++) {
2892 3515 if (cnt % 8 == 0) {
2893 3516 mdb_printf("\n");
2894 3517 }
2895 3518 mdb_printf("%08x ", fw->rseq_gp_reg[cnt]);
2896 3519 }
2897 3520
2898 3521 mdb_printf("\n\nRSEQ-0 Registers");
2899 3522 for (cnt = 0; cnt < sizeof (fw->rseq_0_reg) / 4; cnt++) {
2900 3523 if (cnt % 8 == 0) {
2901 3524 mdb_printf("\n");
2902 3525 }
2903 3526 mdb_printf("%08x ", fw->rseq_0_reg[cnt]);
2904 3527 }
2905 3528
2906 3529 mdb_printf("\n\nRSEQ-1 Registers");
2907 3530 for (cnt = 0; cnt < sizeof (fw->rseq_1_reg) / 4; cnt++) {
2908 3531 if (cnt % 8 == 0) {
2909 3532 mdb_printf("\n");
2910 3533 }
2911 3534 mdb_printf("%08x ", fw->rseq_1_reg[cnt]);
2912 3535 }
2913 3536
2914 3537 mdb_printf("\n\nRSEQ-2 Registers");
2915 3538 for (cnt = 0; cnt < sizeof (fw->rseq_2_reg) / 4; cnt++) {
2916 3539 if (cnt % 8 == 0) {
2917 3540 mdb_printf("\n");
2918 3541 }
2919 3542 mdb_printf("%08x ", fw->rseq_2_reg[cnt]);
2920 3543 }
2921 3544
2922 3545 mdb_printf("\n\nASEQ GP Registers");
2923 3546 for (cnt = 0; cnt < sizeof (fw->aseq_gp_reg) / 4; cnt++) {
2924 3547 if (cnt % 8 == 0) {
2925 3548 mdb_printf("\n");
2926 3549 }
2927 3550 mdb_printf("%08x ", fw->aseq_gp_reg[cnt]);
2928 3551 }
2929 3552
2930 3553 mdb_printf("\n\nASEQ-0 GP Registers");
2931 3554 for (cnt = 0; cnt < sizeof (fw->aseq_0_reg) / 4; cnt++) {
2932 3555 if (cnt % 8 == 0) {
2933 3556 mdb_printf("\n");
2934 3557 }
2935 3558
2936 3559 mdb_printf("%08x ", fw->aseq_0_reg[cnt]);
2937 3560 }
2938 3561
2939 3562 mdb_printf("\n\nASEQ-1 GP Registers");
2940 3563 for (cnt = 0; cnt < sizeof (fw->aseq_1_reg) / 4; cnt++) {
2941 3564 if (cnt % 8 == 0) {
2942 3565 mdb_printf("\n");
2943 3566 }
2944 3567
2945 3568 mdb_printf("%08x ", fw->aseq_1_reg[cnt]);
2946 3569 }
2947 3570
2948 3571 mdb_printf("\n\nASEQ-2 GP Registers");
2949 3572 for (cnt = 0; cnt < sizeof (fw->aseq_2_reg) / 4; cnt++) {
2950 3573 if (cnt % 8 == 0) {
2951 3574 mdb_printf("\n");
2952 3575 }
2953 3576 mdb_printf("%08x ", fw->aseq_2_reg[cnt]);
2954 3577 }
2955 3578
2956 3579 mdb_printf("\n\nCommand DMA Registers");
2957 3580 for (cnt = 0; cnt < sizeof (fw->cmd_dma_reg) / 4; cnt++) {
2958 3581 if (cnt % 8 == 0) {
2959 3582 mdb_printf("\n");
2960 3583 }
2961 3584 mdb_printf("%08x ", fw->cmd_dma_reg[cnt]);
2962 3585 }
2963 3586
2964 3587 mdb_printf("\n\nRequest0 Queue DMA Channel Registers");
2965 3588 for (cnt = 0; cnt < sizeof (fw->req0_dma_reg) / 4; cnt++) {
2966 3589 if (cnt % 8 == 0) {
2967 3590 mdb_printf("\n");
2968 3591 }
2969 3592 mdb_printf("%08x ", fw->req0_dma_reg[cnt]);
2970 3593 }
2971 3594
2972 3595 mdb_printf("\n\nResponse0 Queue DMA Channel Registers");
2973 3596 for (cnt = 0; cnt < sizeof (fw->resp0_dma_reg) / 4; cnt++) {
2974 3597 if (cnt % 8 == 0) {
2975 3598 mdb_printf("\n");
2976 3599 }
2977 3600 mdb_printf("%08x ", fw->resp0_dma_reg[cnt]);
2978 3601 }
2979 3602
2980 3603 mdb_printf("\n\nRequest1 Queue DMA Channel Registers");
2981 3604 for (cnt = 0; cnt < sizeof (fw->req1_dma_reg) / 4; cnt++) {
2982 3605 if (cnt % 8 == 0) {
2983 3606 mdb_printf("\n");
2984 3607 }
2985 3608 mdb_printf("%08x ", fw->req1_dma_reg[cnt]);
2986 3609 }
2987 3610
2988 3611 mdb_printf("\n\nXMT0 Data DMA Registers");
2989 3612 for (cnt = 0; cnt < sizeof (fw->xmt0_dma_reg) / 4; cnt++) {
2990 3613 if (cnt % 8 == 0) {
2991 3614 mdb_printf("\n");
2992 3615 }
2993 3616 mdb_printf("%08x ", fw->xmt0_dma_reg[cnt]);
2994 3617 }
2995 3618
2996 3619 mdb_printf("\n\nXMT1 Data DMA Registers");
2997 3620 for (cnt = 0; cnt < sizeof (fw->xmt1_dma_reg) / 4; cnt++) {
2998 3621 if (cnt % 8 == 0) {
2999 3622 mdb_printf("\n");
3000 3623 }
3001 3624 mdb_printf("%08x ", fw->xmt1_dma_reg[cnt]);
3002 3625 }
3003 3626
3004 3627 mdb_printf("\n\nXMT2 Data DMA Registers");
3005 3628 for (cnt = 0; cnt < sizeof (fw->xmt2_dma_reg) / 4; cnt++) {
3006 3629 if (cnt % 8 == 0) {
3007 3630 mdb_printf("\n");
3008 3631 }
3009 3632 mdb_printf("%08x ", fw->xmt2_dma_reg[cnt]);
3010 3633 }
3011 3634
3012 3635 mdb_printf("\n\nXMT3 Data DMA Registers");
3013 3636 for (cnt = 0; cnt < sizeof (fw->xmt3_dma_reg) / 4; cnt++) {
3014 3637 if (cnt % 8 == 0) {
3015 3638 mdb_printf("\n");
3016 3639 }
3017 3640 mdb_printf("%08x ", fw->xmt3_dma_reg[cnt]);
3018 3641 }
3019 3642
3020 3643 mdb_printf("\n\nXMT4 Data DMA Registers");
3021 3644 for (cnt = 0; cnt < sizeof (fw->xmt4_dma_reg) / 4; cnt++) {
3022 3645 if (cnt % 8 == 0) {
3023 3646 mdb_printf("\n");
3024 3647 }
3025 3648 mdb_printf("%08x ", fw->xmt4_dma_reg[cnt]);
3026 3649 }
3027 3650
3028 3651 mdb_printf("\n\nXMT Data DMA Common Registers");
3029 3652 for (cnt = 0; cnt < sizeof (fw->xmt_data_dma_reg) / 4; cnt++) {
3030 3653 if (cnt % 8 == 0) {
3031 3654 mdb_printf("\n");
3032 3655 }
3033 3656 mdb_printf("%08x ", fw->xmt_data_dma_reg[cnt]);
3034 3657 }
3035 3658
3036 3659 mdb_printf("\n\nRCV Thread 0 Data DMA Registers");
3037 3660 for (cnt = 0; cnt < sizeof (fw->rcvt0_data_dma_reg) / 4; cnt++) {
3038 3661 if (cnt % 8 == 0) {
3039 3662 mdb_printf("\n");
3040 3663 }
3041 3664 mdb_printf("%08x ", fw->rcvt0_data_dma_reg[cnt]);
3042 3665 }
3043 3666
3044 3667 mdb_printf("\n\nRCV Thread 1 Data DMA Registers");
3045 3668 for (cnt = 0; cnt < sizeof (fw->rcvt1_data_dma_reg) / 4; cnt++) {
3046 3669 if (cnt % 8 == 0) {
3047 3670 mdb_printf("\n");
3048 3671 }
3049 3672 mdb_printf("%08x ", fw->rcvt1_data_dma_reg[cnt]);
3050 3673 }
3051 3674
3052 3675 mdb_printf("\n\nRISC GP Registers");
3053 3676 for (cnt = 0; cnt < sizeof (fw->risc_gp_reg) / 4; cnt++) {
3054 3677 if (cnt % 8 == 0) {
3055 3678 mdb_printf("\n");
3056 3679 }
3057 3680 mdb_printf("%08x ", fw->risc_gp_reg[cnt]);
3058 3681 }
3059 3682
3060 3683 mdb_printf("\n\nRISC IO Register\n%08x", fw->risc_io);
3061 3684
3062 3685 mdb_printf("\n\nLMC Registers");
3063 3686 for (cnt = 0; cnt < sizeof (fw->lmc_reg) / 4; cnt++) {
3064 3687 if (cnt % 8 == 0) {
3065 3688 mdb_printf("\n");
3066 3689 }
3067 3690 mdb_printf("%08x ", fw->lmc_reg[cnt]);
3068 3691 }
3069 3692
3070 3693 mdb_printf("\n\nFPM Hardware Registers");
3071 3694 for (cnt = 0; cnt < sizeof (fw->fpm_hdw_reg) / 4; cnt++) {
3072 3695 if (cnt % 8 == 0) {
3073 3696 mdb_printf("\n");
3074 3697 }
3075 3698 mdb_printf("%08x ", fw->fpm_hdw_reg[cnt]);
3076 3699 }
3077 3700
3078 3701 mdb_printf("\n\nFB Hardware Registers");
3079 3702 for (cnt = 0; cnt < sizeof (fw->fb_hdw_reg) / 4; cnt++) {
3080 3703 if (cnt % 8 == 0) {
3081 3704 mdb_printf("\n");
3082 3705 }
3083 3706 mdb_printf("%08x ", fw->fb_hdw_reg[cnt]);
3084 3707 }
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3085 3708
3086 3709 mdb_printf("\n\nCode RAM");
3087 3710 for (cnt = 0; cnt < sizeof (fw->code_ram) / 4; cnt++) {
3088 3711 if (cnt % 8 == 0) {
3089 3712 mdb_printf("\n%08x: ", cnt + 0x20000);
3090 3713 }
3091 3714 mdb_printf("%08x ", fw->code_ram[cnt]);
3092 3715 }
3093 3716
3094 3717 mdb_printf("\n\nExternal Memory");
3718 + dp = (uint32_t *)(void *)((caddr_t)fw->req_rsp_ext_mem +
3719 + fw->req_q_size[0] + fw->req_q_size[1] + fw->rsp_q_size +
3720 + (ha->rsp_queues_cnt * 16));
3095 3721 for (cnt = 0; cnt < ha->fw_ext_memory_size / 4; cnt++) {
3096 3722 if (cnt % 8 == 0) {
3097 3723 mdb_printf("\n%08x: ", cnt + 0x100000);
3098 3724 }
3099 - mdb_printf("%08x ", fw->ext_mem[cnt]);
3725 + mdb_printf("%08x ", *dp++);
3100 3726 }
3101 3727
3102 3728 mdb_printf("\n[<==END] ISP Debug Dump");
3103 3729
3104 3730 mdb_printf("\n\nRequest Queue");
3105 3731
3106 - for (cnt = 0; cnt < REQUEST_QUEUE_SIZE / 4; cnt++) {
3107 - if (cnt % 8 == 0) {
3108 - mdb_printf("\n%08x: ", cnt);
3732 + dp = fw->req_rsp_ext_mem + (ha->rsp_queues_cnt * 4);
3733 + for (cnt = 0; cnt < 2 && fw->req_q_size[cnt]; cnt++) {
3734 + dp2 = dp;
3735 + for (cnt1 = 0; cnt1 < fw->req_q_size[cnt] / 4; cnt1++) {
3736 + if (*dp2++) {
3737 + break;
3738 + }
3109 3739 }
3110 - mdb_printf("%08x ", fw->req_q[cnt]);
3740 + if (cnt1 == fw->req_q_size[cnt] / 4) {
3741 + dp = dp2;
3742 + continue;
3743 + }
3744 + mdb_printf("\n\nRequest Queue\nQueue 0%d:", cnt);
3745 + for (cnt1 = 0; cnt1 < fw->req_q_size[cnt] / 4; cnt1++) {
3746 + if (cnt1 % 8 == 0) {
3747 + mdb_printf("\n%08x: ", cnt1);
3748 + }
3749 + mdb_printf("%08x ", *dp++);
3750 + }
3111 3751 }
3112 3752
3113 - mdb_printf("\n\nResponse Queue");
3753 + for (cnt = 0; cnt < ha->rsp_queues_cnt; cnt++) {
3754 + if (mdb_vread(rsp_q, sizeof (ql_response_q_t),
3755 + (uintptr_t)rsp_queues[cnt]) == -1) {
3756 + mdb_warn("failed to read ha->rsp_queues[%d]", cnt);
3757 + break;
3758 + }
3759 + dp2 = dp;
3760 + for (cnt1 = 0; cnt1 < rsp_q->rsp_ring.size / 4; cnt1++) {
3761 + if (*dp2++) {
3762 + break;
3763 + }
3764 + }
3765 + if (cnt1 == rsp_q->rsp_ring.size / 4) {
3766 + dp = dp2;
3767 + continue;
3768 + }
3769 + mdb_printf("\n\nResponse Queue\nQueue 0%d:", cnt);
3114 3770
3115 - for (cnt = 0; cnt < RESPONSE_QUEUE_SIZE / 4; cnt++) {
3116 - if (cnt % 8 == 0) {
3117 - mdb_printf("\n%08x: ", cnt);
3771 + for (cnt1 = 0; cnt1 < rsp_q->rsp_ring.size / 4; cnt1++) {
3772 + if (cnt1 % 8 == 0) {
3773 + mdb_printf("\n%08x: ", cnt1);
3774 + }
3775 + mdb_printf("%08x ", *dp++);
3118 3776 }
3119 - mdb_printf("%08x ", fw->rsp_q[cnt]);
3120 3777 }
3121 3778
3122 3779 if ((ha->cfg_flags & CFG_ENABLE_FWEXTTRACE) &&
3123 3780 (ha->fwexttracebuf.bp != NULL)) {
3124 3781 uint32_t cnt_b = 0;
3125 3782 uint32_t *w32 = ha->fwexttracebuf.bp;
3126 3783
3127 3784 mdb_printf("\n\nExtended Trace Buffer Memory");
3128 3785 /* show data address as a byte address, data as long words */
3129 3786 for (cnt = 0; cnt < FWEXTSIZE / 4; cnt++) {
3130 3787 cnt_b = cnt * 4;
3131 3788 if (cnt_b % 32 == 0) {
3132 3789 mdb_printf("\n%08x: ", w32 + cnt_b);
3133 3790 }
3134 3791 mdb_printf("%08x ", fw->ext_trace_buf[cnt]);
3135 3792 }
3136 3793 }
3137 3794
3138 3795 if ((ha->cfg_flags & CFG_ENABLE_FWFCETRACE) &&
3139 3796 (ha->fwfcetracebuf.bp != NULL)) {
3140 3797 uint32_t cnt_b = 0;
3141 3798 uint32_t *w32 = ha->fwfcetracebuf.bp;
3142 3799
3143 3800 mdb_printf("\n\nFC Event Trace Buffer Memory");
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3144 3801 /* show data address as a byte address, data as long words */
3145 3802 for (cnt = 0; cnt < FWFCESIZE / 4; cnt++) {
3146 3803 cnt_b = cnt * 4;
3147 3804 if (cnt_b % 32 == 0) {
3148 3805 mdb_printf("\n%08x: ", w32 + cnt_b);
3149 3806 }
3150 3807 mdb_printf("%08x ", fw->fce_trace_buf[cnt]);
3151 3808 }
3152 3809 }
3153 3810
3811 + mdb_free(rsp_q, sizeof (ql_response_q_t));
3812 + mdb_free(rsp_queues, ha->rsp_queues_cnt * sizeof (ql_response_q_t *));
3154 3813 mdb_free(fw, ha->ql_dump_size);
3155 3814
3156 3815 mdb_printf("\n\nreturn exit\n");
3157 3816
3158 3817 return (DCMD_OK);
3159 3818 }
3160 3819
3161 3820 /*
3162 3821 * ql_gettrace_dcmd
3163 3822 * prints out the Extended Logging trace buffer
3164 3823 *
3165 3824 * Input:
3166 3825 * addr = User supplied address. (NB: must be an ha)
3167 3826 * flags = mdb flags.
3168 3827 * argc = Number of user supplied args.
3169 3828 * argv = Arg array.
3170 3829 *
3171 3830 * Returns:
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3172 3831 * DCMD_OK or DCMD_ERR
3173 3832 *
3174 3833 * Context:
3175 3834 * User context.
3176 3835 *
3177 3836 */
3178 3837 static int
3179 3838 qlc_gettrace_dcmd(uintptr_t addr, uint_t flags, int argc, const mdb_arg_t *argv)
3180 3839 {
3181 3840 ql_adapter_state_t *ha;
3182 - int verbose = 0;
3183 - int wrapped = 0;
3184 - char *trace_start;
3185 - char *trace_end;
3186 - char *dump_start = 0;
3187 - char *trace_next = 0;
3188 - char *dump_current = 0;
3189 - el_trace_desc_t *trace_desc;
3841 + ql_trace_desc_t *trace_desc;
3842 + ql_trace_entry_t entry;
3843 + uint32_t i = 0;
3844 + char merge[1024];
3190 3845
3191 3846 if ((!(flags & DCMD_ADDRSPEC)) || addr == NULL) {
3192 3847 mdb_warn("ql_adapter_state structure addr is required");
3193 3848 return (DCMD_USAGE);
3194 3849 }
3195 3850
3196 - if (mdb_getopts(argc, argv, 'v', MDB_OPT_SETBITS, TRUE, &verbose) !=
3197 - argc) {
3851 + if (argc != 0) {
3198 3852 return (DCMD_USAGE);
3199 3853 }
3200 3854
3855 + if (mdb_getopts(argc, argv) != argc) {
3856 + return (DCMD_USAGE);
3857 + }
3858 +
3201 3859 /*
3202 3860 * Get the adapter state struct which was passed
3203 3861 */
3204 3862 if ((ha = (ql_adapter_state_t *)mdb_alloc(sizeof (ql_adapter_state_t),
3205 3863 UM_SLEEP)) == NULL) {
3206 3864 mdb_warn("failed to allocate memory for ql_adapter_state\n");
3207 3865 return (DCMD_OK);
3208 3866 }
3209 3867
3210 3868 if (mdb_vread(ha, sizeof (ql_adapter_state_t), addr) == -1) {
3211 3869 mdb_warn("failed to read ql_adapter_state at %p", addr);
3212 3870 mdb_free(ha, sizeof (ql_adapter_state_t));
3213 3871 return (DCMD_OK);
3214 3872 }
3215 3873
3216 - /*
3217 - * If its not a valid trace descriptor then bail out
3218 - */
3219 - if (ha->el_trace_desc == NULL) {
3874 + if (ha->ql_trace_desc == NULL) {
3220 3875 mdb_warn("trace descriptor does not exist for instance %d\n",
3221 3876 ha->instance);
3222 3877 mdb_free(ha, sizeof (ql_adapter_state_t));
3223 3878 return (DCMD_OK);
3879 +
3224 3880 } else {
3225 - trace_desc = (el_trace_desc_t *)
3226 - mdb_alloc(sizeof (el_trace_desc_t), UM_SLEEP);
3227 - if (mdb_vread(trace_desc, sizeof (el_trace_desc_t),
3228 - (uintptr_t)ha->el_trace_desc) == -1) {
3881 + trace_desc = (ql_trace_desc_t *)
3882 + mdb_alloc(sizeof (ql_trace_desc_t), UM_SLEEP);
3883 +
3884 + if (mdb_vread(trace_desc, sizeof (ql_trace_desc_t),
3885 + (uintptr_t)ha->ql_trace_desc) == -1) {
3229 3886 mdb_warn("failed to read ql_adapter_state at %p",
3230 3887 addr);
3231 - mdb_free(trace_desc, sizeof (el_trace_desc_t));
3888 + mdb_free(trace_desc, sizeof (ql_trace_desc_t));
3232 3889 mdb_free(ha, sizeof (ql_adapter_state_t));
3233 3890 return (DCMD_OK);
3234 3891 }
3892 +
3235 3893 if (trace_desc->trace_buffer == NULL) {
3236 3894 mdb_warn("trace buffer does not exist for "
3237 3895 "instance %d\n", ha->instance);
3238 - mdb_free(trace_desc, sizeof (el_trace_desc_t));
3896 +
3897 + mdb_free(trace_desc, sizeof (ql_trace_desc_t));
3239 3898 mdb_free(ha, sizeof (ql_adapter_state_t));
3240 3899 return (DCMD_OK);
3241 3900 }
3242 3901 }
3243 3902
3244 - /* Get the trace buffer */
3245 -
3246 - trace_start = (char *)
3247 - mdb_zalloc(trace_desc->trace_buffer_size, UM_SLEEP);
3248 -
3249 - if (mdb_vread(trace_start, trace_desc->trace_buffer_size,
3250 - (uintptr_t)trace_desc->trace_buffer) == -1) {
3251 - mdb_warn("failed to read trace buffer?)");
3252 - mdb_free(trace_start, trace_desc->trace_buffer_size);
3903 + /* Check if anything logged or not */
3904 + if (trace_desc->csize == 0) {
3905 + mdb_warn("Extended log buffer is empty.\n");
3906 + mdb_free(trace_desc, sizeof (ql_trace_desc_t));
3253 3907 mdb_free(ha, sizeof (ql_adapter_state_t));
3254 3908 return (DCMD_OK);
3255 3909 }
3256 3910
3257 - /* set the end of the trace buffer. */
3258 - trace_end = trace_start + trace_desc->trace_buffer_size;
3259 -
3260 - /* Find the start point of trace. */
3261 - trace_next = trace_start + trace_desc->next;
3262 -
3263 3911 /*
3264 - * If the buffer has not wrapped next will point at a null so
3265 - * start is the begining of the buffer. If next points at a char
3266 - * then we must traverse the buffer further until a null is detected.
3267 - * The location after the null will be the beginning of the oldest
3268 - * whole object in the buffer, which we use as the start.
3912 + * Locate the start and end point. If ever wrapped, then
3913 + * always print from start to end in the circular buffer
3269 3914 */
3270 3915
3271 - if ((trace_next + EL_BUFFER_RESERVE) >= trace_end) {
3272 - dump_start = trace_start;
3273 - } else if (*trace_next != NULL) {
3274 - dump_start = trace_next + (strlen(trace_next) + 1);
3275 - } else {
3276 - dump_start = trace_start;
3916 + /* always print from start to end */
3917 + for (i = trace_desc->start; i < trace_desc->csize; i++) {
3918 + if (mdb_vread(&entry, sizeof (ql_trace_entry_t),
3919 + (uintptr_t)&trace_desc->trace_buffer[i]) !=
3920 + sizeof (ql_trace_entry_t)) {
3921 + mdb_warn("Cannot read trace entry. %xh", i);
3922 + mdb_free(trace_desc, sizeof (ql_trace_desc_t));
3923 + mdb_free(ha, sizeof (ql_adapter_state_t));
3924 + return (DCMD_ERR);
3925 + }
3926 + if (entry.buf[0] != 0) {
3927 + (void) mdb_snprintf(merge, sizeof (merge),
3928 + "[%Y:%03d:%03d:%03d] "
3929 + "%s",
3930 + entry.hs_time.tv_sec,
3931 + (int)entry.hs_time.tv_nsec / 1000000,
3932 + (int)(entry.hs_time.tv_nsec / 1000) % 1000,
3933 + (int)entry.hs_time.tv_nsec % 1000,
3934 + entry.buf + 1);
3935 + }
3936 + mdb_printf("%s", merge);
3277 3937 }
3278 3938
3279 - dump_current = dump_start;
3280 -
3281 - mdb_printf("\nExtended Logging trace buffer @%x, start @%x, "
3282 - "size=%d\n\n", trace_start, dump_current,
3283 - trace_desc->trace_buffer_size);
3284 -
3285 - /* Don't run off the end, no matter what. */
3286 - while (((uintptr_t)dump_current - (uintptr_t)trace_start) <=
3287 - (uintptr_t)trace_desc->trace_buffer_size) {
3288 - /* Show it... */
3289 - mdb_printf("%s", dump_current);
3290 - /* Calculate the next and make it the current */
3291 - dump_current += (strlen(dump_current) + 1);
3292 - /* check for wrap */
3293 - if ((dump_current + EL_BUFFER_RESERVE) >= trace_end) {
3294 - mdb_printf("Wraping %x\n", dump_current);
3295 - dump_current = trace_start;
3296 - wrapped = 1;
3297 - } else if (wrapped) {
3298 - /* Don't go past next. */
3299 - if ((trace_start + trace_desc->next) <= dump_current) {
3300 - mdb_printf("Done %x", dump_current);
3301 - break;
3939 + if (trace_desc->start != 0) {
3940 + for (i = 0; i < trace_desc->start; i++) {
3941 + if (mdb_vread(&entry, sizeof (ql_trace_entry_t),
3942 + (uintptr_t)&trace_desc->trace_buffer[i]) !=
3943 + sizeof (ql_trace_entry_t)) {
3944 + mdb_warn("Cannot read trace entry. %xh", i);
3945 + mdb_free(trace_desc, sizeof (ql_trace_desc_t));
3946 + mdb_free(ha, sizeof (ql_adapter_state_t));
3947 + return (DCMD_ERR);
3302 3948 }
3303 - } else if (*dump_current == NULL) {
3304 - mdb_printf("Done %x(null)", dump_current);
3305 - break;
3949 + if (entry.buf[0] != 0) {
3950 + (void) mdb_snprintf(merge, sizeof (merge),
3951 + "[%Y:%03d:%03d:%03d] "
3952 + "%s",
3953 + entry.hs_time.tv_sec,
3954 + (int)entry.hs_time.tv_nsec / 1000000,
3955 + (int)(entry.hs_time.tv_nsec / 1000) % 1000,
3956 + (int)entry.hs_time.tv_nsec % 1000,
3957 + entry.buf + 1);
3958 + }
3959 + mdb_printf("%s", merge);
3306 3960 }
3307 3961 }
3308 3962
3963 + mdb_printf("\n");
3964 + mdb_free(trace_desc, sizeof (ql_trace_desc_t));
3309 3965 mdb_free(ha, sizeof (ql_adapter_state_t));
3310 - mdb_free(trace_start, trace_desc->trace_buffer_size);
3311 - mdb_free(trace_desc, sizeof (el_trace_desc_t));
3312 -
3313 3966 return (DCMD_OK);
3314 3967 }
3968 +
3315 3969 /*
3316 3970 * ql_doprint
3317 3971 * ql generic function to call the print dcmd
3318 3972 *
3319 3973 * Input:
3320 3974 * addr - address to struct
3321 3975 * prtsting - address to string
3322 3976 *
3323 3977 * Returns:
3324 3978 * WALK_DONE
3325 3979 *
3326 3980 * Context:
3327 3981 * User context.
3328 3982 *
3329 3983 */
3330 3984 static int32_t
3331 3985 ql_doprint(uintptr_t addr, int8_t *prtstring)
3332 3986 {
3333 3987 struct mdb_arg printarg;
3334 3988
3335 3989 printarg.a_un.a_str = (int8_t *)(mdb_zalloc(strlen(prtstring),
3336 3990 UM_SLEEP));
3337 3991 printarg.a_type = MDB_TYPE_STRING;
3338 3992 (void) strcpy((int8_t *)(printarg.a_un.a_str), prtstring);
3339 3993
3340 3994 if ((mdb_call_dcmd("print", addr, DCMD_ADDRSPEC, 1,
3341 3995 &printarg)) == -1) {
3342 3996 mdb_warn("ql_doprint: failed print dcmd: %s"
3343 3997 "at addr: %llxh", prtstring, addr);
3344 3998 }
3345 3999
3346 4000 mdb_free((void *)(printarg.a_un.a_str), strlen(prtstring));
3347 4001 return (WALK_DONE);
3348 4002 }
3349 4003
3350 4004 /*
3351 4005 * ql_dump_flags
3352 4006 * mdb utility to print the flag string
3353 4007 *
3354 4008 * Input:
3355 4009 * flags - flags to print
3356 4010 * strings - text to print when flag is set
3357 4011 *
3358 4012 * Returns:
3359 4013 *
3360 4014 *
3361 4015 * Context:
3362 4016 * User context.
3363 4017 *
3364 4018 */
3365 4019 static void
3366 4020 ql_dump_flags(uint64_t flags, int8_t **strings)
3367 4021 {
3368 4022 int i, linel, first = 1;
3369 4023 uint64_t mask = 1;
3370 4024
3371 4025 linel = 8;
3372 4026 mdb_printf("\t");
3373 4027 for (i = 0; i < 64; i++) {
3374 4028 if (strings[i] == NULL)
3375 4029 break;
3376 4030 if (flags & mask) {
3377 4031 if (!first) {
3378 4032 mdb_printf(" | ");
3379 4033 } else {
3380 4034 first = 0;
3381 4035 }
3382 4036 linel += (int32_t)strlen(strings[i]) + 3;
3383 4037 if (linel > 80) {
3384 4038 mdb_printf("\n\t");
3385 4039 linel = (int32_t)strlen(strings[i]) + 1 + 8;
3386 4040 }
3387 4041 mdb_printf("%s", strings[i]);
3388 4042 }
3389 4043 mask <<= 1;
3390 4044 }
3391 4045 mdb_printf("\n");
3392 4046 }
3393 4047
3394 4048 /*
3395 4049 * MDB module linkage information
3396 4050 *
3397 4051 *
3398 4052 * dcmd structures for the _mdb_init function
3399 4053 */
3400 4054 static const mdb_dcmd_t dcmds[] = {
3401 4055 { "qlclinks", NULL, "Prints qlc link information", qlclinks_dcmd },
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3402 4056 { "qlcosc", NULL, "Prints outstanding cmd info", qlc_osc_dcmd },
3403 4057 { "qlcver", NULL, "Prints driver/mdb version", qlcver_dcmd },
3404 4058 { "qlc_elog", "[on|off] [<inst #>|all]", "Turns qlc extended logging "
3405 4059 "on / off", qlc_el_dcmd },
3406 4060 { "qlcstate", ":[-v]", "Prints qlc adapter state information",
3407 4061 qlcstate_dcmd },
3408 4062 { "qlctgtq", NULL, "Prints qlc target queues", qltgtq_dcmd },
3409 4063 { "qlcwdog", NULL, "Prints out watchdog linked list", qlc_wdog_dcmd},
3410 4064 { "qlcgetdump", ":[-v]", "Retrieves the ASCII f/w dump",
3411 4065 qlc_getdump_dcmd },
3412 - { "qlcgettrace", ":[-v]", "Retrieves the ASCII Extended Logging trace",
4066 + { "qlcgettrace", ":", "Retrieves the ASCII Extended Logging trace",
3413 4067 qlc_gettrace_dcmd },
3414 4068 { NULL }
3415 4069 };
3416 4070
3417 4071 /*
3418 4072 * walker structures for the _mdb_init function
3419 4073 */
3420 4074 static const mdb_walker_t walkers[] = {
3421 4075 { "qlcstates", "walk list of qlc ql_state_t structures",
3422 4076 qlstates_walk_init, qlstates_walk_step, qlstates_walk_fini },
3423 4077 { "qlcsrbs", "walk list of qlc ql_srb_t strctures",
3424 4078 qlsrb_walk_init, qlsrb_walk_step, qlsrb_walk_fini },
3425 4079 { "qlclunq", "walk list of qlc ql_lun_t strctures",
3426 4080 qllunq_walk_init, qllunq_walk_step, qllunq_walk_fini },
3427 4081 { NULL }
3428 4082 };
3429 4083
3430 4084 static const mdb_modinfo_t ql_mdb_modinfo = {
3431 4085 MDB_API_VERSION, dcmds, walkers
3432 4086 };
3433 4087
3434 4088 /*
3435 4089 * Registration function which lists the dcmds and walker structures
3436 4090 */
3437 4091 const mdb_modinfo_t *
3438 4092 _mdb_init(void)
3439 4093 {
3440 4094 return (&ql_mdb_modinfo);
3441 4095 }
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