2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /* Copyright 2010 QLogic Corporation */
23
24 /*
25 * ISP2xxx Solaris Fibre Channel Adapter (FCA) qlc mdb source file.
26 *
27 * ***********************************************************************
28 * * **
29 * * NOTICE **
30 * * COPYRIGHT (C) 1996-2010 QLOGIC CORPORATION **
31 * * ALL RIGHTS RESERVED **
32 * * **
33 * ***********************************************************************
34 *
35 */
36
37 #pragma ident "Copyright 2010 QLogic Corporation; ql_mdb.c"
38
39 #include <sys/mdb_modapi.h>
40 #include <ql_apps.h>
41 #include <ql_api.h>
42 #include <ql_init.h>
43 #include <ql_debug.h>
44
45 /*
46 * local prototypes
47 */
48 static int32_t ql_doprint(uintptr_t, int8_t *);
49 static void ql_dump_flags(uint64_t, int8_t **);
50 static int qlclinks_dcmd(uintptr_t, uint_t, int, const mdb_arg_t *);
51 static int qlcstate_dcmd(uintptr_t, uint_t, int, const mdb_arg_t *);
52 static int qlc_osc_dcmd(uintptr_t, uint_t, int, const mdb_arg_t *);
53 static int qlc_wdog_dcmd(uintptr_t, uint_t, int, const mdb_arg_t *);
54 static int qlc_getdump_dcmd(uintptr_t, uint_t, int, const mdb_arg_t *);
55 static int qlc_gettrace_dcmd(uintptr_t, uint_t, int, const mdb_arg_t *);
56 #if 0
57 static int qlc_triggerdump_dcmd(uintptr_t, uint_t, int, const mdb_arg_t *);
58 #endif
59 static int qlcver_dcmd(uintptr_t, uint_t, int, const mdb_arg_t *);
60 static int qlstates_walk_init(mdb_walk_state_t *);
61 static int qlstates_walk_step(mdb_walk_state_t *);
62 static void qlstates_walk_fini(mdb_walk_state_t *);
63 static int qlsrb_walk_init(mdb_walk_state_t *);
64 static int qlsrb_walk_step(mdb_walk_state_t *);
65 static void qlsrb_walk_fini(mdb_walk_state_t *);
66 static int get_next_link(ql_link_t *);
67 static int get_first_link(ql_head_t *, ql_link_t *);
68
69 static int ql_24xx_dump_dcmd(ql_adapter_state_t *, uint_t, int,
70 const mdb_arg_t *);
71 static int ql_23xx_dump_dcmd(ql_adapter_state_t *, uint_t, int,
72 const mdb_arg_t *);
73 static int ql_25xx_dump_dcmd(ql_adapter_state_t *, uint_t, int,
74 const mdb_arg_t *);
75 static int ql_81xx_dump_dcmd(ql_adapter_state_t *, uint_t, int,
76 const mdb_arg_t *);
77 static void ql_elog_common(ql_adapter_state_t *, boolean_t);
78
79 /*
80 * local adapter state flags strings
81 */
82 int8_t *adapter_state_flags[] = {
83 "FCA_BOUND",
84 "QL_OPENED",
85 "ONLINE",
86 "INTERRUPTS_ENABLED",
87 "ABORT_CMDS_LOOP_DOWN_TMO",
88 "POINT_TO_POINT",
89 "IP_ENABLED",
90 "IP_INITIALIZED",
91 "MENLO_LOGIN_OPERATIONAL",
92 "ADAPTER_SUSPENDED",
93 "ADAPTER_TIMER_BUSY",
94 "PARITY_ERROR",
95 "FLASH_ERRLOG_MARKER",
96 "VP_ENABLED",
97 "FDISC_ENABLED",
98 "FUNCTION_1",
99 "MPI_RESET_NEEDED",
100 NULL
101 };
102
103 int8_t *adapter_config_flags[] = {
104 "ENABLE_HARD_ADDRESS",
105 "ENABLE_64BIT_ADDRESSING",
106 "ENABLE_LIP_RESET",
107 "ENABLE_FULL_LIP_LOGIN",
108 "ENABLE_TARGET_RESET",
109 "ENABLE_LINK_DOWN_REPORTING",
110 "DISABLE_EXTENDED_LOGGING_TRACE",
111 "ENABLE_FCP_2_SUPPORT",
112 "MULTI_CHIP_ADAPTER",
113 "SBUS_CARD",
114 "CTRL_2300",
115 "CTRL_6322",
116 "CTRL_2200",
117 "CTRL_2422",
118 "CTRL_25XX",
119 "ENABLE_EXTENDED_LOGGING",
120 "DISABLE_RISC_CODE_LOAD",
121 "SET_CACHE_LINE_SIZE_1",
122 "CTRL_MENLO",
123 "EXT_FW_INTERFACE",
124 "LOAD_FLASH_FW",
125 "DUMP_MAILBOX_TIMEOUT",
126 "DUMP_ISP_SYSTEM_ERROR",
127 "DUMP_DRIVER_COMMAND_TIMEOUT",
128 "DUMP_LOOP_OFFLINE_TIMEOUT",
129 "ENABLE_FWEXTTRACE",
130 "ENABLE_FWFCETRACE",
131 "FW_MISMATCH",
132 "CTRL_81XX",
133 "CTRL_8021",
134 "ENABLE_FAST_TIMEOUT",
135 "LR_SUPPORT",
136 NULL
137 };
138
139 /*
140 * local task daemon flags strings
141 */
142 int8_t *task_daemon_flags[] = {
143 "TASK_DAEMON_STOP_FLG",
144 "TASK_DAEMON_SLEEPING_FLG",
145 "TASK_DAEMON_ALIVE_FLG",
146 "TASK_DAEMON_IDLE_CHK_FLG",
147 "SUSPENDED_WAKEUP_FLG",
148 "FC_STATE_CHANGE",
149 "NEED_UNSOLICITED_BUFFERS",
150 "RESET_MARKER_NEEDED",
151 "RESET_ACTIVE",
152 "ISP_ABORT_NEEDED",
153 "ABORT_ISP_ACTIVE",
154 "LOOP_RESYNC_NEEDED",
155 "LOOP_RESYNC_ACTIVE",
156 "LOOP_DOWN",
157 "DRIVER_STALL",
158 "COMMAND_WAIT_NEEDED",
159 "COMMAND_WAIT_ACTIVE",
160 "STATE_ONLINE",
161 "ABORT_QUEUES_NEEDED",
162 "TASK_DAEMON_STALLED_FLG",
163 "TASK_THREAD_CALLED",
164 "FIRMWARE_UP",
165 "LIP_RESET_PENDING",
166 "FIRMWARE_LOADED",
167 "RSCN_UPDATE_NEEDED",
168 "HANDLE_PORT_BYPASS_CHANGE",
169 "PORT_RETRY_NEEDED",
170 "TASK_DAEMON_POWERING_DOWN",
171 "TD_IIDMA_NEEDED",
172 "SEND_PLOGI",
173 "IDC_EVENT",
174 NULL
175 };
176
177 /*
178 * local interrupt aif flags
179 */
180 int8_t *aif_flags[] = {
181 "IFLG_INTR_LEGACY",
182 "IFLG_INTR_FIXED",
183 "IFLG_INTR_MSI",
184 "IFLG_INTR_MSIX",
185 NULL
186 };
187
188 int8_t *qlsrb_flags[] = {
189 "SRB_ISP_STARTED",
190 "SRB_ISP_COMPLETED",
191 "SRB_RETRY",
192 "SRB_POLL",
193 "SRB_WATCHDOG_ENABLED",
194 "SRB_ABORT",
195 "SRB_UB_IN_FCA",
196 "SRB_UB_IN_ISP",
197 "SRB_UB_CALLBACK",
198 "SRB_UB_RSCN",
199 "SRB_UB_FCP",
200 "SRB_FCP_CMD_PKT",
201 "SRB_FCP_DATA_PKT",
202 "SRB_FCP_RSP_PKT",
203 "SRB_IP_PKT",
204 "SRB_GENERIC_SERVICES_PKT",
205 "SRB_COMMAND_TIMEOUT",
206 "SRB_ABORTING",
207 "SRB_IN_DEVICE_QUEUE",
208 "SRB_IN_TOKEN_ARRAY",
209 "SRB_UB_FREE_REQUESTED",
210 "SRB_UB_ACQUIRED",
211 "SRB_MS_PKT",
212 NULL
213 };
214
215 int8_t *qllun_flags[] = {
216 "LQF_UNTAGGED_PENDING",
217 NULL
218 };
219
220 int8_t *qltgt_flags[] = {
221 "TQF_TAPE_DEVICE",
222 "TQF_QUEUE_SUSPENDED",
223 "TQF_FABRIC_DEVICE",
224 "TQF_INITIATOR_DEVICE",
225 "TQF_RSCN_RCVD",
226 "TQF_NEED_AUTHENTICATION",
227 "TQF_PLOGI_PROGRS",
228 "TQF_IIDMA_NEEDED",
229 NULL
230 };
231
232 int8_t *qldump_flags[] = {
233 "QL_DUMPING",
234 "QL_DUMP_VALID",
235 "QL_DUMP_UPLOADED",
236 NULL
237 };
238
239 /*
240 * qlclinks_dcmd
241 * mdb dcmd which prints out the ql_hba pointers
242 *
243 * Input:
244 * addr = User supplied address -- error if supplied.
245 * flags = mdb flags.
246 * argc = Number of user supplied args -- error if non-zero.
247 * argv = Arg array.
248 *
253 * User context.
254 *
255 */
256 /*ARGSUSED*/
257 static int
258 qlclinks_dcmd(uintptr_t addr, uint_t flags, int argc, const mdb_arg_t *argv)
259 {
260 ql_head_t ql_hba;
261 ql_adapter_state_t *qlstate;
262 uintptr_t hbaptr = NULL;
263
264 if ((flags & DCMD_ADDRSPEC) || argc != 0) {
265 return (DCMD_USAGE);
266 }
267
268 if (mdb_readvar(&ql_hba, "ql_hba") == -1) {
269 mdb_warn("failed to read ql_hba structure");
270 return (DCMD_ERR);
271 }
272
273 if (&ql_hba == NULL) {
274 mdb_warn("failed to read ql_hba structure -- is qlc loaded?");
275 return (DCMD_ERR);
276 }
277
278 mdb_printf("\nqlc adapter state linkages (f=0x%llx, l=0x%llx)\n\n",
279 ql_hba.first, ql_hba.last);
280
281 if ((qlstate = (ql_adapter_state_t *)mdb_alloc(
282 sizeof (ql_adapter_state_t), UM_SLEEP)) == NULL) {
283 mdb_warn("Unable to allocate memory for ql_adapter_state\n");
284 return (DCMD_OK);
285 }
286
287 (void) mdb_inc_indent((ulong_t)4);
288 mdb_printf("%<u>%-?s\t%-45s%</u>\n\n", "baseaddr", "instance");
289
290 hbaptr = (uintptr_t)ql_hba.first;
291 while (hbaptr != NULL) {
292
293 if (mdb_vread(qlstate, sizeof (ql_adapter_state_t),
428 "ql_adapter_state\n");
429 return (DCMD_OK);
430 }
431
432 mdb_printf("\n%-8s%-11s%s\n", "f/w", "compiled", "loaded");
433 mdb_printf("%<u>%-8s%-11s%-13s%s%</u>\n\n", "class", "version",
434 "version", "instance list");
435
436 for (fwt = &fw_table[0]; fwt->fw_class; fwt++) {
437
438 if (mdb_vread(fwverptr, sizeof (void *),
439 (uintptr_t)fwt->fw_version) == -1) {
440 mdb_warn("unable to read fwverptr\n");
441 mdb_free(fwverptr, sizeof (void *));
442 mdb_free(qlstate, sizeof (ql_adapter_state_t));
443 return (DCMD_OK);
444 }
445
446 mdb_printf("%x\t%-11s", fwt->fw_class, fwverptr);
447
448 if (&ql_hba == NULL) {
449 mdb_warn("failed to read ql_hba structure");
450 hbaptr = NULL;
451 } else {
452 hbaptr = (uintptr_t)ql_hba.first;
453 }
454
455 found = 0;
456 while (hbaptr != NULL) {
457
458 if (mdb_vread(qlstate,
459 sizeof (ql_adapter_state_t), hbaptr) ==
460 -1) {
461 mdb_warn("failed to read "
462 "ql_adapter_state at %p", hbaptr);
463 break;
464 }
465
466 if (qlstate->fw_class == fwt->fw_class) {
467 if (found == 0) {
468 mdb_printf("%x.%02x.%02x\t",
552 mdb_printf("\tqlc mdb library compiled version is: %s\n",
553 QL_VERSION);
554 mdb_printf("\tqlc driver version is: %s\n", qlcversion);
555
556 return (DCMD_OK);
557 }
558
559 if ((strcasecmp(argv[0].a_un.a_str, "on")) == 0) {
560 elswitch = TRUE;
561 } else if ((strcasecmp(argv[0].a_un.a_str, "off")) == 0) {
562 elswitch = FALSE;
563 } else {
564 return (DCMD_USAGE);
565 }
566
567 if (mdb_readvar(&ql_hba, "ql_hba") == -1) {
568 mdb_warn("failed to read ql_hba structure");
569 return (DCMD_ERR);
570 }
571
572 if (&ql_hba == NULL) {
573 mdb_warn("failed to read ql_hba structure - is qlc loaded?");
574 return (DCMD_ERR);
575 }
576
577 if ((qlstate = (ql_adapter_state_t *)mdb_alloc(qlsize,
578 UM_SLEEP)) == NULL) {
579 mdb_warn("Unable to allocate memory for "
580 "ql_adapter_state\n");
581 return (DCMD_OK);
582 }
583
584 if ((strcasecmp(argv[1].a_un.a_str, "all")) == 0) {
585
586 if (argc != 2) {
587 mdb_free(qlstate, qlsize);
588 return (DCMD_USAGE);
589 }
590
591 hbaptr = (uintptr_t)ql_hba.first;
592
736 mdb_alloc(sizeof (ql_adapter_state_t), UM_SLEEP)) == NULL) {
737 mdb_warn("Unable to allocate memory for ql_adapter_state\n");
738 return (DCMD_OK);
739 }
740 if (mdb_vread(qlstate, sizeof (ql_adapter_state_t), addr) == -1) {
741 mdb_free(qlstate, sizeof (ql_adapter_state_t));
742 mdb_warn("failed to read ql_adapter_state at %p", addr);
743 return (DCMD_OK);
744 }
745
746 qlosc = (uintptr_t)qlstate->outstanding_cmds;
747 mdb_printf("qlc instance: %d, base addr = %llx, osc base = %p\n",
748 qlstate->instance, qlstate->hba.base_address, qlosc);
749
750 if ((qlsrb = (ql_srb_t *)mdb_alloc(sizeof (ql_srb_t), UM_SLEEP)) ==
751 NULL) {
752 mdb_free(qlstate, sizeof (ql_adapter_state_t));
753 mdb_warn("failed to allocate space for srb_t\n");
754 return (DCMD_OK);
755 }
756 for (indx = 0; indx < MAX_OUTSTANDING_COMMANDS; indx++, qlosc += 8) {
757 if (mdb_vread(&ptr1, 8, qlosc) == -1) {
758 mdb_warn("failed to read ptr1, indx=%d", indx);
759 break;
760 }
761 if (ptr1 == 0) {
762 continue;
763 }
764
765 mdb_printf("osc ptr = %p, indx = %xh\n", ptr1, indx);
766
767 if (mdb_vread(qlsrb, sizeof (ql_srb_t), ptr1) == -1) {
768 mdb_warn("failed to read ql_srb_t at %p", ptr1);
769 break;
770 }
771 (void) ql_doprint(ptr1, "struct ql_srb");
772 found++;
773 }
774
775 mdb_free(qlsrb, sizeof (ql_srb_t));
776 mdb_free(qlstate, sizeof (ql_adapter_state_t));
1586 const mdb_arg_t *argv)
1587 {
1588 ql_adapter_state_t *qlstate;
1589 uintptr_t hbaptr = NULL;
1590 ql_head_t ql_hba;
1591 uint32_t qlsize = sizeof (ql_adapter_state_t);
1592 int mdbs;
1593
1594 if ((mdbs = mdb_get_state()) == MDB_STATE_DEAD) {
1595 mdb_warn("Cannot change core file data (state=%xh)\n", mdbs);
1596 return (DCMD_OK);
1597 }
1598
1599 if ((qlstate = (ql_adapter_state_t *)mdb_alloc(qlsize,
1600 UM_SLEEP)) == NULL) {
1601 mdb_warn("Unable to allocate memory for ql_adapter_state\n");
1602 return (DCMD_OK);
1603 }
1604
1605 if (addr == NULL) {
1606 char *tptr;
1607 uint32_t instance;
1608
1609 if (argc == 0) {
1610 mdb_warn("must specify either the ha addr or "
1611 "the instance number\n");
1612 mdb_free(qlstate, qlsize);
1613 return (DCMD_OK);
1614 }
1615
1616 /*
1617 * find the specified instance in the ha list
1618 */
1619
1620 instance = (uint32_t)strtol(argv[1].a_un.a_str, &tptr, 16);
1621 if (tptr == argv[1].a_un.a_str) {
1622 mdb_printf("instance # is illegal: '%s'\n",
1623 argv[1].a_un.a_str);
1624 mdb_free(qlstate, qlsize);
1625 return (DCMD_OK);
1626 }
1627
1628 if (mdb_readvar(&ql_hba, "ql_hba") == -1) {
1629 mdb_warn("failed to read ql_hba structure");
1630 mdb_free(qlstate, qlsize);
1631 return (DCMD_ERR);
1632 }
1633
1634 if (&ql_hba == NULL) {
1635 mdb_warn("failed to read ql_hba structure - "
1636 "is qlc loaded?");
1637 mdb_free(qlstate, qlsize);
1638 return (DCMD_ERR);
1639 }
1640
1641 hbaptr = (uintptr_t)ql_hba.first;
1642 while (hbaptr != NULL) {
1643
1644 if (mdb_vread(qlstate, qlsize, hbaptr) == -1) {
1645 mdb_free(qlstate, qlsize);
1646 mdb_warn("failed to read "
1744 if (mdb_getopts(argc, argv, 'v', MDB_OPT_SETBITS, TRUE, &verbose) !=
1745 argc) {
1746 return (DCMD_USAGE);
1747 }
1748
1749 /*
1750 * Get the adapter state struct which was passed
1751 */
1752 if ((ha = (ql_adapter_state_t *)mdb_alloc(sizeof (ql_adapter_state_t),
1753 UM_SLEEP)) == NULL) {
1754 mdb_warn("failed to allocate memory for ql_adapter_state\n");
1755 return (DCMD_OK);
1756 }
1757
1758 /*
1759 * show user which instances have valid f/w dumps available if
1760 * user has specified verbose option
1761 */
1762 if (mdb_readvar(&ql_hba, "ql_hba") == -1) {
1763 mdb_warn("failed to read ql_hba structure");
1764 } else if (&ql_hba == NULL) {
1765 mdb_warn("failed to read ql_hba structure -- is qlc loaded?");
1766 } else if (verbose) {
1767 hbaptr = (uintptr_t)ql_hba.first;
1768 while (hbaptr != NULL) {
1769
1770 if (mdb_vread(ha, sizeof (ql_adapter_state_t),
1771 hbaptr) == -1) {
1772 mdb_free(ha, sizeof (ql_adapter_state_t));
1773 mdb_warn("failed read ql_adapter_state at %p",
1774 hbaptr);
1775 return (DCMD_OK);
1776 }
1777
1778 mdb_printf("instance %d:\n", ha->instance);
1779 (void) mdb_inc_indent((ulong_t)4);
1780
1781 if (ha->ql_dump_state == 0) {
1782 mdb_printf("no dump flags\n");
1783 } else {
1784 ql_dump_flags((uint64_t)ha->ql_dump_state,
1800 }
1801
1802 if (mdb_vread(ha, sizeof (ql_adapter_state_t), addr) == -1) {
1803 mdb_warn("failed to read ql_adapter_state at %p", addr);
1804 mdb_free(ha, sizeof (ql_adapter_state_t));
1805 return (DCMD_OK);
1806 }
1807
1808 /*
1809 * If its not a valid dump or there's not a f/w dump binary (???)
1810 * then bail out
1811 */
1812 if (((ha->ql_dump_state & QL_DUMP_VALID) == 0) ||
1813 (ha->ql_dump_ptr == NULL)) {
1814 mdb_warn("dump does not exist for instance %d (%x, %p)\n",
1815 ha->instance, ha->ql_dump_state, ha->ql_dump_ptr);
1816 mdb_free(ha, sizeof (ql_adapter_state_t));
1817 return (DCMD_OK);
1818 }
1819
1820 if (CFG_IST(ha, CFG_CTRL_2422)) {
1821 (void) ql_24xx_dump_dcmd(ha, flags, argc, argv);
1822 } else if (CFG_IST(ha, CFG_CTRL_25XX)) {
1823 (void) ql_25xx_dump_dcmd(ha, flags, argc, argv);
1824 } else if (CFG_IST(ha, CFG_CTRL_81XX)) {
1825 (void) ql_81xx_dump_dcmd(ha, flags, argc, argv);
1826 } else if (!(CFG_IST(ha, CFG_CTRL_8021))) {
1827 (void) ql_23xx_dump_dcmd(ha, flags, argc, argv);
1828 }
1829
1830 mdb_free(ha, sizeof (ql_adapter_state_t));
1831
1832 return (DCMD_OK);
1833 }
1834
1835 /*
1836 * ql_23xx_dump_dcmd
1837 * prints out a firmware dump buffer
1838 *
1839 * Input:
1840 * addr = User supplied address. (NB: nust be an ha)
1841 * flags = mdb flags.
1842 * argc = Number of user supplied args.
1843 * argv = Arg array.
1844 *
1845 * Returns:
1846 * DCMD_OK or DCMD_ERR
1847 *
1848 * Context:
1849 * User context.
1850 *
1851 */
1852 /*ARGSUSED*/
1853 static int
1854 ql_23xx_dump_dcmd(ql_adapter_state_t *ha, uint_t flags, int argc,
1855 const mdb_arg_t *argv)
1856 {
1857 ql_fw_dump_t *fw;
1858 uint32_t cnt = 0;
1859 int mbox_cnt;
1860
1861 fw = (ql_fw_dump_t *)mdb_alloc(ha->ql_dump_size, UM_SLEEP);
1862
1863 if (mdb_vread(fw, ha->ql_dump_size,
1864 (uintptr_t)ha->ql_dump_ptr) == -1) {
1865 mdb_warn("failed to read ql_dump_ptr (no f/w dump active?)");
1866 mdb_free(fw, ha->ql_dump_size);
1867 return (DCMD_OK);
1868 }
1869
1870 if (ha->cfg_flags & CFG_CTRL_2300) {
1871 mdb_printf("\nISP 2300IP ");
1872 } else if (ha->cfg_flags & CFG_CTRL_6322) {
1873 mdb_printf("\nISP 6322FLX ");
1874 } else {
1875 mdb_printf("\nISP 2200IP ");
1876 }
1877
1878 mdb_printf("Firmware Version %d.%d.%d\n",
1879 ha->fw_major_version, ha->fw_minor_version,
1880 ha->fw_subminor_version);
1881
1882 mdb_printf("\nPBIU Registers:");
1883 for (cnt = 0; cnt < sizeof (fw->pbiu_reg) / 2; cnt++) {
1884 if (cnt % 8 == 0) {
1885 mdb_printf("\n");
1886 }
1887 mdb_printf("%04x ", fw->pbiu_reg[cnt]);
1888 }
1889
1890 if (ha->cfg_flags & (CFG_CTRL_2300 | CFG_CTRL_6322)) {
1891 mdb_printf("\n\nReqQ-RspQ-Risc2Host Status registers:");
1892 for (cnt = 0; cnt < sizeof (fw->risc_host_reg) / 2; cnt++) {
1893 if (cnt % 8 == 0) {
1894 mdb_printf("\n");
1895 }
1896 mdb_printf("%04x ", fw->risc_host_reg[cnt]);
1897 }
1898 }
1899
1900 mdb_printf("\n\nMailbox Registers:");
1901 mbox_cnt = (ha->cfg_flags & (CFG_CTRL_2300 | CFG_CTRL_6322)) ? 16 : 8;
1902 for (cnt = 0; cnt < mbox_cnt; cnt++) {
1903 if (cnt % 8 == 0) {
1904 mdb_printf("\n");
1905 }
1906 mdb_printf("%04x ", fw->mailbox_reg[cnt]);
1907 }
1908
1909 if (ha->cfg_flags & (CFG_CTRL_2300 | CFG_CTRL_6322)) {
1910 mdb_printf("\n\nAuto Request Response DMA Registers:");
1911 for (cnt = 0; cnt < sizeof (fw->resp_dma_reg) / 2; cnt++) {
1912 if (cnt % 8 == 0) {
1913 mdb_printf("\n");
1914 }
1915 mdb_printf("%04x ", fw->resp_dma_reg[cnt]);
1916 }
1917 }
1918
1919 mdb_printf("\n\nDMA Registers:");
1920 for (cnt = 0; cnt < sizeof (fw->dma_reg) / 2; cnt++) {
1921 if (cnt % 8 == 0) {
1922 mdb_printf("\n");
1923 }
1924 mdb_printf("%04x ", fw->dma_reg[cnt]);
1925 }
1926
1927 mdb_printf("\n\nRISC Hardware Registers:");
1928 for (cnt = 0; cnt < sizeof (fw->risc_hdw_reg) / 2; cnt++) {
1929 if (cnt % 8 == 0) {
1982
1983 mdb_printf("\n\nRISC GP6 Registers:");
1984 for (cnt = 0; cnt < sizeof (fw->risc_gp6_reg) / 2; cnt++) {
1985 if (cnt % 8 == 0) {
1986 mdb_printf("\n");
1987 }
1988 mdb_printf("%04x ", fw->risc_gp6_reg[cnt]);
1989 }
1990
1991 mdb_printf("\n\nRISC GP7 Registers:");
1992 for (cnt = 0; cnt < sizeof (fw->risc_gp7_reg) / 2; cnt++) {
1993 if (cnt % 8 == 0) {
1994 mdb_printf("\n");
1995 }
1996 mdb_printf("%04x ", fw->risc_gp7_reg[cnt]);
1997 }
1998
1999 mdb_printf("\n\nFrame Buffer Hardware Registers:");
2000 for (cnt = 0; cnt < sizeof (fw->frame_buf_hdw_reg) / 2; cnt++) {
2001 if ((cnt == 16) &&
2002 ((ha->cfg_flags & (CFG_CTRL_2300 | CFG_CTRL_6322)) == 0)) {
2003 break;
2004 }
2005 if (cnt % 8 == 0) {
2006 mdb_printf("\n");
2007 }
2008 mdb_printf("%04x ", fw->frame_buf_hdw_reg[cnt]);
2009 }
2010
2011 mdb_printf("\n\nFPM B0 Registers:");
2012 for (cnt = 0; cnt < sizeof (fw->fpm_b0_reg) / 2; cnt++) {
2013 if (cnt % 8 == 0) {
2014 mdb_printf("\n");
2015 }
2016 mdb_printf("%04x ", fw->fpm_b0_reg[cnt]);
2017 }
2018
2019 mdb_printf("\n\nFPM B1 Registers:");
2020 for (cnt = 0; cnt < sizeof (fw->fpm_b1_reg) / 2; cnt++) {
2021 if (cnt % 8 == 0) {
2022 mdb_printf("\n");
2023 }
2024 mdb_printf("%04x ", fw->fpm_b1_reg[cnt]);
2025 }
2026
2027 if (ha->cfg_flags & (CFG_CTRL_2300 | CFG_CTRL_6322)) {
2028 mdb_printf("\n\nCode RAM Dump:");
2029 for (cnt = 0; cnt < sizeof (fw->risc_ram) / 2; cnt++) {
2030 if (cnt % 8 == 0) {
2031 mdb_printf("\n%05x: ", cnt + 0x0800);
2032 }
2033 mdb_printf("%04x ", fw->risc_ram[cnt]);
2034 }
2035
2036 mdb_printf("\n\nStack RAM Dump:");
2037 for (cnt = 0; cnt < sizeof (fw->stack_ram) / 2; cnt++) {
2038 if (cnt % 8 == 0) {
2039 mdb_printf("\n%05x: ", cnt + 0x010000);
2040 }
2041 mdb_printf("%04x ", fw->stack_ram[cnt]);
2042 }
2043
2044 mdb_printf("\n\nData RAM Dump:");
2045 for (cnt = 0; cnt < sizeof (fw->data_ram) / 2; cnt++) {
2046 if (cnt % 8 == 0) {
2047 mdb_printf("\n%05x: ", cnt + 0x010800);
2412 *
2413 * Input:
2414 * addr = User supplied address. (NB: nust be an ha)
2415 * flags = mdb flags.
2416 * argc = Number of user supplied args.
2417 * argv = Arg array.
2418 *
2419 * Returns:
2420 * DCMD_OK or DCMD_ERR
2421 *
2422 * Context:
2423 * User context.
2424 *
2425 */
2426 /*ARGSUSED*/
2427 static int
2428 ql_25xx_dump_dcmd(ql_adapter_state_t *ha, uint_t flags, int argc,
2429 const mdb_arg_t *argv)
2430 {
2431 ql_25xx_fw_dump_t *fw;
2432 uint32_t cnt = 0;
2433
2434 fw = (ql_25xx_fw_dump_t *)mdb_alloc(ha->ql_dump_size, UM_SLEEP);
2435
2436 if (mdb_vread(fw, ha->ql_dump_size,
2437 (uintptr_t)ha->ql_dump_ptr) == -1) {
2438 mdb_warn("failed to read ql_dump_ptr (no f/w dump active?)");
2439 mdb_free(fw, ha->ql_dump_size);
2440 return (DCMD_OK);
2441 }
2442
2443 mdb_printf("\nISP FW Version %d.%02d.%02d Attributes %X\n",
2444 ha->fw_major_version, ha->fw_minor_version,
2445 ha->fw_subminor_version, ha->fw_attributes);
2446
2447 mdb_printf("\nR2H Register\n%08x\n", fw->r2h_status);
2448
2449 mdb_printf("\n\nHostRisc Registers");
2450 for (cnt = 0; cnt < sizeof (fw->hostrisc_reg) / 4; cnt++) {
2451 if (cnt % 8 == 0) {
2452 mdb_printf("\n");
2453 }
2454 mdb_printf("%08x ", fw->hostrisc_reg[cnt]);
2455 }
2456
2457 mdb_printf("\n\nPCIe Registers");
2458 for (cnt = 0; cnt < sizeof (fw->pcie_reg) / 4; cnt++) {
2459 if (cnt % 8 == 0) {
2460 mdb_printf("\n");
2461 }
2462 mdb_printf("%08x ", fw->pcie_reg[cnt]);
2463 }
2464
2465 mdb_printf("\n\nHost Interface Registers");
2466 for (cnt = 0; cnt < sizeof (fw->host_reg) / 4; cnt++) {
2467 if (cnt % 8 == 0) {
2699 mdb_printf("%08x ", fw->fpm_hdw_reg[cnt]);
2700 }
2701
2702 mdb_printf("\n\nFB Hardware Registers");
2703 for (cnt = 0; cnt < sizeof (fw->fb_hdw_reg) / 4; cnt++) {
2704 if (cnt % 8 == 0) {
2705 mdb_printf("\n");
2706 }
2707 mdb_printf("%08x ", fw->fb_hdw_reg[cnt]);
2708 }
2709
2710 mdb_printf("\n\nCode RAM");
2711 for (cnt = 0; cnt < sizeof (fw->code_ram) / 4; cnt++) {
2712 if (cnt % 8 == 0) {
2713 mdb_printf("\n%08x: ", cnt + 0x20000);
2714 }
2715 mdb_printf("%08x ", fw->code_ram[cnt]);
2716 }
2717
2718 mdb_printf("\n\nExternal Memory");
2719 for (cnt = 0; cnt < ha->fw_ext_memory_size / 4; cnt++) {
2720 if (cnt % 8 == 0) {
2721 mdb_printf("\n%08x: ", cnt + 0x100000);
2722 }
2723 mdb_printf("%08x ", fw->ext_mem[cnt]);
2724 }
2725
2726 mdb_printf("\n[<==END] ISP Debug Dump");
2727
2728 mdb_printf("\n\nRequest Queue");
2729
2730 for (cnt = 0; cnt < REQUEST_QUEUE_SIZE / 4; cnt++) {
2731 if (cnt % 8 == 0) {
2732 mdb_printf("\n%08x: ", cnt);
2733 }
2734 mdb_printf("%08x ", fw->req_q[cnt]);
2735 }
2736
2737 mdb_printf("\n\nResponse Queue");
2738
2739 for (cnt = 0; cnt < RESPONSE_QUEUE_SIZE / 4; cnt++) {
2740 if (cnt % 8 == 0) {
2741 mdb_printf("\n%08x: ", cnt);
2742 }
2743 mdb_printf("%08x ", fw->rsp_q[cnt]);
2744 }
2745
2746 if ((ha->cfg_flags & CFG_ENABLE_FWEXTTRACE) &&
2747 (ha->fwexttracebuf.bp != NULL)) {
2748 uint32_t cnt_b = 0;
2749 uint32_t *w32 = ha->fwexttracebuf.bp;
2750
2751 mdb_printf("\n\nExtended Trace Buffer Memory");
2752 /* show data address as a byte address, data as long words */
2753 for (cnt = 0; cnt < FWEXTSIZE / 4; cnt++) {
2754 cnt_b = cnt * 4;
2755 if (cnt_b % 32 == 0) {
2756 mdb_printf("\n%08x: ", w32 + cnt_b);
2757 }
2758 mdb_printf("%08x ", fw->ext_trace_buf[cnt]);
2759 }
2760 }
2761
2762 if ((ha->cfg_flags & CFG_ENABLE_FWFCETRACE) &&
2763 (ha->fwfcetracebuf.bp != NULL)) {
2764 uint32_t cnt_b = 0;
2765 uint32_t *w32 = ha->fwfcetracebuf.bp;
2766
2767 mdb_printf("\n\nFC Event Trace Buffer Memory");
2768 /* show data address as a byte address, data as long words */
2769 for (cnt = 0; cnt < FWFCESIZE / 4; cnt++) {
2770 cnt_b = cnt * 4;
2771 if (cnt_b % 32 == 0) {
2772 mdb_printf("\n%08x: ", w32 + cnt_b);
2773 }
2774 mdb_printf("%08x ", fw->fce_trace_buf[cnt]);
2775 }
2776 }
2777
2778 mdb_free(fw, ha->ql_dump_size);
2779
2780 mdb_printf("\n\nreturn exit\n");
2781
2782 return (DCMD_OK);
2783 }
2784
2785 /*
2786 * ql_81xx_dump_dcmd
2787 * prints out a firmware dump buffer
2788 *
2789 * Input:
2790 * addr = User supplied address. (NB: nust be an ha)
2791 * flags = mdb flags.
2792 * argc = Number of user supplied args.
2793 * argv = Arg array.
2794 *
2795 * Returns:
2796 * DCMD_OK or DCMD_ERR
2797 *
2798 * Context:
2799 * User context.
2800 *
2801 */
2802 /*ARGSUSED*/
2803 static int
2804 ql_81xx_dump_dcmd(ql_adapter_state_t *ha, uint_t flags, int argc,
2805 const mdb_arg_t *argv)
2806 {
2807 ql_81xx_fw_dump_t *fw;
2808 uint32_t cnt = 0;
2809
2810 fw = (ql_81xx_fw_dump_t *)mdb_alloc(ha->ql_dump_size, UM_SLEEP);
2811
2812 if (mdb_vread(fw, ha->ql_dump_size,
2813 (uintptr_t)ha->ql_dump_ptr) == -1) {
2814 mdb_warn("failed to read ql_dump_ptr (no f/w dump active?)");
2815 mdb_free(fw, ha->ql_dump_size);
2816 return (DCMD_OK);
2817 }
2818
2819 mdb_printf("\nISP FW Version %d.%02d.%02d Attributes %X\n",
2820 ha->fw_major_version, ha->fw_minor_version,
2821 ha->fw_subminor_version, ha->fw_attributes);
2822
2823 mdb_printf("\nR2H Register\n%08x\n", fw->r2h_status);
2824
2825 mdb_printf("\n\nHostRisc Registers");
2826 for (cnt = 0; cnt < sizeof (fw->hostrisc_reg) / 4; cnt++) {
2827 if (cnt % 8 == 0) {
2828 mdb_printf("\n");
2829 }
2830 mdb_printf("%08x ", fw->hostrisc_reg[cnt]);
2831 }
2832
2833 mdb_printf("\n\nPCIe Registers");
2834 for (cnt = 0; cnt < sizeof (fw->pcie_reg) / 4; cnt++) {
2835 if (cnt % 8 == 0) {
2836 mdb_printf("\n");
2837 }
2838 mdb_printf("%08x ", fw->pcie_reg[cnt]);
2839 }
2840
2841 mdb_printf("\n\nHost Interface Registers");
2842 for (cnt = 0; cnt < sizeof (fw->host_reg) / 4; cnt++) {
2843 if (cnt % 8 == 0) {
2844 mdb_printf("\n");
3075 mdb_printf("%08x ", fw->fpm_hdw_reg[cnt]);
3076 }
3077
3078 mdb_printf("\n\nFB Hardware Registers");
3079 for (cnt = 0; cnt < sizeof (fw->fb_hdw_reg) / 4; cnt++) {
3080 if (cnt % 8 == 0) {
3081 mdb_printf("\n");
3082 }
3083 mdb_printf("%08x ", fw->fb_hdw_reg[cnt]);
3084 }
3085
3086 mdb_printf("\n\nCode RAM");
3087 for (cnt = 0; cnt < sizeof (fw->code_ram) / 4; cnt++) {
3088 if (cnt % 8 == 0) {
3089 mdb_printf("\n%08x: ", cnt + 0x20000);
3090 }
3091 mdb_printf("%08x ", fw->code_ram[cnt]);
3092 }
3093
3094 mdb_printf("\n\nExternal Memory");
3095 for (cnt = 0; cnt < ha->fw_ext_memory_size / 4; cnt++) {
3096 if (cnt % 8 == 0) {
3097 mdb_printf("\n%08x: ", cnt + 0x100000);
3098 }
3099 mdb_printf("%08x ", fw->ext_mem[cnt]);
3100 }
3101
3102 mdb_printf("\n[<==END] ISP Debug Dump");
3103
3104 mdb_printf("\n\nRequest Queue");
3105
3106 for (cnt = 0; cnt < REQUEST_QUEUE_SIZE / 4; cnt++) {
3107 if (cnt % 8 == 0) {
3108 mdb_printf("\n%08x: ", cnt);
3109 }
3110 mdb_printf("%08x ", fw->req_q[cnt]);
3111 }
3112
3113 mdb_printf("\n\nResponse Queue");
3114
3115 for (cnt = 0; cnt < RESPONSE_QUEUE_SIZE / 4; cnt++) {
3116 if (cnt % 8 == 0) {
3117 mdb_printf("\n%08x: ", cnt);
3118 }
3119 mdb_printf("%08x ", fw->rsp_q[cnt]);
3120 }
3121
3122 if ((ha->cfg_flags & CFG_ENABLE_FWEXTTRACE) &&
3123 (ha->fwexttracebuf.bp != NULL)) {
3124 uint32_t cnt_b = 0;
3125 uint32_t *w32 = ha->fwexttracebuf.bp;
3126
3127 mdb_printf("\n\nExtended Trace Buffer Memory");
3128 /* show data address as a byte address, data as long words */
3129 for (cnt = 0; cnt < FWEXTSIZE / 4; cnt++) {
3130 cnt_b = cnt * 4;
3131 if (cnt_b % 32 == 0) {
3132 mdb_printf("\n%08x: ", w32 + cnt_b);
3133 }
3134 mdb_printf("%08x ", fw->ext_trace_buf[cnt]);
3135 }
3136 }
3137
3138 if ((ha->cfg_flags & CFG_ENABLE_FWFCETRACE) &&
3139 (ha->fwfcetracebuf.bp != NULL)) {
3140 uint32_t cnt_b = 0;
3141 uint32_t *w32 = ha->fwfcetracebuf.bp;
3142
3143 mdb_printf("\n\nFC Event Trace Buffer Memory");
3144 /* show data address as a byte address, data as long words */
3145 for (cnt = 0; cnt < FWFCESIZE / 4; cnt++) {
3146 cnt_b = cnt * 4;
3147 if (cnt_b % 32 == 0) {
3148 mdb_printf("\n%08x: ", w32 + cnt_b);
3149 }
3150 mdb_printf("%08x ", fw->fce_trace_buf[cnt]);
3151 }
3152 }
3153
3154 mdb_free(fw, ha->ql_dump_size);
3155
3156 mdb_printf("\n\nreturn exit\n");
3157
3158 return (DCMD_OK);
3159 }
3160
3161 /*
3162 * ql_gettrace_dcmd
3163 * prints out the Extended Logging trace buffer
3164 *
3165 * Input:
3166 * addr = User supplied address. (NB: must be an ha)
3167 * flags = mdb flags.
3168 * argc = Number of user supplied args.
3169 * argv = Arg array.
3170 *
3171 * Returns:
3172 * DCMD_OK or DCMD_ERR
3173 *
3174 * Context:
3175 * User context.
3176 *
3177 */
3178 static int
3179 qlc_gettrace_dcmd(uintptr_t addr, uint_t flags, int argc, const mdb_arg_t *argv)
3180 {
3181 ql_adapter_state_t *ha;
3182 int verbose = 0;
3183 int wrapped = 0;
3184 char *trace_start;
3185 char *trace_end;
3186 char *dump_start = 0;
3187 char *trace_next = 0;
3188 char *dump_current = 0;
3189 el_trace_desc_t *trace_desc;
3190
3191 if ((!(flags & DCMD_ADDRSPEC)) || addr == NULL) {
3192 mdb_warn("ql_adapter_state structure addr is required");
3193 return (DCMD_USAGE);
3194 }
3195
3196 if (mdb_getopts(argc, argv, 'v', MDB_OPT_SETBITS, TRUE, &verbose) !=
3197 argc) {
3198 return (DCMD_USAGE);
3199 }
3200
3201 /*
3202 * Get the adapter state struct which was passed
3203 */
3204 if ((ha = (ql_adapter_state_t *)mdb_alloc(sizeof (ql_adapter_state_t),
3205 UM_SLEEP)) == NULL) {
3206 mdb_warn("failed to allocate memory for ql_adapter_state\n");
3207 return (DCMD_OK);
3208 }
3209
3210 if (mdb_vread(ha, sizeof (ql_adapter_state_t), addr) == -1) {
3211 mdb_warn("failed to read ql_adapter_state at %p", addr);
3212 mdb_free(ha, sizeof (ql_adapter_state_t));
3213 return (DCMD_OK);
3214 }
3215
3216 /*
3217 * If its not a valid trace descriptor then bail out
3218 */
3219 if (ha->el_trace_desc == NULL) {
3220 mdb_warn("trace descriptor does not exist for instance %d\n",
3221 ha->instance);
3222 mdb_free(ha, sizeof (ql_adapter_state_t));
3223 return (DCMD_OK);
3224 } else {
3225 trace_desc = (el_trace_desc_t *)
3226 mdb_alloc(sizeof (el_trace_desc_t), UM_SLEEP);
3227 if (mdb_vread(trace_desc, sizeof (el_trace_desc_t),
3228 (uintptr_t)ha->el_trace_desc) == -1) {
3229 mdb_warn("failed to read ql_adapter_state at %p",
3230 addr);
3231 mdb_free(trace_desc, sizeof (el_trace_desc_t));
3232 mdb_free(ha, sizeof (ql_adapter_state_t));
3233 return (DCMD_OK);
3234 }
3235 if (trace_desc->trace_buffer == NULL) {
3236 mdb_warn("trace buffer does not exist for "
3237 "instance %d\n", ha->instance);
3238 mdb_free(trace_desc, sizeof (el_trace_desc_t));
3239 mdb_free(ha, sizeof (ql_adapter_state_t));
3240 return (DCMD_OK);
3241 }
3242 }
3243
3244 /* Get the trace buffer */
3245
3246 trace_start = (char *)
3247 mdb_zalloc(trace_desc->trace_buffer_size, UM_SLEEP);
3248
3249 if (mdb_vread(trace_start, trace_desc->trace_buffer_size,
3250 (uintptr_t)trace_desc->trace_buffer) == -1) {
3251 mdb_warn("failed to read trace buffer?)");
3252 mdb_free(trace_start, trace_desc->trace_buffer_size);
3253 mdb_free(ha, sizeof (ql_adapter_state_t));
3254 return (DCMD_OK);
3255 }
3256
3257 /* set the end of the trace buffer. */
3258 trace_end = trace_start + trace_desc->trace_buffer_size;
3259
3260 /* Find the start point of trace. */
3261 trace_next = trace_start + trace_desc->next;
3262
3263 /*
3264 * If the buffer has not wrapped next will point at a null so
3265 * start is the begining of the buffer. If next points at a char
3266 * then we must traverse the buffer further until a null is detected.
3267 * The location after the null will be the beginning of the oldest
3268 * whole object in the buffer, which we use as the start.
3269 */
3270
3271 if ((trace_next + EL_BUFFER_RESERVE) >= trace_end) {
3272 dump_start = trace_start;
3273 } else if (*trace_next != NULL) {
3274 dump_start = trace_next + (strlen(trace_next) + 1);
3275 } else {
3276 dump_start = trace_start;
3277 }
3278
3279 dump_current = dump_start;
3280
3281 mdb_printf("\nExtended Logging trace buffer @%x, start @%x, "
3282 "size=%d\n\n", trace_start, dump_current,
3283 trace_desc->trace_buffer_size);
3284
3285 /* Don't run off the end, no matter what. */
3286 while (((uintptr_t)dump_current - (uintptr_t)trace_start) <=
3287 (uintptr_t)trace_desc->trace_buffer_size) {
3288 /* Show it... */
3289 mdb_printf("%s", dump_current);
3290 /* Calculate the next and make it the current */
3291 dump_current += (strlen(dump_current) + 1);
3292 /* check for wrap */
3293 if ((dump_current + EL_BUFFER_RESERVE) >= trace_end) {
3294 mdb_printf("Wraping %x\n", dump_current);
3295 dump_current = trace_start;
3296 wrapped = 1;
3297 } else if (wrapped) {
3298 /* Don't go past next. */
3299 if ((trace_start + trace_desc->next) <= dump_current) {
3300 mdb_printf("Done %x", dump_current);
3301 break;
3302 }
3303 } else if (*dump_current == NULL) {
3304 mdb_printf("Done %x(null)", dump_current);
3305 break;
3306 }
3307 }
3308
3309 mdb_free(ha, sizeof (ql_adapter_state_t));
3310 mdb_free(trace_start, trace_desc->trace_buffer_size);
3311 mdb_free(trace_desc, sizeof (el_trace_desc_t));
3312
3313 return (DCMD_OK);
3314 }
3315 /*
3316 * ql_doprint
3317 * ql generic function to call the print dcmd
3318 *
3319 * Input:
3320 * addr - address to struct
3321 * prtsting - address to string
3322 *
3323 * Returns:
3324 * WALK_DONE
3325 *
3326 * Context:
3327 * User context.
3328 *
3329 */
3330 static int32_t
3331 ql_doprint(uintptr_t addr, int8_t *prtstring)
3332 {
3333 struct mdb_arg printarg;
3334
3392 }
3393
3394 /*
3395 * MDB module linkage information
3396 *
3397 *
3398 * dcmd structures for the _mdb_init function
3399 */
3400 static const mdb_dcmd_t dcmds[] = {
3401 { "qlclinks", NULL, "Prints qlc link information", qlclinks_dcmd },
3402 { "qlcosc", NULL, "Prints outstanding cmd info", qlc_osc_dcmd },
3403 { "qlcver", NULL, "Prints driver/mdb version", qlcver_dcmd },
3404 { "qlc_elog", "[on|off] [<inst #>|all]", "Turns qlc extended logging "
3405 "on / off", qlc_el_dcmd },
3406 { "qlcstate", ":[-v]", "Prints qlc adapter state information",
3407 qlcstate_dcmd },
3408 { "qlctgtq", NULL, "Prints qlc target queues", qltgtq_dcmd },
3409 { "qlcwdog", NULL, "Prints out watchdog linked list", qlc_wdog_dcmd},
3410 { "qlcgetdump", ":[-v]", "Retrieves the ASCII f/w dump",
3411 qlc_getdump_dcmd },
3412 { "qlcgettrace", ":[-v]", "Retrieves the ASCII Extended Logging trace",
3413 qlc_gettrace_dcmd },
3414 { NULL }
3415 };
3416
3417 /*
3418 * walker structures for the _mdb_init function
3419 */
3420 static const mdb_walker_t walkers[] = {
3421 { "qlcstates", "walk list of qlc ql_state_t structures",
3422 qlstates_walk_init, qlstates_walk_step, qlstates_walk_fini },
3423 { "qlcsrbs", "walk list of qlc ql_srb_t strctures",
3424 qlsrb_walk_init, qlsrb_walk_step, qlsrb_walk_fini },
3425 { "qlclunq", "walk list of qlc ql_lun_t strctures",
3426 qllunq_walk_init, qllunq_walk_step, qllunq_walk_fini },
3427 { NULL }
3428 };
3429
3430 static const mdb_modinfo_t ql_mdb_modinfo = {
3431 MDB_API_VERSION, dcmds, walkers
3432 };
|
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /* Copyright 2015 QLogic Corporation */
23
24 /*
25 * ISP2xxx Solaris Fibre Channel Adapter (FCA) qlc mdb source file.
26 *
27 * ***********************************************************************
28 * * **
29 * * NOTICE **
30 * * COPYRIGHT (C) 1996-2015 QLOGIC CORPORATION **
31 * * ALL RIGHTS RESERVED **
32 * * **
33 * ***********************************************************************
34 *
35 */
36
37 #pragma ident "Copyright 2015 QLogic Corporation; ql_mdb.c"
38
39 #include <sys/mdb_modapi.h>
40 #include <ql_apps.h>
41 #include <ql_api.h>
42 #include <ql_init.h>
43
44 /*
45 * local prototypes
46 */
47 static int32_t ql_doprint(uintptr_t, int8_t *);
48 static void ql_dump_flags(uint64_t, int8_t **);
49 static int qlclinks_dcmd(uintptr_t, uint_t, int, const mdb_arg_t *);
50 static int qlcstate_dcmd(uintptr_t, uint_t, int, const mdb_arg_t *);
51 static int qlc_osc_dcmd(uintptr_t, uint_t, int, const mdb_arg_t *);
52 static int qlc_wdog_dcmd(uintptr_t, uint_t, int, const mdb_arg_t *);
53 static int qlc_getdump_dcmd(uintptr_t, uint_t, int, const mdb_arg_t *);
54 static int qlc_gettrace_dcmd(uintptr_t, uint_t, int, const mdb_arg_t *);
55 #if 0
56 static int qlc_triggerdump_dcmd(uintptr_t, uint_t, int, const mdb_arg_t *);
57 #endif
58 static int qlcver_dcmd(uintptr_t, uint_t, int, const mdb_arg_t *);
59 static int qlstates_walk_init(mdb_walk_state_t *);
60 static int qlstates_walk_step(mdb_walk_state_t *);
61 static void qlstates_walk_fini(mdb_walk_state_t *);
62 static int qlsrb_walk_init(mdb_walk_state_t *);
63 static int qlsrb_walk_step(mdb_walk_state_t *);
64 static void qlsrb_walk_fini(mdb_walk_state_t *);
65 static int get_next_link(ql_link_t *);
66 static int get_first_link(ql_head_t *, ql_link_t *);
67
68 static int ql_24xx_dump_dcmd(ql_adapter_state_t *, uint_t, int,
69 const mdb_arg_t *);
70 static int ql_23xx_dump_dcmd(ql_adapter_state_t *, uint_t, int,
71 const mdb_arg_t *);
72 static int ql_25xx_dump_dcmd(ql_adapter_state_t *, uint_t, int,
73 const mdb_arg_t *);
74 static int ql_81xx_dump_dcmd(ql_adapter_state_t *, uint_t, int,
75 const mdb_arg_t *);
76 static int ql_8021_dump_dcmd(ql_adapter_state_t *, uint_t, int,
77 const mdb_arg_t *);
78 static int ql_8300_dump_dcmd(ql_adapter_state_t *, uint_t, int,
79 const mdb_arg_t *);
80 static void ql_elog_common(ql_adapter_state_t *, boolean_t);
81
82 /*
83 * local adapter state flags strings
84 */
85 int8_t *adapter_state_flags[] = {
86 "FCA_BOUND",
87 "QL_OPENED",
88 "ONLINE",
89 "INTERRUPTS_ENABLED",
90 "ABORT_CMDS_LOOP_DOWN_TMO",
91 "POINT_TO_POINT",
92 "IP_ENABLED",
93 "IP_INITIALIZED",
94 "MENLO_LOGIN_OPERATIONAL",
95 "ADAPTER_SUSPENDED",
96 "FW_DUMP_NEEDED",
97 "PARITY_ERROR",
98 "FLASH_ERRLOG_MARKER",
99 "VP_ENABLED",
100 "FDISC_ENABLED",
101 "MULTI_QUEUE",
102 "MPI_RESET_NEEDED",
103 "VP_ID_NOT_ACQUIRED",
104 "IDC_STALL_NEEDED",
105 "POLL_INTR",
106 "IDC_RESTART_NEEDED",
107 "IDC_ACK_NEEDED",
108 "LOOPBACK_ACTIVE",
109 "QUEUE_SHADOW_PTRS",
110 "NO_INTR_HANDSHAKE",
111 "COMP_THD_TERMINATE",
112 "DISABLE_NIC_FW_DMP",
113 "MULTI_CHIP_ADAPTER",
114 NULL
115 };
116
117 int8_t *adapter_config_flags[] = {
118 "CTRL_27XX",
119 "ENABLE_64BIT_ADDRESSING",
120 "ENABLE_LIP_RESET",
121 "ENABLE_FULL_LIP_LOGIN",
122 "ENABLE_TARGET_RESET",
123 "ENABLE_LINK_DOWN_REPORTING",
124 "DISABLE_EXTENDED_LOGGING_TRACE",
125 "ENABLE_FCP_2_SUPPORT",
126 "CTRL_83XX",
127 "SBUS_CARD",
128 "CTRL_23XX",
129 "CTRL_63XX",
130 "CTRL_22XX",
131 "CTRL_24XX",
132 "CTRL_25XX",
133 "ENABLE_EXTENDED_LOGGING",
134 "DISABLE_RISC_CODE_LOAD",
135 "SET_CACHE_LINE_SIZE_1",
136 "CTRL_MENLO",
137 "EXT_FW_INTERFACE",
138 "LOAD_FLASH_FW",
139 "DUMP_MAILBOX_TIMEOUT",
140 "DUMP_ISP_SYSTEM_ERROR",
141 "DUMP_DRIVER_COMMAND_TIMEOUT",
142 "DUMP_LOOP_OFFLINE_TIMEOUT",
143 "ENABLE_FWEXTTRACE",
144 "ENABLE_FWFCETRACE",
145 "CTRL_80XX",
146 "CTRL_81XX",
147 "CTRL_82XX",
148 "FAST_TIMEOUT",
149 "LR_SUPPORT",
150 NULL
151 };
152
153 /*
154 * local task daemon flags strings
155 */
156 int8_t *task_daemon_flags[] = {
157 "TASK_DAEMON_STOP_FLG",
158 "TASK_DAEMON_SLEEPING_FLG",
159 "TASK_DAEMON_ALIVE_FLG",
160 "TASK_DAEMON_IDLE_CHK_FLG",
161 "SUSPENDED_WAKEUP_FLG",
162 "FC_STATE_CHANGE",
163 "NEED_UNSOLICITED_BUFFERS",
164 "MARKER_NEEDED",
165 "MARKER_ACTIVE",
166 "ISP_ABORT_NEEDED",
167 "ABORT_ISP_ACTIVE",
168 "LOOP_RESYNC_NEEDED",
169 "LOOP_RESYNC_ACTIVE",
170 "LOOP_DOWN",
171 "DRIVER_STALL",
172 "COMMAND_WAIT_NEEDED",
173 "COMMAND_WAIT_ACTIVE",
174 "STATE_ONLINE",
175 "ABORT_QUEUES_NEEDED",
176 "TASK_DAEMON_STALLED_FLG",
177 "SEND_PLOGI",
178 "FIRMWARE_UP",
179 "IDC_POLL_NEEDED",
180 "FIRMWARE_LOADED",
181 "RSCN_UPDATE_NEEDED",
182 "HANDLE_PORT_BYPASS_CHANGE",
183 "PORT_RETRY_NEEDED",
184 "TASK_DAEMON_POWERING_DOWN",
185 "TD_IIDMA_NEEDED",
186 "WATCHDOG_NEEDED",
187 "LED_BLINK",
188 NULL
189 };
190
191 /*
192 * local interrupt aif flags
193 */
194 int8_t *aif_flags[] = {
195 "IFLG_INTR_LEGACY",
196 "IFLG_INTR_FIXED",
197 "IFLG_INTR_MSI",
198 "IFLG_INTR_MSIX",
199 NULL
200 };
201
202 int8_t *qlsrb_flags[] = {
203 "SRB_ISP_STARTED",
204 "SRB_ISP_COMPLETED",
205 "SRB_RETRY",
206 "SRB_POLL",
207 "SRB_WATCHDOG_ENABLED",
208 "SRB_ABORT",
209 "SRB_UB_IN_FCA",
210 "SRB_UB_IN_ISP",
211 "SRB_UB_CALLBACK",
212 "SRB_UB_RSCN",
213 "SRB_UB_FCP",
214 "SRB_FCP_CMD_PKT",
215 "SRB_FCP_DATA_PKT",
216 "SRB_FCP_RSP_PKT",
217 "SRB_IP_PKT",
218 "SRB_GENERIC_SERVICES_PKT",
219 "SRB_COMMAND_TIMEOUT",
220 "SRB_ABORTING",
221 "SRB_IN_DEVICE_QUEUE",
222 "SRB_IN_TOKEN_ARRAY",
223 "SRB_UB_FREE_REQUESTED",
224 "SRB_UB_ACQUIRED",
225 "SRB_MS_PKT",
226 "SRB_ELS_PKT",
227 NULL
228 };
229
230 int8_t *qllun_flags[] = {
231 "LQF_UNTAGGED_PENDING",
232 NULL
233 };
234
235 int8_t *qltgt_flags[] = {
236 "TQF_TAPE_DEVICE",
237 "TQF_QUEUE_SUSPENDED",
238 "TQF_FABRIC_DEVICE",
239 "TQF_INITIATOR_DEVICE",
240 "TQF_RSCN_RCVD",
241 "TQF_NEED_AUTHENTICATION",
242 "TQF_PLOGI_PROGRS",
243 "TQF_IIDMA_NEEDED",
244 "TQF_LOGIN_NEEDED",
245 NULL
246 };
247
248 int8_t *qldump_flags[] = {
249 "QL_DUMPING",
250 "QL_DUMP_VALID",
251 "QL_DUMP_UPLOADED",
252 NULL
253 };
254
255 /*
256 * qlclinks_dcmd
257 * mdb dcmd which prints out the ql_hba pointers
258 *
259 * Input:
260 * addr = User supplied address -- error if supplied.
261 * flags = mdb flags.
262 * argc = Number of user supplied args -- error if non-zero.
263 * argv = Arg array.
264 *
269 * User context.
270 *
271 */
272 /*ARGSUSED*/
273 static int
274 qlclinks_dcmd(uintptr_t addr, uint_t flags, int argc, const mdb_arg_t *argv)
275 {
276 ql_head_t ql_hba;
277 ql_adapter_state_t *qlstate;
278 uintptr_t hbaptr = NULL;
279
280 if ((flags & DCMD_ADDRSPEC) || argc != 0) {
281 return (DCMD_USAGE);
282 }
283
284 if (mdb_readvar(&ql_hba, "ql_hba") == -1) {
285 mdb_warn("failed to read ql_hba structure");
286 return (DCMD_ERR);
287 }
288
289 if (ql_hba.first == NULL) {
290 mdb_warn("failed to read ql_hba structure -- is qlc loaded?");
291 return (DCMD_ERR);
292 }
293
294 mdb_printf("\nqlc adapter state linkages (f=0x%llx, l=0x%llx)\n\n",
295 ql_hba.first, ql_hba.last);
296
297 if ((qlstate = (ql_adapter_state_t *)mdb_alloc(
298 sizeof (ql_adapter_state_t), UM_SLEEP)) == NULL) {
299 mdb_warn("Unable to allocate memory for ql_adapter_state\n");
300 return (DCMD_OK);
301 }
302
303 (void) mdb_inc_indent((ulong_t)4);
304 mdb_printf("%<u>%-?s\t%-45s%</u>\n\n", "baseaddr", "instance");
305
306 hbaptr = (uintptr_t)ql_hba.first;
307 while (hbaptr != NULL) {
308
309 if (mdb_vread(qlstate, sizeof (ql_adapter_state_t),
444 "ql_adapter_state\n");
445 return (DCMD_OK);
446 }
447
448 mdb_printf("\n%-8s%-11s%s\n", "f/w", "compiled", "loaded");
449 mdb_printf("%<u>%-8s%-11s%-13s%s%</u>\n\n", "class", "version",
450 "version", "instance list");
451
452 for (fwt = &fw_table[0]; fwt->fw_class; fwt++) {
453
454 if (mdb_vread(fwverptr, sizeof (void *),
455 (uintptr_t)fwt->fw_version) == -1) {
456 mdb_warn("unable to read fwverptr\n");
457 mdb_free(fwverptr, sizeof (void *));
458 mdb_free(qlstate, sizeof (ql_adapter_state_t));
459 return (DCMD_OK);
460 }
461
462 mdb_printf("%x\t%-11s", fwt->fw_class, fwverptr);
463
464 if (ql_hba.first == NULL) {
465 mdb_warn("failed to read ql_hba structure");
466 hbaptr = NULL;
467 } else {
468 hbaptr = (uintptr_t)ql_hba.first;
469 }
470
471 found = 0;
472 while (hbaptr != NULL) {
473
474 if (mdb_vread(qlstate,
475 sizeof (ql_adapter_state_t), hbaptr) ==
476 -1) {
477 mdb_warn("failed to read "
478 "ql_adapter_state at %p", hbaptr);
479 break;
480 }
481
482 if (qlstate->fw_class == fwt->fw_class) {
483 if (found == 0) {
484 mdb_printf("%x.%02x.%02x\t",
568 mdb_printf("\tqlc mdb library compiled version is: %s\n",
569 QL_VERSION);
570 mdb_printf("\tqlc driver version is: %s\n", qlcversion);
571
572 return (DCMD_OK);
573 }
574
575 if ((strcasecmp(argv[0].a_un.a_str, "on")) == 0) {
576 elswitch = TRUE;
577 } else if ((strcasecmp(argv[0].a_un.a_str, "off")) == 0) {
578 elswitch = FALSE;
579 } else {
580 return (DCMD_USAGE);
581 }
582
583 if (mdb_readvar(&ql_hba, "ql_hba") == -1) {
584 mdb_warn("failed to read ql_hba structure");
585 return (DCMD_ERR);
586 }
587
588 if (ql_hba.first == NULL) {
589 mdb_warn("failed to read ql_hba structure - is qlc loaded?");
590 return (DCMD_ERR);
591 }
592
593 if ((qlstate = (ql_adapter_state_t *)mdb_alloc(qlsize,
594 UM_SLEEP)) == NULL) {
595 mdb_warn("Unable to allocate memory for "
596 "ql_adapter_state\n");
597 return (DCMD_OK);
598 }
599
600 if ((strcasecmp(argv[1].a_un.a_str, "all")) == 0) {
601
602 if (argc != 2) {
603 mdb_free(qlstate, qlsize);
604 return (DCMD_USAGE);
605 }
606
607 hbaptr = (uintptr_t)ql_hba.first;
608
752 mdb_alloc(sizeof (ql_adapter_state_t), UM_SLEEP)) == NULL) {
753 mdb_warn("Unable to allocate memory for ql_adapter_state\n");
754 return (DCMD_OK);
755 }
756 if (mdb_vread(qlstate, sizeof (ql_adapter_state_t), addr) == -1) {
757 mdb_free(qlstate, sizeof (ql_adapter_state_t));
758 mdb_warn("failed to read ql_adapter_state at %p", addr);
759 return (DCMD_OK);
760 }
761
762 qlosc = (uintptr_t)qlstate->outstanding_cmds;
763 mdb_printf("qlc instance: %d, base addr = %llx, osc base = %p\n",
764 qlstate->instance, qlstate->hba.base_address, qlosc);
765
766 if ((qlsrb = (ql_srb_t *)mdb_alloc(sizeof (ql_srb_t), UM_SLEEP)) ==
767 NULL) {
768 mdb_free(qlstate, sizeof (ql_adapter_state_t));
769 mdb_warn("failed to allocate space for srb_t\n");
770 return (DCMD_OK);
771 }
772 for (indx = 0; indx < qlstate->osc_max_cnt; indx++, qlosc += 8) {
773 if (mdb_vread(&ptr1, 8, qlosc) == -1) {
774 mdb_warn("failed to read ptr1, indx=%d", indx);
775 break;
776 }
777 if (ptr1 == 0) {
778 continue;
779 }
780
781 mdb_printf("osc ptr = %p, indx = %xh\n", ptr1, indx);
782
783 if (mdb_vread(qlsrb, sizeof (ql_srb_t), ptr1) == -1) {
784 mdb_warn("failed to read ql_srb_t at %p", ptr1);
785 break;
786 }
787 (void) ql_doprint(ptr1, "struct ql_srb");
788 found++;
789 }
790
791 mdb_free(qlsrb, sizeof (ql_srb_t));
792 mdb_free(qlstate, sizeof (ql_adapter_state_t));
1602 const mdb_arg_t *argv)
1603 {
1604 ql_adapter_state_t *qlstate;
1605 uintptr_t hbaptr = NULL;
1606 ql_head_t ql_hba;
1607 uint32_t qlsize = sizeof (ql_adapter_state_t);
1608 int mdbs;
1609
1610 if ((mdbs = mdb_get_state()) == MDB_STATE_DEAD) {
1611 mdb_warn("Cannot change core file data (state=%xh)\n", mdbs);
1612 return (DCMD_OK);
1613 }
1614
1615 if ((qlstate = (ql_adapter_state_t *)mdb_alloc(qlsize,
1616 UM_SLEEP)) == NULL) {
1617 mdb_warn("Unable to allocate memory for ql_adapter_state\n");
1618 return (DCMD_OK);
1619 }
1620
1621 if (addr == NULL) {
1622 uint32_t instance;
1623
1624 if (argc == 0) {
1625 mdb_warn("must specify either the ha addr or "
1626 "the instance number\n");
1627 mdb_free(qlstate, qlsize);
1628 return (DCMD_OK);
1629 }
1630
1631 /*
1632 * find the specified instance in the ha list
1633 */
1634
1635 instance = (uint32_t)mdb_strtoull(argv[1].a_un.a_str);
1636
1637 if (mdb_readvar(&ql_hba, "ql_hba") == -1) {
1638 mdb_warn("failed to read ql_hba structure");
1639 mdb_free(qlstate, qlsize);
1640 return (DCMD_ERR);
1641 }
1642
1643 if (&ql_hba == NULL) {
1644 mdb_warn("failed to read ql_hba structure - "
1645 "is qlc loaded?");
1646 mdb_free(qlstate, qlsize);
1647 return (DCMD_ERR);
1648 }
1649
1650 hbaptr = (uintptr_t)ql_hba.first;
1651 while (hbaptr != NULL) {
1652
1653 if (mdb_vread(qlstate, qlsize, hbaptr) == -1) {
1654 mdb_free(qlstate, qlsize);
1655 mdb_warn("failed to read "
1753 if (mdb_getopts(argc, argv, 'v', MDB_OPT_SETBITS, TRUE, &verbose) !=
1754 argc) {
1755 return (DCMD_USAGE);
1756 }
1757
1758 /*
1759 * Get the adapter state struct which was passed
1760 */
1761 if ((ha = (ql_adapter_state_t *)mdb_alloc(sizeof (ql_adapter_state_t),
1762 UM_SLEEP)) == NULL) {
1763 mdb_warn("failed to allocate memory for ql_adapter_state\n");
1764 return (DCMD_OK);
1765 }
1766
1767 /*
1768 * show user which instances have valid f/w dumps available if
1769 * user has specified verbose option
1770 */
1771 if (mdb_readvar(&ql_hba, "ql_hba") == -1) {
1772 mdb_warn("failed to read ql_hba structure");
1773 } else if (ql_hba.first == NULL) {
1774 mdb_warn("failed to read ql_hba structure -- is qlc loaded?");
1775 } else if (verbose) {
1776 hbaptr = (uintptr_t)ql_hba.first;
1777 while (hbaptr != NULL) {
1778
1779 if (mdb_vread(ha, sizeof (ql_adapter_state_t),
1780 hbaptr) == -1) {
1781 mdb_free(ha, sizeof (ql_adapter_state_t));
1782 mdb_warn("failed read ql_adapter_state at %p",
1783 hbaptr);
1784 return (DCMD_OK);
1785 }
1786
1787 mdb_printf("instance %d:\n", ha->instance);
1788 (void) mdb_inc_indent((ulong_t)4);
1789
1790 if (ha->ql_dump_state == 0) {
1791 mdb_printf("no dump flags\n");
1792 } else {
1793 ql_dump_flags((uint64_t)ha->ql_dump_state,
1809 }
1810
1811 if (mdb_vread(ha, sizeof (ql_adapter_state_t), addr) == -1) {
1812 mdb_warn("failed to read ql_adapter_state at %p", addr);
1813 mdb_free(ha, sizeof (ql_adapter_state_t));
1814 return (DCMD_OK);
1815 }
1816
1817 /*
1818 * If its not a valid dump or there's not a f/w dump binary (???)
1819 * then bail out
1820 */
1821 if (((ha->ql_dump_state & QL_DUMP_VALID) == 0) ||
1822 (ha->ql_dump_ptr == NULL)) {
1823 mdb_warn("dump does not exist for instance %d (%x, %p)\n",
1824 ha->instance, ha->ql_dump_state, ha->ql_dump_ptr);
1825 mdb_free(ha, sizeof (ql_adapter_state_t));
1826 return (DCMD_OK);
1827 }
1828
1829 if (CFG_IST(ha, CFG_CTRL_24XX)) {
1830 (void) ql_24xx_dump_dcmd(ha, flags, argc, argv);
1831 } else if (CFG_IST(ha, CFG_CTRL_25XX)) {
1832 (void) ql_25xx_dump_dcmd(ha, flags, argc, argv);
1833 } else if (CFG_IST(ha, CFG_CTRL_81XX)) {
1834 (void) ql_81xx_dump_dcmd(ha, flags, argc, argv);
1835 } else if (CFG_IST(ha, CFG_CTRL_82XX | CFG_CTRL_27XX)) {
1836 (void) ql_8021_dump_dcmd(ha, flags, argc, argv);
1837 } else if (CFG_IST(ha, CFG_CTRL_83XX)) {
1838 (void) ql_8300_dump_dcmd(ha, flags, argc, argv);
1839 } else {
1840 (void) ql_23xx_dump_dcmd(ha, flags, argc, argv);
1841 }
1842
1843 mdb_free(ha, sizeof (ql_adapter_state_t));
1844
1845 return (DCMD_OK);
1846 }
1847
1848 /*
1849 * ql_8021_dump_dcmd
1850 * prints out a firmware dump buffer
1851 *
1852 * Input:
1853 * addr = User supplied address. (NB: nust be an ha)
1854 * flags = mdb flags.
1855 * argc = Number of user supplied args.
1856 * argv = Arg array.
1857 *
1858 * Returns:
1859 * DCMD_OK or DCMD_ERR
1860 *
1861 * Context:
1862 * User context.
1863 *
1864 */
1865 /*ARGSUSED*/
1866 static int
1867 ql_8021_dump_dcmd(ql_adapter_state_t *ha, uint_t flags, int argc,
1868 const mdb_arg_t *argv)
1869 {
1870 uint8_t *fw, *bp;
1871 uint32_t cnt = 0;
1872
1873 bp = fw = (uint8_t *)mdb_alloc(ha->ql_dump_size, UM_SLEEP);
1874
1875 if (mdb_vread(fw, ha->ql_dump_size,
1876 (uintptr_t)ha->ql_dump_ptr) == -1) {
1877 mdb_warn("failed to read ql_dump_ptr (no f/w dump active?)");
1878 mdb_free(fw, ha->ql_dump_size);
1879 return (DCMD_OK);
1880 }
1881
1882 while (cnt < ha->ql_dump_size) {
1883 mdb_printf("%02x ", *bp++);
1884 if (++cnt % 16 == 0) {
1885 mdb_printf("\n");
1886 }
1887 }
1888 if (cnt % 16 != 0) {
1889 mdb_printf("\n");
1890 }
1891
1892 mdb_free(fw, ha->ql_dump_size);
1893
1894 return (DCMD_OK);
1895 }
1896
1897 /*
1898 * ql_83xx_dump_dcmd
1899 * prints out a firmware dump buffer
1900 *
1901 * Input:
1902 * addr = User supplied address. (NB: must be an ha)
1903 * flags = mdb flags.
1904 * argc = Number of user supplied args.
1905 * argv = Arg array.
1906 *
1907 * Returns:
1908 * DCMD_OK or DCMD_ERR
1909 *
1910 * Context:
1911 * User context.
1912 *
1913 */
1914 /*ARGSUSED*/
1915 static int
1916 ql_8300_dump_dcmd(ql_adapter_state_t *ha, uint_t flags, int argc,
1917 const mdb_arg_t *argv)
1918 {
1919 ql_83xx_fw_dump_t *fw;
1920 ql_response_q_t **rsp_queues, *rsp_q;
1921 uint32_t cnt, cnt1, *dp, *dp2;
1922
1923 fw = mdb_alloc(ha->ql_dump_size, UM_SLEEP);
1924 rsp_queues = mdb_alloc(ha->rsp_queues_cnt *
1925 sizeof (ql_response_q_t *), UM_SLEEP);
1926 rsp_q = mdb_alloc(sizeof (ql_response_q_t), UM_SLEEP);
1927
1928 if (mdb_vread(fw, ha->ql_dump_size,
1929 (uintptr_t)ha->ql_dump_ptr) == -1 ||
1930 mdb_vread(rsp_queues, ha->rsp_queues_cnt *
1931 sizeof (ql_response_q_t *), (uintptr_t)ha->rsp_queues) == -1) {
1932 mdb_warn("failed to read fw_dump_buffer (no f/w dump active?)");
1933 mdb_free(rsp_q, sizeof (ql_response_q_t));
1934 mdb_free(rsp_queues, ha->rsp_queues_cnt *
1935 sizeof (ql_response_q_t *));
1936 mdb_free(fw, ha->ql_dump_size);
1937 return (DCMD_OK);
1938 }
1939
1940 mdb_printf("\nISP FW Version %d.%02d.%02d Attributes %X\n",
1941 ha->fw_major_version, ha->fw_minor_version,
1942 ha->fw_subminor_version, ha->fw_attributes);
1943
1944 mdb_printf("\nHCCR Register\n%08x\n", fw->hccr);
1945
1946 mdb_printf("\nR2H Status Register\n%08x\n", fw->r2h_status);
1947
1948 mdb_printf("\nAER Uncorrectable Error Status Register\n%08x\n",
1949 fw->aer_ues);
1950
1951 mdb_printf("\nHostRisc Registers");
1952 for (cnt = 0; cnt < sizeof (fw->hostrisc_reg) / 4; cnt++) {
1953 if (cnt % 8 == 0) {
1954 mdb_printf("\n");
1955 }
1956 mdb_printf("%08x ", fw->hostrisc_reg[cnt]);
1957 }
1958
1959 mdb_printf("\n\nPCIe Registers");
1960 for (cnt = 0; cnt < sizeof (fw->pcie_reg) / 4; cnt++) {
1961 if (cnt % 8 == 0) {
1962 mdb_printf("\n");
1963 }
1964 mdb_printf("%08x ", fw->pcie_reg[cnt]);
1965 }
1966
1967 dp = fw->req_rsp_ext_mem;
1968 for (cnt = 0; cnt < ha->rsp_queues_cnt; cnt++) {
1969 mdb_printf("\n\nQueue Pointers #%d:\n", cnt);
1970 for (cnt1 = 0; cnt1 < 4; cnt1++) {
1971 mdb_printf("%08x ", *dp++);
1972 }
1973 }
1974
1975 mdb_printf("\n\nHost Interface Registers");
1976 for (cnt = 0; cnt < sizeof (fw->host_reg) / 4; cnt++) {
1977 if (cnt % 8 == 0) {
1978 mdb_printf("\n");
1979 }
1980 mdb_printf("%08x ", fw->host_reg[cnt]);
1981 }
1982
1983 mdb_printf("\n\nShadow Registers");
1984 for (cnt = 0; cnt < sizeof (fw->shadow_reg) / 4; cnt++) {
1985 if (cnt % 8 == 0) {
1986 mdb_printf("\n");
1987 }
1988 mdb_printf("%08x ", fw->shadow_reg[cnt]);
1989 }
1990
1991 mdb_printf("\n\nRISC IO Register\n%08x", fw->risc_io);
1992
1993 mdb_printf("\n\nMailbox Registers");
1994 for (cnt = 0; cnt < sizeof (fw->mailbox_reg) / 2; cnt++) {
1995 if (cnt % 16 == 0) {
1996 mdb_printf("\n");
1997 }
1998 mdb_printf("%04x ", fw->mailbox_reg[cnt]);
1999 }
2000
2001 mdb_printf("\n\nXSEQ GP Registers");
2002 for (cnt = 0; cnt < sizeof (fw->xseq_gp_reg) / 4; cnt++) {
2003 if (cnt % 8 == 0) {
2004 mdb_printf("\n");
2005 }
2006 mdb_printf("%08x ", fw->xseq_gp_reg[cnt]);
2007 }
2008
2009 mdb_printf("\n\nXSEQ-0 Registers");
2010 for (cnt = 0; cnt < sizeof (fw->xseq_0_reg) / 4; cnt++) {
2011 if (cnt % 8 == 0) {
2012 mdb_printf("\n");
2013 }
2014 mdb_printf("%08x ", fw->xseq_0_reg[cnt]);
2015 }
2016
2017 mdb_printf("\n\nXSEQ-1 Registers");
2018 for (cnt = 0; cnt < sizeof (fw->xseq_1_reg) / 4; cnt++) {
2019 if (cnt % 8 == 0) {
2020 mdb_printf("\n");
2021 }
2022 mdb_printf("%08x ", fw->xseq_1_reg[cnt]);
2023 }
2024
2025 mdb_printf("\n\nXSEQ-2 Registers");
2026 for (cnt = 0; cnt < sizeof (fw->xseq_2_reg) / 4; cnt++) {
2027 if (cnt % 8 == 0) {
2028 mdb_printf("\n");
2029 }
2030 mdb_printf("%08x ", fw->xseq_2_reg[cnt]);
2031 }
2032
2033 mdb_printf("\n\nRSEQ GP Registers");
2034 for (cnt = 0; cnt < sizeof (fw->rseq_gp_reg) / 4; cnt++) {
2035 if (cnt % 8 == 0) {
2036 mdb_printf("\n");
2037 }
2038 mdb_printf("%08x ", fw->rseq_gp_reg[cnt]);
2039 }
2040
2041 mdb_printf("\n\nRSEQ-0 Registers");
2042 for (cnt = 0; cnt < sizeof (fw->rseq_0_reg) / 4; cnt++) {
2043 if (cnt % 8 == 0) {
2044 mdb_printf("\n");
2045 }
2046 mdb_printf("%08x ", fw->rseq_0_reg[cnt]);
2047 }
2048
2049 mdb_printf("\n\nRSEQ-1 Registers");
2050 for (cnt = 0; cnt < sizeof (fw->rseq_1_reg) / 4; cnt++) {
2051 if (cnt % 8 == 0) {
2052 mdb_printf("\n");
2053 }
2054 mdb_printf("%08x ", fw->rseq_1_reg[cnt]);
2055 }
2056
2057 mdb_printf("\n\nRSEQ-2 Registers");
2058 for (cnt = 0; cnt < sizeof (fw->rseq_2_reg) / 4; cnt++) {
2059 if (cnt % 8 == 0) {
2060 mdb_printf("\n");
2061 }
2062 mdb_printf("%08x ", fw->rseq_2_reg[cnt]);
2063 }
2064
2065 mdb_printf("\n\nRSEQ-3 Registers");
2066 for (cnt = 0; cnt < sizeof (fw->rseq_3_reg) / 4; cnt++) {
2067 if (cnt % 8 == 0) {
2068 mdb_printf("\n");
2069 }
2070 mdb_printf("%08x ", fw->rseq_3_reg[cnt]);
2071 }
2072
2073 mdb_printf("\n\nASEQ GP Registers");
2074 for (cnt = 0; cnt < sizeof (fw->aseq_gp_reg) / 4; cnt++) {
2075 if (cnt % 8 == 0) {
2076 mdb_printf("\n");
2077 }
2078 mdb_printf("%08x ", fw->aseq_gp_reg[cnt]);
2079 }
2080
2081 mdb_printf("\n\nASEQ-0 Registers");
2082 for (cnt = 0; cnt < sizeof (fw->aseq_0_reg) / 4; cnt++) {
2083 if (cnt % 8 == 0) {
2084 mdb_printf("\n");
2085 }
2086 mdb_printf("%08x ", fw->aseq_0_reg[cnt]);
2087 }
2088
2089 mdb_printf("\n\nASEQ-1 Registers");
2090 for (cnt = 0; cnt < sizeof (fw->aseq_1_reg) / 4; cnt++) {
2091 if (cnt % 8 == 0) {
2092 mdb_printf("\n");
2093 }
2094 mdb_printf("%08x ", fw->aseq_1_reg[cnt]);
2095 }
2096
2097 mdb_printf("\n\nASEQ-2 Registers");
2098 for (cnt = 0; cnt < sizeof (fw->aseq_2_reg) / 4; cnt++) {
2099 if (cnt % 8 == 0) {
2100 mdb_printf("\n");
2101 }
2102 mdb_printf("%08x ", fw->aseq_2_reg[cnt]);
2103 }
2104
2105 mdb_printf("\n\nASEQ-3 Registers");
2106 for (cnt = 0; cnt < sizeof (fw->aseq_3_reg) / 4; cnt++) {
2107 if (cnt % 8 == 0) {
2108 mdb_printf("\n");
2109 }
2110 mdb_printf("%08x ", fw->aseq_3_reg[cnt]);
2111 }
2112
2113 mdb_printf("\n\nCommand DMA Registers");
2114 for (cnt = 0; cnt < sizeof (fw->cmd_dma_reg) / 4; cnt++) {
2115 if (cnt % 8 == 0) {
2116 mdb_printf("\n");
2117 }
2118 mdb_printf("%08x ", fw->cmd_dma_reg[cnt]);
2119 }
2120
2121 mdb_printf("\n\nRequest0 Queue DMA Channel Registers");
2122 for (cnt = 0; cnt < sizeof (fw->req0_dma_reg) / 4; cnt++) {
2123 if (cnt % 8 == 0) {
2124 mdb_printf("\n");
2125 }
2126 mdb_printf("%08x ", fw->req0_dma_reg[cnt]);
2127 }
2128
2129 mdb_printf("\n\nResponse0 Queue DMA Channel Registers");
2130 for (cnt = 0; cnt < sizeof (fw->resp0_dma_reg) / 4; cnt++) {
2131 if (cnt % 8 == 0) {
2132 mdb_printf("\n");
2133 }
2134 mdb_printf("%08x ", fw->resp0_dma_reg[cnt]);
2135 }
2136
2137 mdb_printf("\n\nRequest1 Queue DMA Channel Registers");
2138 for (cnt = 0; cnt < sizeof (fw->req1_dma_reg) / 4; cnt++) {
2139 if (cnt % 8 == 0) {
2140 mdb_printf("\n");
2141 }
2142 mdb_printf("%08x ", fw->req1_dma_reg[cnt]);
2143 }
2144
2145 mdb_printf("\n\nXMT0 Data DMA Registers");
2146 for (cnt = 0; cnt < sizeof (fw->xmt0_dma_reg) / 4; cnt++) {
2147 if (cnt % 8 == 0) {
2148 mdb_printf("\n");
2149 }
2150 mdb_printf("%08x ", fw->xmt0_dma_reg[cnt]);
2151 }
2152
2153 mdb_printf("\n\nXMT1 Data DMA Registers");
2154 for (cnt = 0; cnt < sizeof (fw->xmt1_dma_reg) / 4; cnt++) {
2155 if (cnt % 8 == 0) {
2156 mdb_printf("\n");
2157 }
2158 mdb_printf("%08x ", fw->xmt1_dma_reg[cnt]);
2159 }
2160
2161 mdb_printf("\n\nXMT2 Data DMA Registers");
2162 for (cnt = 0; cnt < sizeof (fw->xmt2_dma_reg) / 4; cnt++) {
2163 if (cnt % 8 == 0) {
2164 mdb_printf("\n");
2165 }
2166 mdb_printf("%08x ", fw->xmt2_dma_reg[cnt]);
2167 }
2168
2169 mdb_printf("\n\nXMT3 Data DMA Registers");
2170 for (cnt = 0; cnt < sizeof (fw->xmt3_dma_reg) / 4; cnt++) {
2171 if (cnt % 8 == 0) {
2172 mdb_printf("\n");
2173 }
2174 mdb_printf("%08x ", fw->xmt3_dma_reg[cnt]);
2175 }
2176
2177 mdb_printf("\n\nXMT4 Data DMA Registers");
2178 for (cnt = 0; cnt < sizeof (fw->xmt4_dma_reg) / 4; cnt++) {
2179 if (cnt % 8 == 0) {
2180 mdb_printf("\n");
2181 }
2182 mdb_printf("%08x ", fw->xmt4_dma_reg[cnt]);
2183 }
2184
2185 mdb_printf("\n\nXMT Data DMA Common Registers");
2186 for (cnt = 0; cnt < sizeof (fw->xmt_data_dma_reg) / 4; cnt++) {
2187 if (cnt % 8 == 0) {
2188 mdb_printf("\n");
2189 }
2190 mdb_printf("%08x ", fw->xmt_data_dma_reg[cnt]);
2191 }
2192
2193 mdb_printf("\n\nRCV Thread 0 Data DMA Registers");
2194 for (cnt = 0; cnt < sizeof (fw->rcvt0_data_dma_reg) / 4; cnt++) {
2195 if (cnt % 8 == 0) {
2196 mdb_printf("\n");
2197 }
2198 mdb_printf("%08x ", fw->rcvt0_data_dma_reg[cnt]);
2199 }
2200
2201 mdb_printf("\n\nRCV Thread 1 Data DMA Registers");
2202 for (cnt = 0; cnt < sizeof (fw->rcvt1_data_dma_reg) / 4; cnt++) {
2203 if (cnt % 8 == 0) {
2204 mdb_printf("\n");
2205 }
2206 mdb_printf("%08x ", fw->rcvt1_data_dma_reg[cnt]);
2207 }
2208
2209 mdb_printf("\n\nRISC GP Registers");
2210 for (cnt = 0; cnt < sizeof (fw->risc_gp_reg) / 4; cnt++) {
2211 if (cnt % 8 == 0) {
2212 mdb_printf("\n");
2213 }
2214 mdb_printf("%08x ", fw->risc_gp_reg[cnt]);
2215 }
2216
2217 mdb_printf("\n\nLMC Registers");
2218 for (cnt = 0; cnt < sizeof (fw->lmc_reg) / 4; cnt++) {
2219 if (cnt % 8 == 0) {
2220 mdb_printf("\n");
2221 }
2222 mdb_printf("%08x ", fw->lmc_reg[cnt]);
2223 }
2224
2225 mdb_printf("\n\nFPM Hardware Registers");
2226 for (cnt = 0; cnt < sizeof (fw->fpm_hdw_reg) / 4; cnt++) {
2227 if (cnt % 8 == 0) {
2228 mdb_printf("\n");
2229 }
2230 mdb_printf("%08x ", fw->fpm_hdw_reg[cnt]);
2231 }
2232
2233 mdb_printf("\n\nRQ0 Array Registers");
2234 for (cnt = 0; cnt < sizeof (fw->rq0_array_reg) / 4; cnt++) {
2235 if (cnt % 8 == 0) {
2236 mdb_printf("\n");
2237 }
2238 mdb_printf("%08x ", fw->rq0_array_reg[cnt]);
2239 }
2240
2241 mdb_printf("\n\nRQ1 Array Registers");
2242 for (cnt = 0; cnt < sizeof (fw->rq1_array_reg) / 4; cnt++) {
2243 if (cnt % 8 == 0) {
2244 mdb_printf("\n");
2245 }
2246 mdb_printf("%08x ", fw->rq1_array_reg[cnt]);
2247 }
2248
2249 mdb_printf("\n\nRP0 Array Registers");
2250 for (cnt = 0; cnt < sizeof (fw->rp0_array_reg) / 4; cnt++) {
2251 if (cnt % 8 == 0) {
2252 mdb_printf("\n");
2253 }
2254 mdb_printf("%08x ", fw->rp0_array_reg[cnt]);
2255 }
2256
2257 mdb_printf("\n\nRP1 Array Registers");
2258 for (cnt = 0; cnt < sizeof (fw->rp1_array_reg) / 4; cnt++) {
2259 if (cnt % 8 == 0) {
2260 mdb_printf("\n");
2261 }
2262 mdb_printf("%08x ", fw->rp1_array_reg[cnt]);
2263 }
2264
2265 mdb_printf("\n\nAT0 Array Registers");
2266 for (cnt = 0; cnt < sizeof (fw->ato_array_reg) / 4; cnt++) {
2267 if (cnt % 8 == 0) {
2268 mdb_printf("\n");
2269 }
2270 mdb_printf("%08x ", fw->ato_array_reg[cnt]);
2271 }
2272
2273 mdb_printf("\n\nQueue Control Registers");
2274 for (cnt = 0; cnt < sizeof (fw->queue_control_reg) / 4; cnt++) {
2275 if (cnt % 8 == 0) {
2276 mdb_printf("\n");
2277 }
2278 mdb_printf("%08x ", fw->queue_control_reg[cnt]);
2279 }
2280
2281 mdb_printf("\n\nFB Hardware Registers");
2282 for (cnt = 0; cnt < sizeof (fw->fb_hdw_reg) / 4; cnt++) {
2283 if (cnt % 8 == 0) {
2284 mdb_printf("\n");
2285 }
2286 mdb_printf("%08x ", fw->fb_hdw_reg[cnt]);
2287 }
2288
2289 mdb_printf("\n\nCode RAM");
2290 for (cnt = 0; cnt < sizeof (fw->code_ram) / 4; cnt++) {
2291 if (cnt % 8 == 0) {
2292 mdb_printf("\n%08x: ", cnt + 0x20000);
2293 }
2294 mdb_printf("%08x ", fw->code_ram[cnt]);
2295 }
2296
2297 mdb_printf("\n\nExternal Memory");
2298 dp = (uint32_t *)(void *)((caddr_t)fw->req_rsp_ext_mem +
2299 fw->req_q_size[0] + fw->req_q_size[1] + fw->rsp_q_size +
2300 (ha->rsp_queues_cnt * 16));
2301 for (cnt = 0; cnt < ha->fw_ext_memory_size / 4; cnt++) {
2302 if (cnt % 8 == 0) {
2303 mdb_printf("\n%08x: ", cnt + 0x100000);
2304 }
2305 mdb_printf("%08x ", *dp++);
2306 }
2307
2308 mdb_printf("\n\n[<==END] ISP Debug Dump");
2309
2310 dp = fw->req_rsp_ext_mem + (ha->rsp_queues_cnt * 4);
2311 for (cnt = 0; cnt < 2 && fw->req_q_size[cnt]; cnt++) {
2312 dp2 = dp;
2313 for (cnt1 = 0; cnt1 < fw->req_q_size[cnt] / 4; cnt1++) {
2314 if (*dp2++) {
2315 break;
2316 }
2317 }
2318 if (cnt1 == fw->req_q_size[cnt] / 4) {
2319 dp = dp2;
2320 continue;
2321 }
2322 mdb_printf("\n\nRequest Queue\nQueue 0%d:", cnt);
2323 for (cnt1 = 0; cnt1 < fw->req_q_size[cnt] / 4; cnt1++) {
2324 if (cnt1 % 8 == 0) {
2325 mdb_printf("\n%08x: ", cnt1);
2326 }
2327 mdb_printf("%08x ", *dp++);
2328 }
2329 }
2330
2331 for (cnt = 0; cnt < ha->rsp_queues_cnt; cnt++) {
2332 if (mdb_vread(rsp_q, sizeof (ql_response_q_t),
2333 (uintptr_t)rsp_queues[cnt]) == -1) {
2334 mdb_warn("failed to read ha->rsp_queues[%d]", cnt);
2335 break;
2336 }
2337 dp2 = dp;
2338 for (cnt1 = 0; cnt1 < rsp_q->rsp_ring.size / 4; cnt1++) {
2339 if (*dp2++) {
2340 break;
2341 }
2342 }
2343 if (cnt1 == rsp_q->rsp_ring.size / 4) {
2344 dp = dp2;
2345 continue;
2346 }
2347 mdb_printf("\n\nResponse Queue\nQueue 0%d:", cnt);
2348
2349 for (cnt1 = 0; cnt1 < rsp_q->rsp_ring.size / 4; cnt1++) {
2350 if (cnt1 % 8 == 0) {
2351 mdb_printf("\n%08x: ", cnt1);
2352 }
2353 mdb_printf("%08x ", *dp++);
2354 }
2355 }
2356
2357 if (ha->fwexttracebuf.dma_handle != NULL) {
2358 uint32_t cnt_b;
2359 uint32_t *w32 = ha->fwexttracebuf.bp;
2360
2361 mdb_printf("\n\nExtended Trace Buffer Memory");
2362 /* show data address as a byte address, data as long words */
2363 for (cnt = 0; cnt < FWEXTSIZE / 4; cnt++) {
2364 cnt_b = cnt * 4;
2365 if (cnt_b % 32 == 0) {
2366 mdb_printf("\n%08x: ", w32 + cnt_b);
2367 }
2368 mdb_printf("%08x ", fw->ext_trace_buf[cnt]);
2369 }
2370 }
2371
2372 if (ha->fwfcetracebuf.dma_handle != NULL) {
2373 uint32_t cnt_b;
2374 uint32_t *w32 = ha->fwfcetracebuf.bp;
2375
2376 mdb_printf("\n\nFC Event Trace Buffer Memory");
2377 /* show data address as a byte address, data as long words */
2378 for (cnt = 0; cnt < FWFCESIZE / 4; cnt++) {
2379 cnt_b = cnt * 4;
2380 if (cnt_b % 32 == 0) {
2381 mdb_printf("\n%08x: ", w32 + cnt_b);
2382 }
2383 mdb_printf("%08x ", fw->fce_trace_buf[cnt]);
2384 }
2385 }
2386
2387 mdb_free(rsp_q, sizeof (ql_response_q_t));
2388 mdb_free(rsp_queues, ha->rsp_queues_cnt * sizeof (ql_response_q_t *));
2389 mdb_free(fw, ha->ql_dump_size);
2390
2391 mdb_printf("\n\nreturn exit\n");
2392
2393 return (DCMD_OK);
2394 }
2395
2396 /*
2397 * ql_23xx_dump_dcmd
2398 * prints out a firmware dump buffer
2399 *
2400 * Input:
2401 * addr = User supplied address. (NB: nust be an ha)
2402 * flags = mdb flags.
2403 * argc = Number of user supplied args.
2404 * argv = Arg array.
2405 *
2406 * Returns:
2407 * DCMD_OK or DCMD_ERR
2408 *
2409 * Context:
2410 * User context.
2411 *
2412 */
2413 /*ARGSUSED*/
2414 static int
2415 ql_23xx_dump_dcmd(ql_adapter_state_t *ha, uint_t flags, int argc,
2416 const mdb_arg_t *argv)
2417 {
2418 ql_fw_dump_t *fw;
2419 uint32_t cnt = 0;
2420 int mbox_cnt;
2421
2422 fw = (ql_fw_dump_t *)mdb_alloc(ha->ql_dump_size, UM_SLEEP);
2423
2424 if (mdb_vread(fw, ha->ql_dump_size,
2425 (uintptr_t)ha->ql_dump_ptr) == -1) {
2426 mdb_warn("failed to read ql_dump_ptr (no f/w dump active?)");
2427 mdb_free(fw, ha->ql_dump_size);
2428 return (DCMD_OK);
2429 }
2430
2431 if (ha->cfg_flags & CFG_CTRL_23XX) {
2432 mdb_printf("\nISP 2300IP ");
2433 } else if (ha->cfg_flags & CFG_CTRL_63XX) {
2434 mdb_printf("\nISP 2322/6322FLX ");
2435 } else {
2436 mdb_printf("\nISP 2200IP ");
2437 }
2438
2439 mdb_printf("Firmware Version %d.%d.%d\n",
2440 ha->fw_major_version, ha->fw_minor_version,
2441 ha->fw_subminor_version);
2442
2443 mdb_printf("\nPBIU Registers:");
2444 for (cnt = 0; cnt < sizeof (fw->pbiu_reg) / 2; cnt++) {
2445 if (cnt % 8 == 0) {
2446 mdb_printf("\n");
2447 }
2448 mdb_printf("%04x ", fw->pbiu_reg[cnt]);
2449 }
2450
2451 if (ha->cfg_flags & CFG_CTRL_2363) {
2452 mdb_printf("\n\nReqQ-RspQ-Risc2Host Status registers:");
2453 for (cnt = 0; cnt < sizeof (fw->risc_host_reg) / 2; cnt++) {
2454 if (cnt % 8 == 0) {
2455 mdb_printf("\n");
2456 }
2457 mdb_printf("%04x ", fw->risc_host_reg[cnt]);
2458 }
2459 }
2460
2461 mdb_printf("\n\nMailbox Registers:");
2462 mbox_cnt = ha->cfg_flags & CFG_CTRL_2363 ? 16 : 8;
2463 for (cnt = 0; cnt < mbox_cnt; cnt++) {
2464 if (cnt % 8 == 0) {
2465 mdb_printf("\n");
2466 }
2467 mdb_printf("%04x ", fw->mailbox_reg[cnt]);
2468 }
2469
2470 if (ha->cfg_flags & CFG_CTRL_2363) {
2471 mdb_printf("\n\nAuto Request Response DMA Registers:");
2472 for (cnt = 0; cnt < sizeof (fw->resp_dma_reg) / 2; cnt++) {
2473 if (cnt % 8 == 0) {
2474 mdb_printf("\n");
2475 }
2476 mdb_printf("%04x ", fw->resp_dma_reg[cnt]);
2477 }
2478 }
2479
2480 mdb_printf("\n\nDMA Registers:");
2481 for (cnt = 0; cnt < sizeof (fw->dma_reg) / 2; cnt++) {
2482 if (cnt % 8 == 0) {
2483 mdb_printf("\n");
2484 }
2485 mdb_printf("%04x ", fw->dma_reg[cnt]);
2486 }
2487
2488 mdb_printf("\n\nRISC Hardware Registers:");
2489 for (cnt = 0; cnt < sizeof (fw->risc_hdw_reg) / 2; cnt++) {
2490 if (cnt % 8 == 0) {
2543
2544 mdb_printf("\n\nRISC GP6 Registers:");
2545 for (cnt = 0; cnt < sizeof (fw->risc_gp6_reg) / 2; cnt++) {
2546 if (cnt % 8 == 0) {
2547 mdb_printf("\n");
2548 }
2549 mdb_printf("%04x ", fw->risc_gp6_reg[cnt]);
2550 }
2551
2552 mdb_printf("\n\nRISC GP7 Registers:");
2553 for (cnt = 0; cnt < sizeof (fw->risc_gp7_reg) / 2; cnt++) {
2554 if (cnt % 8 == 0) {
2555 mdb_printf("\n");
2556 }
2557 mdb_printf("%04x ", fw->risc_gp7_reg[cnt]);
2558 }
2559
2560 mdb_printf("\n\nFrame Buffer Hardware Registers:");
2561 for (cnt = 0; cnt < sizeof (fw->frame_buf_hdw_reg) / 2; cnt++) {
2562 if ((cnt == 16) &&
2563 ((ha->cfg_flags & CFG_CTRL_2363) == 0)) {
2564 break;
2565 }
2566 if (cnt % 8 == 0) {
2567 mdb_printf("\n");
2568 }
2569 mdb_printf("%04x ", fw->frame_buf_hdw_reg[cnt]);
2570 }
2571
2572 mdb_printf("\n\nFPM B0 Registers:");
2573 for (cnt = 0; cnt < sizeof (fw->fpm_b0_reg) / 2; cnt++) {
2574 if (cnt % 8 == 0) {
2575 mdb_printf("\n");
2576 }
2577 mdb_printf("%04x ", fw->fpm_b0_reg[cnt]);
2578 }
2579
2580 mdb_printf("\n\nFPM B1 Registers:");
2581 for (cnt = 0; cnt < sizeof (fw->fpm_b1_reg) / 2; cnt++) {
2582 if (cnt % 8 == 0) {
2583 mdb_printf("\n");
2584 }
2585 mdb_printf("%04x ", fw->fpm_b1_reg[cnt]);
2586 }
2587
2588 if (ha->cfg_flags & CFG_CTRL_2363) {
2589 mdb_printf("\n\nCode RAM Dump:");
2590 for (cnt = 0; cnt < sizeof (fw->risc_ram) / 2; cnt++) {
2591 if (cnt % 8 == 0) {
2592 mdb_printf("\n%05x: ", cnt + 0x0800);
2593 }
2594 mdb_printf("%04x ", fw->risc_ram[cnt]);
2595 }
2596
2597 mdb_printf("\n\nStack RAM Dump:");
2598 for (cnt = 0; cnt < sizeof (fw->stack_ram) / 2; cnt++) {
2599 if (cnt % 8 == 0) {
2600 mdb_printf("\n%05x: ", cnt + 0x010000);
2601 }
2602 mdb_printf("%04x ", fw->stack_ram[cnt]);
2603 }
2604
2605 mdb_printf("\n\nData RAM Dump:");
2606 for (cnt = 0; cnt < sizeof (fw->data_ram) / 2; cnt++) {
2607 if (cnt % 8 == 0) {
2608 mdb_printf("\n%05x: ", cnt + 0x010800);
2973 *
2974 * Input:
2975 * addr = User supplied address. (NB: nust be an ha)
2976 * flags = mdb flags.
2977 * argc = Number of user supplied args.
2978 * argv = Arg array.
2979 *
2980 * Returns:
2981 * DCMD_OK or DCMD_ERR
2982 *
2983 * Context:
2984 * User context.
2985 *
2986 */
2987 /*ARGSUSED*/
2988 static int
2989 ql_25xx_dump_dcmd(ql_adapter_state_t *ha, uint_t flags, int argc,
2990 const mdb_arg_t *argv)
2991 {
2992 ql_25xx_fw_dump_t *fw;
2993 ql_response_q_t **rsp_queues, *rsp_q;
2994 uint32_t cnt, cnt1, *dp, *dp2;
2995
2996 fw = (ql_25xx_fw_dump_t *)mdb_alloc(ha->ql_dump_size, UM_SLEEP);
2997 rsp_queues = mdb_alloc(ha->rsp_queues_cnt *
2998 sizeof (ql_response_q_t *), UM_SLEEP);
2999 rsp_q = mdb_alloc(sizeof (ql_response_q_t), UM_SLEEP);
3000
3001 if (mdb_vread(fw, ha->ql_dump_size,
3002 (uintptr_t)ha->ql_dump_ptr) == -1 ||
3003 mdb_vread(rsp_queues, ha->rsp_queues_cnt *
3004 sizeof (ql_response_q_t *), (uintptr_t)ha->rsp_queues) == -1) {
3005 mdb_warn("failed to read ql_dump_ptr (no f/w dump active?)");
3006 mdb_free(rsp_q, sizeof (ql_response_q_t));
3007 mdb_free(rsp_queues, ha->rsp_queues_cnt *
3008 sizeof (ql_response_q_t *));
3009 mdb_free(fw, ha->ql_dump_size);
3010 return (DCMD_OK);
3011 }
3012
3013 mdb_printf("\nISP FW Version %d.%02d.%02d Attributes %X\n",
3014 ha->fw_major_version, ha->fw_minor_version,
3015 ha->fw_subminor_version, ha->fw_attributes);
3016
3017 mdb_printf("\nHCCR Register\n%08x\n", fw->hccr);
3018 mdb_printf("\nR2H Register\n%08x\n", fw->r2h_status);
3019 mdb_printf("\nAER Uncorrectable Error Status Register\n%08x\n",
3020 fw->aer_ues);
3021
3022 mdb_printf("\n\nHostRisc Registers");
3023 for (cnt = 0; cnt < sizeof (fw->hostrisc_reg) / 4; cnt++) {
3024 if (cnt % 8 == 0) {
3025 mdb_printf("\n");
3026 }
3027 mdb_printf("%08x ", fw->hostrisc_reg[cnt]);
3028 }
3029
3030 mdb_printf("\n\nPCIe Registers");
3031 for (cnt = 0; cnt < sizeof (fw->pcie_reg) / 4; cnt++) {
3032 if (cnt % 8 == 0) {
3033 mdb_printf("\n");
3034 }
3035 mdb_printf("%08x ", fw->pcie_reg[cnt]);
3036 }
3037
3038 mdb_printf("\n\nHost Interface Registers");
3039 for (cnt = 0; cnt < sizeof (fw->host_reg) / 4; cnt++) {
3040 if (cnt % 8 == 0) {
3272 mdb_printf("%08x ", fw->fpm_hdw_reg[cnt]);
3273 }
3274
3275 mdb_printf("\n\nFB Hardware Registers");
3276 for (cnt = 0; cnt < sizeof (fw->fb_hdw_reg) / 4; cnt++) {
3277 if (cnt % 8 == 0) {
3278 mdb_printf("\n");
3279 }
3280 mdb_printf("%08x ", fw->fb_hdw_reg[cnt]);
3281 }
3282
3283 mdb_printf("\n\nCode RAM");
3284 for (cnt = 0; cnt < sizeof (fw->code_ram) / 4; cnt++) {
3285 if (cnt % 8 == 0) {
3286 mdb_printf("\n%08x: ", cnt + 0x20000);
3287 }
3288 mdb_printf("%08x ", fw->code_ram[cnt]);
3289 }
3290
3291 mdb_printf("\n\nExternal Memory");
3292 dp = (uint32_t *)(void *)((caddr_t)fw->req_rsp_ext_mem +
3293 fw->req_q_size[0] + fw->req_q_size[1] + fw->rsp_q_size +
3294 (ha->rsp_queues_cnt * 16));
3295 for (cnt = 0; cnt < ha->fw_ext_memory_size / 4; cnt++) {
3296 if (cnt % 8 == 0) {
3297 mdb_printf("\n%08x: ", cnt + 0x100000);
3298 }
3299 mdb_printf("%08x ", *dp++);
3300 }
3301
3302 mdb_printf("\n[<==END] ISP Debug Dump");
3303
3304 mdb_printf("\n\nRequest Queue");
3305
3306 dp = fw->req_rsp_ext_mem + (ha->rsp_queues_cnt * 4);
3307 for (cnt = 0; cnt < 2 && fw->req_q_size[cnt]; cnt++) {
3308 dp2 = dp;
3309 for (cnt1 = 0; cnt1 < fw->req_q_size[cnt] / 4; cnt1++) {
3310 if (*dp2++) {
3311 break;
3312 }
3313 }
3314 if (cnt1 == fw->req_q_size[cnt] / 4) {
3315 dp = dp2;
3316 continue;
3317 }
3318 mdb_printf("\n\nRequest Queue\nQueue 0%d:", cnt);
3319 for (cnt1 = 0; cnt1 < fw->req_q_size[cnt] / 4; cnt1++) {
3320 if (cnt1 % 8 == 0) {
3321 mdb_printf("\n%08x: ", cnt1);
3322 }
3323 mdb_printf("%08x ", *dp++);
3324 }
3325 }
3326
3327 for (cnt = 0; cnt < ha->rsp_queues_cnt; cnt++) {
3328 if (mdb_vread(rsp_q, sizeof (ql_response_q_t),
3329 (uintptr_t)rsp_queues[cnt]) == -1) {
3330 mdb_warn("failed to read ha->rsp_queues[%d]", cnt);
3331 break;
3332 }
3333 dp2 = dp;
3334 for (cnt1 = 0; cnt1 < rsp_q->rsp_ring.size / 4; cnt1++) {
3335 if (*dp2++) {
3336 break;
3337 }
3338 }
3339 if (cnt1 == rsp_q->rsp_ring.size / 4) {
3340 dp = dp2;
3341 continue;
3342 }
3343 mdb_printf("\n\nResponse Queue\nQueue 0%d:", cnt);
3344
3345 for (cnt1 = 0; cnt1 < rsp_q->rsp_ring.size / 4; cnt1++) {
3346 if (cnt1 % 8 == 0) {
3347 mdb_printf("\n%08x: ", cnt1);
3348 }
3349 mdb_printf("%08x ", *dp++);
3350 }
3351 }
3352
3353 if ((ha->cfg_flags & CFG_ENABLE_FWEXTTRACE) &&
3354 (ha->fwexttracebuf.bp != NULL)) {
3355 uint32_t cnt_b = 0;
3356 uint32_t *w32 = ha->fwexttracebuf.bp;
3357
3358 mdb_printf("\n\nExtended Trace Buffer Memory");
3359 /* show data address as a byte address, data as long words */
3360 for (cnt = 0; cnt < FWEXTSIZE / 4; cnt++) {
3361 cnt_b = cnt * 4;
3362 if (cnt_b % 32 == 0) {
3363 mdb_printf("\n%08x: ", w32 + cnt_b);
3364 }
3365 mdb_printf("%08x ", fw->ext_trace_buf[cnt]);
3366 }
3367 }
3368
3369 if ((ha->cfg_flags & CFG_ENABLE_FWFCETRACE) &&
3370 (ha->fwfcetracebuf.bp != NULL)) {
3371 uint32_t cnt_b = 0;
3372 uint32_t *w32 = ha->fwfcetracebuf.bp;
3373
3374 mdb_printf("\n\nFC Event Trace Buffer Memory");
3375 /* show data address as a byte address, data as long words */
3376 for (cnt = 0; cnt < FWFCESIZE / 4; cnt++) {
3377 cnt_b = cnt * 4;
3378 if (cnt_b % 32 == 0) {
3379 mdb_printf("\n%08x: ", w32 + cnt_b);
3380 }
3381 mdb_printf("%08x ", fw->fce_trace_buf[cnt]);
3382 }
3383 }
3384
3385 mdb_free(rsp_q, sizeof (ql_response_q_t));
3386 mdb_free(rsp_queues, ha->rsp_queues_cnt * sizeof (ql_response_q_t *));
3387 mdb_free(fw, ha->ql_dump_size);
3388
3389 mdb_printf("\n\nreturn exit\n");
3390
3391 return (DCMD_OK);
3392 }
3393
3394 /*
3395 * ql_81xx_dump_dcmd
3396 * prints out a firmware dump buffer
3397 *
3398 * Input:
3399 * addr = User supplied address. (NB: nust be an ha)
3400 * flags = mdb flags.
3401 * argc = Number of user supplied args.
3402 * argv = Arg array.
3403 *
3404 * Returns:
3405 * DCMD_OK or DCMD_ERR
3406 *
3407 * Context:
3408 * User context.
3409 *
3410 */
3411 /*ARGSUSED*/
3412 static int
3413 ql_81xx_dump_dcmd(ql_adapter_state_t *ha, uint_t flags, int argc,
3414 const mdb_arg_t *argv)
3415 {
3416 ql_81xx_fw_dump_t *fw;
3417 ql_response_q_t **rsp_queues, *rsp_q;
3418 uint32_t cnt, cnt1, *dp, *dp2;
3419
3420 fw = (ql_81xx_fw_dump_t *)mdb_alloc(ha->ql_dump_size, UM_SLEEP);
3421 rsp_queues = mdb_alloc(ha->rsp_queues_cnt *
3422 sizeof (ql_response_q_t *), UM_SLEEP);
3423 rsp_q = mdb_alloc(sizeof (ql_response_q_t), UM_SLEEP);
3424
3425 if (mdb_vread(fw, ha->ql_dump_size,
3426 (uintptr_t)ha->ql_dump_ptr) == -1 ||
3427 mdb_vread(rsp_queues, ha->rsp_queues_cnt *
3428 sizeof (ql_response_q_t *), (uintptr_t)ha->rsp_queues) == -1) {
3429 mdb_warn("failed to read ql_dump_ptr (no f/w dump active?)");
3430 mdb_free(rsp_q, sizeof (ql_response_q_t));
3431 mdb_free(rsp_queues, ha->rsp_queues_cnt *
3432 sizeof (ql_response_q_t *));
3433 mdb_free(fw, ha->ql_dump_size);
3434 return (DCMD_OK);
3435 }
3436
3437 mdb_printf("\nISP FW Version %d.%02d.%02d Attributes %X\n",
3438 ha->fw_major_version, ha->fw_minor_version,
3439 ha->fw_subminor_version, ha->fw_attributes);
3440
3441 mdb_printf("\nHCCR Register\n%08x\n", fw->hccr);
3442
3443 mdb_printf("\nR2H Register\n%08x\n", fw->r2h_status);
3444
3445 mdb_printf("\nAER Uncorrectable Error Status Register\n%08x\n",
3446 fw->aer_ues);
3447
3448 mdb_printf("\n\nHostRisc Registers");
3449 for (cnt = 0; cnt < sizeof (fw->hostrisc_reg) / 4; cnt++) {
3450 if (cnt % 8 == 0) {
3451 mdb_printf("\n");
3452 }
3453 mdb_printf("%08x ", fw->hostrisc_reg[cnt]);
3454 }
3455
3456 mdb_printf("\n\nPCIe Registers");
3457 for (cnt = 0; cnt < sizeof (fw->pcie_reg) / 4; cnt++) {
3458 if (cnt % 8 == 0) {
3459 mdb_printf("\n");
3460 }
3461 mdb_printf("%08x ", fw->pcie_reg[cnt]);
3462 }
3463
3464 mdb_printf("\n\nHost Interface Registers");
3465 for (cnt = 0; cnt < sizeof (fw->host_reg) / 4; cnt++) {
3466 if (cnt % 8 == 0) {
3467 mdb_printf("\n");
3698 mdb_printf("%08x ", fw->fpm_hdw_reg[cnt]);
3699 }
3700
3701 mdb_printf("\n\nFB Hardware Registers");
3702 for (cnt = 0; cnt < sizeof (fw->fb_hdw_reg) / 4; cnt++) {
3703 if (cnt % 8 == 0) {
3704 mdb_printf("\n");
3705 }
3706 mdb_printf("%08x ", fw->fb_hdw_reg[cnt]);
3707 }
3708
3709 mdb_printf("\n\nCode RAM");
3710 for (cnt = 0; cnt < sizeof (fw->code_ram) / 4; cnt++) {
3711 if (cnt % 8 == 0) {
3712 mdb_printf("\n%08x: ", cnt + 0x20000);
3713 }
3714 mdb_printf("%08x ", fw->code_ram[cnt]);
3715 }
3716
3717 mdb_printf("\n\nExternal Memory");
3718 dp = (uint32_t *)(void *)((caddr_t)fw->req_rsp_ext_mem +
3719 fw->req_q_size[0] + fw->req_q_size[1] + fw->rsp_q_size +
3720 (ha->rsp_queues_cnt * 16));
3721 for (cnt = 0; cnt < ha->fw_ext_memory_size / 4; cnt++) {
3722 if (cnt % 8 == 0) {
3723 mdb_printf("\n%08x: ", cnt + 0x100000);
3724 }
3725 mdb_printf("%08x ", *dp++);
3726 }
3727
3728 mdb_printf("\n[<==END] ISP Debug Dump");
3729
3730 mdb_printf("\n\nRequest Queue");
3731
3732 dp = fw->req_rsp_ext_mem + (ha->rsp_queues_cnt * 4);
3733 for (cnt = 0; cnt < 2 && fw->req_q_size[cnt]; cnt++) {
3734 dp2 = dp;
3735 for (cnt1 = 0; cnt1 < fw->req_q_size[cnt] / 4; cnt1++) {
3736 if (*dp2++) {
3737 break;
3738 }
3739 }
3740 if (cnt1 == fw->req_q_size[cnt] / 4) {
3741 dp = dp2;
3742 continue;
3743 }
3744 mdb_printf("\n\nRequest Queue\nQueue 0%d:", cnt);
3745 for (cnt1 = 0; cnt1 < fw->req_q_size[cnt] / 4; cnt1++) {
3746 if (cnt1 % 8 == 0) {
3747 mdb_printf("\n%08x: ", cnt1);
3748 }
3749 mdb_printf("%08x ", *dp++);
3750 }
3751 }
3752
3753 for (cnt = 0; cnt < ha->rsp_queues_cnt; cnt++) {
3754 if (mdb_vread(rsp_q, sizeof (ql_response_q_t),
3755 (uintptr_t)rsp_queues[cnt]) == -1) {
3756 mdb_warn("failed to read ha->rsp_queues[%d]", cnt);
3757 break;
3758 }
3759 dp2 = dp;
3760 for (cnt1 = 0; cnt1 < rsp_q->rsp_ring.size / 4; cnt1++) {
3761 if (*dp2++) {
3762 break;
3763 }
3764 }
3765 if (cnt1 == rsp_q->rsp_ring.size / 4) {
3766 dp = dp2;
3767 continue;
3768 }
3769 mdb_printf("\n\nResponse Queue\nQueue 0%d:", cnt);
3770
3771 for (cnt1 = 0; cnt1 < rsp_q->rsp_ring.size / 4; cnt1++) {
3772 if (cnt1 % 8 == 0) {
3773 mdb_printf("\n%08x: ", cnt1);
3774 }
3775 mdb_printf("%08x ", *dp++);
3776 }
3777 }
3778
3779 if ((ha->cfg_flags & CFG_ENABLE_FWEXTTRACE) &&
3780 (ha->fwexttracebuf.bp != NULL)) {
3781 uint32_t cnt_b = 0;
3782 uint32_t *w32 = ha->fwexttracebuf.bp;
3783
3784 mdb_printf("\n\nExtended Trace Buffer Memory");
3785 /* show data address as a byte address, data as long words */
3786 for (cnt = 0; cnt < FWEXTSIZE / 4; cnt++) {
3787 cnt_b = cnt * 4;
3788 if (cnt_b % 32 == 0) {
3789 mdb_printf("\n%08x: ", w32 + cnt_b);
3790 }
3791 mdb_printf("%08x ", fw->ext_trace_buf[cnt]);
3792 }
3793 }
3794
3795 if ((ha->cfg_flags & CFG_ENABLE_FWFCETRACE) &&
3796 (ha->fwfcetracebuf.bp != NULL)) {
3797 uint32_t cnt_b = 0;
3798 uint32_t *w32 = ha->fwfcetracebuf.bp;
3799
3800 mdb_printf("\n\nFC Event Trace Buffer Memory");
3801 /* show data address as a byte address, data as long words */
3802 for (cnt = 0; cnt < FWFCESIZE / 4; cnt++) {
3803 cnt_b = cnt * 4;
3804 if (cnt_b % 32 == 0) {
3805 mdb_printf("\n%08x: ", w32 + cnt_b);
3806 }
3807 mdb_printf("%08x ", fw->fce_trace_buf[cnt]);
3808 }
3809 }
3810
3811 mdb_free(rsp_q, sizeof (ql_response_q_t));
3812 mdb_free(rsp_queues, ha->rsp_queues_cnt * sizeof (ql_response_q_t *));
3813 mdb_free(fw, ha->ql_dump_size);
3814
3815 mdb_printf("\n\nreturn exit\n");
3816
3817 return (DCMD_OK);
3818 }
3819
3820 /*
3821 * ql_gettrace_dcmd
3822 * prints out the Extended Logging trace buffer
3823 *
3824 * Input:
3825 * addr = User supplied address. (NB: must be an ha)
3826 * flags = mdb flags.
3827 * argc = Number of user supplied args.
3828 * argv = Arg array.
3829 *
3830 * Returns:
3831 * DCMD_OK or DCMD_ERR
3832 *
3833 * Context:
3834 * User context.
3835 *
3836 */
3837 static int
3838 qlc_gettrace_dcmd(uintptr_t addr, uint_t flags, int argc, const mdb_arg_t *argv)
3839 {
3840 ql_adapter_state_t *ha;
3841 ql_trace_desc_t *trace_desc;
3842 ql_trace_entry_t entry;
3843 uint32_t i = 0;
3844 char merge[1024];
3845
3846 if ((!(flags & DCMD_ADDRSPEC)) || addr == NULL) {
3847 mdb_warn("ql_adapter_state structure addr is required");
3848 return (DCMD_USAGE);
3849 }
3850
3851 if (argc != 0) {
3852 return (DCMD_USAGE);
3853 }
3854
3855 if (mdb_getopts(argc, argv) != argc) {
3856 return (DCMD_USAGE);
3857 }
3858
3859 /*
3860 * Get the adapter state struct which was passed
3861 */
3862 if ((ha = (ql_adapter_state_t *)mdb_alloc(sizeof (ql_adapter_state_t),
3863 UM_SLEEP)) == NULL) {
3864 mdb_warn("failed to allocate memory for ql_adapter_state\n");
3865 return (DCMD_OK);
3866 }
3867
3868 if (mdb_vread(ha, sizeof (ql_adapter_state_t), addr) == -1) {
3869 mdb_warn("failed to read ql_adapter_state at %p", addr);
3870 mdb_free(ha, sizeof (ql_adapter_state_t));
3871 return (DCMD_OK);
3872 }
3873
3874 if (ha->ql_trace_desc == NULL) {
3875 mdb_warn("trace descriptor does not exist for instance %d\n",
3876 ha->instance);
3877 mdb_free(ha, sizeof (ql_adapter_state_t));
3878 return (DCMD_OK);
3879
3880 } else {
3881 trace_desc = (ql_trace_desc_t *)
3882 mdb_alloc(sizeof (ql_trace_desc_t), UM_SLEEP);
3883
3884 if (mdb_vread(trace_desc, sizeof (ql_trace_desc_t),
3885 (uintptr_t)ha->ql_trace_desc) == -1) {
3886 mdb_warn("failed to read ql_adapter_state at %p",
3887 addr);
3888 mdb_free(trace_desc, sizeof (ql_trace_desc_t));
3889 mdb_free(ha, sizeof (ql_adapter_state_t));
3890 return (DCMD_OK);
3891 }
3892
3893 if (trace_desc->trace_buffer == NULL) {
3894 mdb_warn("trace buffer does not exist for "
3895 "instance %d\n", ha->instance);
3896
3897 mdb_free(trace_desc, sizeof (ql_trace_desc_t));
3898 mdb_free(ha, sizeof (ql_adapter_state_t));
3899 return (DCMD_OK);
3900 }
3901 }
3902
3903 /* Check if anything logged or not */
3904 if (trace_desc->csize == 0) {
3905 mdb_warn("Extended log buffer is empty.\n");
3906 mdb_free(trace_desc, sizeof (ql_trace_desc_t));
3907 mdb_free(ha, sizeof (ql_adapter_state_t));
3908 return (DCMD_OK);
3909 }
3910
3911 /*
3912 * Locate the start and end point. If ever wrapped, then
3913 * always print from start to end in the circular buffer
3914 */
3915
3916 /* always print from start to end */
3917 for (i = trace_desc->start; i < trace_desc->csize; i++) {
3918 if (mdb_vread(&entry, sizeof (ql_trace_entry_t),
3919 (uintptr_t)&trace_desc->trace_buffer[i]) !=
3920 sizeof (ql_trace_entry_t)) {
3921 mdb_warn("Cannot read trace entry. %xh", i);
3922 mdb_free(trace_desc, sizeof (ql_trace_desc_t));
3923 mdb_free(ha, sizeof (ql_adapter_state_t));
3924 return (DCMD_ERR);
3925 }
3926 if (entry.buf[0] != 0) {
3927 (void) mdb_snprintf(merge, sizeof (merge),
3928 "[%Y:%03d:%03d:%03d] "
3929 "%s",
3930 entry.hs_time.tv_sec,
3931 (int)entry.hs_time.tv_nsec / 1000000,
3932 (int)(entry.hs_time.tv_nsec / 1000) % 1000,
3933 (int)entry.hs_time.tv_nsec % 1000,
3934 entry.buf + 1);
3935 }
3936 mdb_printf("%s", merge);
3937 }
3938
3939 if (trace_desc->start != 0) {
3940 for (i = 0; i < trace_desc->start; i++) {
3941 if (mdb_vread(&entry, sizeof (ql_trace_entry_t),
3942 (uintptr_t)&trace_desc->trace_buffer[i]) !=
3943 sizeof (ql_trace_entry_t)) {
3944 mdb_warn("Cannot read trace entry. %xh", i);
3945 mdb_free(trace_desc, sizeof (ql_trace_desc_t));
3946 mdb_free(ha, sizeof (ql_adapter_state_t));
3947 return (DCMD_ERR);
3948 }
3949 if (entry.buf[0] != 0) {
3950 (void) mdb_snprintf(merge, sizeof (merge),
3951 "[%Y:%03d:%03d:%03d] "
3952 "%s",
3953 entry.hs_time.tv_sec,
3954 (int)entry.hs_time.tv_nsec / 1000000,
3955 (int)(entry.hs_time.tv_nsec / 1000) % 1000,
3956 (int)entry.hs_time.tv_nsec % 1000,
3957 entry.buf + 1);
3958 }
3959 mdb_printf("%s", merge);
3960 }
3961 }
3962
3963 mdb_printf("\n");
3964 mdb_free(trace_desc, sizeof (ql_trace_desc_t));
3965 mdb_free(ha, sizeof (ql_adapter_state_t));
3966 return (DCMD_OK);
3967 }
3968
3969 /*
3970 * ql_doprint
3971 * ql generic function to call the print dcmd
3972 *
3973 * Input:
3974 * addr - address to struct
3975 * prtsting - address to string
3976 *
3977 * Returns:
3978 * WALK_DONE
3979 *
3980 * Context:
3981 * User context.
3982 *
3983 */
3984 static int32_t
3985 ql_doprint(uintptr_t addr, int8_t *prtstring)
3986 {
3987 struct mdb_arg printarg;
3988
4046 }
4047
4048 /*
4049 * MDB module linkage information
4050 *
4051 *
4052 * dcmd structures for the _mdb_init function
4053 */
4054 static const mdb_dcmd_t dcmds[] = {
4055 { "qlclinks", NULL, "Prints qlc link information", qlclinks_dcmd },
4056 { "qlcosc", NULL, "Prints outstanding cmd info", qlc_osc_dcmd },
4057 { "qlcver", NULL, "Prints driver/mdb version", qlcver_dcmd },
4058 { "qlc_elog", "[on|off] [<inst #>|all]", "Turns qlc extended logging "
4059 "on / off", qlc_el_dcmd },
4060 { "qlcstate", ":[-v]", "Prints qlc adapter state information",
4061 qlcstate_dcmd },
4062 { "qlctgtq", NULL, "Prints qlc target queues", qltgtq_dcmd },
4063 { "qlcwdog", NULL, "Prints out watchdog linked list", qlc_wdog_dcmd},
4064 { "qlcgetdump", ":[-v]", "Retrieves the ASCII f/w dump",
4065 qlc_getdump_dcmd },
4066 { "qlcgettrace", ":", "Retrieves the ASCII Extended Logging trace",
4067 qlc_gettrace_dcmd },
4068 { NULL }
4069 };
4070
4071 /*
4072 * walker structures for the _mdb_init function
4073 */
4074 static const mdb_walker_t walkers[] = {
4075 { "qlcstates", "walk list of qlc ql_state_t structures",
4076 qlstates_walk_init, qlstates_walk_step, qlstates_walk_fini },
4077 { "qlcsrbs", "walk list of qlc ql_srb_t strctures",
4078 qlsrb_walk_init, qlsrb_walk_step, qlsrb_walk_fini },
4079 { "qlclunq", "walk list of qlc ql_lun_t strctures",
4080 qllunq_walk_init, qllunq_walk_step, qllunq_walk_fini },
4081 { NULL }
4082 };
4083
4084 static const mdb_modinfo_t ql_mdb_modinfo = {
4085 MDB_API_VERSION, dcmds, walkers
4086 };
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