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Revert "OS-8005 bhyve memory pressure needs to target ARC better (#354)"
This reverts commit a6033573eedd94118d2b9e65f45deca0bf4b42f7.
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--- old/usr/src/uts/i86pc/sys/vmm_dev.h
+++ new/usr/src/uts/i86pc/sys/vmm_dev.h
1 1 /*-
2 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 3 *
4 4 * Copyright (c) 2011 NetApp, Inc.
5 5 * All rights reserved.
6 6 *
7 7 * Redistribution and use in source and binary forms, with or without
8 8 * modification, are permitted provided that the following conditions
9 9 * are met:
10 10 * 1. Redistributions of source code must retain the above copyright
11 11 * notice, this list of conditions and the following disclaimer.
12 12 * 2. Redistributions in binary form must reproduce the above copyright
13 13 * notice, this list of conditions and the following disclaimer in the
14 14 * documentation and/or other materials provided with the distribution.
15 15 *
16 16 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
17 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 19 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
20 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 26 * SUCH DAMAGE.
27 27 *
28 28 * $FreeBSD$
29 29 */
30 30 /*
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31 31 * This file and its contents are supplied under the terms of the
32 32 * Common Development and Distribution License ("CDDL"), version 1.0.
33 33 * You may only use this file in accordance with the terms of version
34 34 * 1.0 of the CDDL.
35 35 *
36 36 * A full copy of the text of the CDDL should have accompanied this
37 37 * source. A copy of the CDDL is also available via the Internet at
38 38 * http://www.illumos.org/license/CDDL.
39 39 *
40 40 * Copyright 2015 Pluribus Networks Inc.
41 - * Copyright 2020 Joyent, Inc.
41 + * Copyright 2019 Joyent, Inc.
42 42 */
43 43
44 44 #ifndef _VMM_DEV_H_
45 45 #define _VMM_DEV_H_
46 46
47 47 #include <machine/vmm.h>
48 48
49 49 struct vm_memmap {
50 50 vm_paddr_t gpa;
51 51 int segid; /* memory segment */
52 52 vm_ooffset_t segoff; /* offset into memory segment */
53 53 size_t len; /* mmap length */
54 54 int prot; /* RWX */
55 55 int flags;
56 56 };
57 57 #define VM_MEMMAP_F_WIRED 0x01
58 58 #define VM_MEMMAP_F_IOMMU 0x02
59 59
60 60 struct vm_munmap {
61 61 vm_paddr_t gpa;
62 62 size_t len;
63 63 };
64 64
65 65 #define VM_MEMSEG_NAME(m) ((m)->name[0] != '\0' ? (m)->name : NULL)
66 66 struct vm_memseg {
67 67 int segid;
68 68 size_t len;
69 69 char name[SPECNAMELEN + 1];
70 70 };
71 71
72 72 struct vm_register {
73 73 int cpuid;
74 74 int regnum; /* enum vm_reg_name */
75 75 uint64_t regval;
76 76 };
77 77
78 78 struct vm_seg_desc { /* data or code segment */
79 79 int cpuid;
80 80 int regnum; /* enum vm_reg_name */
81 81 struct seg_desc desc;
82 82 };
83 83
84 84 struct vm_register_set {
85 85 int cpuid;
86 86 unsigned int count;
87 87 const int *regnums; /* enum vm_reg_name */
88 88 uint64_t *regvals;
89 89 };
90 90
91 91 struct vm_exception {
92 92 int cpuid;
93 93 int vector;
94 94 uint32_t error_code;
95 95 int error_code_valid;
96 96 int restart_instruction;
97 97 };
98 98
99 99 struct vm_lapic_msi {
100 100 uint64_t msg;
101 101 uint64_t addr;
102 102 };
103 103
104 104 struct vm_lapic_irq {
105 105 int cpuid;
106 106 int vector;
107 107 };
108 108
109 109 struct vm_ioapic_irq {
110 110 int irq;
111 111 };
112 112
113 113 struct vm_isa_irq {
114 114 int atpic_irq;
115 115 int ioapic_irq;
116 116 };
117 117
118 118 struct vm_isa_irq_trigger {
119 119 int atpic_irq;
120 120 enum vm_intr_trigger trigger;
121 121 };
122 122
123 123 struct vm_capability {
124 124 int cpuid;
125 125 enum vm_cap_type captype;
126 126 int capval;
127 127 int allcpus;
128 128 };
129 129
130 130 struct vm_pptdev {
131 131 int pptfd;
132 132 };
133 133
134 134 struct vm_pptdev_mmio {
135 135 int pptfd;
136 136 vm_paddr_t gpa;
137 137 vm_paddr_t hpa;
138 138 size_t len;
139 139 };
140 140
141 141 struct vm_pptdev_msi {
142 142 int vcpu;
143 143 int pptfd;
144 144 int numvec; /* 0 means disabled */
145 145 uint64_t msg;
146 146 uint64_t addr;
147 147 };
148 148
149 149 struct vm_pptdev_msix {
150 150 int vcpu;
151 151 int pptfd;
152 152 int idx;
153 153 uint64_t msg;
154 154 uint32_t vector_control;
155 155 uint64_t addr;
156 156 };
157 157
158 158 struct vm_pptdev_limits {
159 159 int pptfd;
160 160 int msi_limit;
161 161 int msix_limit;
162 162 };
163 163
164 164 struct vm_nmi {
165 165 int cpuid;
166 166 };
167 167
168 168 #define MAX_VM_STATS (64 + VM_MAXCPU)
169 169
170 170 struct vm_stats {
171 171 int cpuid; /* in */
172 172 int num_entries; /* out */
173 173 struct timeval tv;
174 174 uint64_t statbuf[MAX_VM_STATS];
175 175 };
176 176
177 177 struct vm_stat_desc {
178 178 int index; /* in */
179 179 char desc[128]; /* out */
180 180 };
181 181
182 182 struct vm_x2apic {
183 183 int cpuid;
184 184 enum x2apic_state state;
185 185 };
186 186
187 187 struct vm_gpa_pte {
188 188 uint64_t gpa; /* in */
189 189 uint64_t pte[4]; /* out */
190 190 int ptenum;
191 191 };
192 192
193 193 struct vm_hpet_cap {
194 194 uint32_t capabilities; /* lower 32 bits of HPET capabilities */
195 195 };
196 196
197 197 struct vm_suspend {
198 198 enum vm_suspend_how how;
199 199 };
200 200
201 201 struct vm_gla2gpa {
202 202 int vcpuid; /* inputs */
203 203 int prot; /* PROT_READ or PROT_WRITE */
204 204 uint64_t gla;
205 205 struct vm_guest_paging paging;
206 206 int fault; /* outputs */
207 207 uint64_t gpa;
208 208 };
209 209
210 210 struct vm_activate_cpu {
211 211 int vcpuid;
212 212 };
213 213
214 214 struct vm_cpuset {
215 215 int which;
216 216 int cpusetsize;
217 217 #ifndef _KERNEL
218 218 cpuset_t *cpus;
219 219 #else
220 220 void *cpus;
221 221 #endif
222 222 };
223 223 #define VM_ACTIVE_CPUS 0
224 224 #define VM_SUSPENDED_CPUS 1
225 225 #define VM_DEBUG_CPUS 2
226 226
227 227 struct vm_intinfo {
228 228 int vcpuid;
229 229 uint64_t info1;
230 230 uint64_t info2;
231 231 };
232 232
233 233 struct vm_rtc_time {
234 234 time_t secs;
235 235 };
236 236
237 237 struct vm_rtc_data {
238 238 int offset;
239 239 uint8_t value;
240 240 };
241 241
242 242 struct vm_devmem_offset {
243 243 int segid;
244 244 off_t offset;
245 245 };
246 246
247 247 struct vm_cpu_topology {
248 248 uint16_t sockets;
249 249 uint16_t cores;
250 250 uint16_t threads;
251 251 uint16_t maxcpus;
252 252 };
253 253
254 254 struct vm_readwrite_kernemu_device {
255 255 int vcpuid;
256 256 unsigned access_width : 3;
257 257 unsigned _unused : 29;
258 258 uint64_t gpa;
259 259 uint64_t value;
260 260 };
261 261 _Static_assert(sizeof(struct vm_readwrite_kernemu_device) == 24, "ABI");
262 262
263 263 enum vcpu_reset_kind {
264 264 VRK_RESET = 0,
265 265 /*
266 266 * The reset performed by an INIT IPI clears much of the CPU state, but
267 267 * some portions are left untouched, unlike VRK_RESET, which represents
268 268 * a "full" reset as if the system was freshly powered on.
269 269 */
270 270 VRK_INIT = 1,
271 271 };
272 272
273 273 struct vm_vcpu_reset {
274 274 int vcpuid;
275 275 uint32_t kind; /* contains: enum vcpu_reset_kind */
276 276 };
277 277
278 278 struct vm_run_state {
279 279 int vcpuid;
280 280 uint32_t state; /* of enum cpu_init_status type */
281 281 uint8_t sipi_vector; /* vector of SIPI, if any */
282 282 uint8_t _pad[3];
283 283 };
284 284
285 285 #define VMMCTL_IOC_BASE (('V' << 16) | ('M' << 8))
286 286 #define VMM_IOC_BASE (('v' << 16) | ('m' << 8))
287 287 #define VMM_LOCK_IOC_BASE (('v' << 16) | ('l' << 8))
288 288 #define VMM_CPU_IOC_BASE (('v' << 16) | ('p' << 8))
289 289
290 290 /* Operations performed on the vmmctl device */
291 291 #define VMM_CREATE_VM (VMMCTL_IOC_BASE | 0x01)
292 292 #define VMM_DESTROY_VM (VMMCTL_IOC_BASE | 0x02)
293 293 #define VMM_VM_SUPPORTED (VMMCTL_IOC_BASE | 0x03)
294 294
295 295 /* Operations performed in the context of a given vCPU */
296 296 #define VM_RUN (VMM_CPU_IOC_BASE | 0x01)
297 297 #define VM_SET_REGISTER (VMM_CPU_IOC_BASE | 0x02)
298 298 #define VM_GET_REGISTER (VMM_CPU_IOC_BASE | 0x03)
299 299 #define VM_SET_SEGMENT_DESCRIPTOR (VMM_CPU_IOC_BASE | 0x04)
300 300 #define VM_GET_SEGMENT_DESCRIPTOR (VMM_CPU_IOC_BASE | 0x05)
301 301 #define VM_SET_REGISTER_SET (VMM_CPU_IOC_BASE | 0x06)
302 302 #define VM_GET_REGISTER_SET (VMM_CPU_IOC_BASE | 0x07)
303 303 #define VM_INJECT_EXCEPTION (VMM_CPU_IOC_BASE | 0x08)
304 304 #define VM_SET_CAPABILITY (VMM_CPU_IOC_BASE | 0x09)
305 305 #define VM_GET_CAPABILITY (VMM_CPU_IOC_BASE | 0x0a)
306 306 #define VM_PPTDEV_MSI (VMM_CPU_IOC_BASE | 0x0b)
307 307 #define VM_PPTDEV_MSIX (VMM_CPU_IOC_BASE | 0x0c)
308 308 #define VM_SET_X2APIC_STATE (VMM_CPU_IOC_BASE | 0x0d)
309 309 #define VM_GLA2GPA (VMM_CPU_IOC_BASE | 0x0e)
310 310 #define VM_GLA2GPA_NOFAULT (VMM_CPU_IOC_BASE | 0x0f)
311 311 #define VM_ACTIVATE_CPU (VMM_CPU_IOC_BASE | 0x10)
312 312 #define VM_SET_INTINFO (VMM_CPU_IOC_BASE | 0x11)
313 313 #define VM_GET_INTINFO (VMM_CPU_IOC_BASE | 0x12)
314 314 #define VM_RESTART_INSTRUCTION (VMM_CPU_IOC_BASE | 0x13)
315 315 #define VM_SET_KERNEMU_DEV (VMM_CPU_IOC_BASE | 0x14)
316 316 #define VM_GET_KERNEMU_DEV (VMM_CPU_IOC_BASE | 0x15)
317 317 #define VM_RESET_CPU (VMM_CPU_IOC_BASE | 0x16)
318 318 #define VM_GET_RUN_STATE (VMM_CPU_IOC_BASE | 0x17)
319 319 #define VM_SET_RUN_STATE (VMM_CPU_IOC_BASE | 0x18)
320 320
321 321 /* Operations requiring write-locking the VM */
322 322 #define VM_REINIT (VMM_LOCK_IOC_BASE | 0x01)
323 323 #define VM_BIND_PPTDEV (VMM_LOCK_IOC_BASE | 0x02)
324 324 #define VM_UNBIND_PPTDEV (VMM_LOCK_IOC_BASE | 0x03)
325 325 #define VM_MAP_PPTDEV_MMIO (VMM_LOCK_IOC_BASE | 0x04)
326 326 #define VM_ALLOC_MEMSEG (VMM_LOCK_IOC_BASE | 0x05)
327 327 #define VM_MMAP_MEMSEG (VMM_LOCK_IOC_BASE | 0x06)
328 328 #define VM_PMTMR_LOCATE (VMM_LOCK_IOC_BASE | 0x07)
329 329 #define VM_MUNMAP_MEMSEG (VMM_LOCK_IOC_BASE | 0x08)
330 330 #define VM_UNMAP_PPTDEV_MMIO (VMM_LOCK_IOC_BASE | 0x09)
331 331
332 332 #define VM_WRLOCK_CYCLE (VMM_LOCK_IOC_BASE | 0xff)
333 333
334 334 /* All other ioctls */
335 335 #define VM_GET_GPA_PMAP (VMM_IOC_BASE | 0x01)
336 336 #define VM_GET_MEMSEG (VMM_IOC_BASE | 0x02)
337 337 #define VM_MMAP_GETNEXT (VMM_IOC_BASE | 0x03)
338 338
339 339 #define VM_LAPIC_IRQ (VMM_IOC_BASE | 0x04)
340 340 #define VM_LAPIC_LOCAL_IRQ (VMM_IOC_BASE | 0x05)
341 341 #define VM_LAPIC_MSI (VMM_IOC_BASE | 0x06)
342 342
343 343 #define VM_IOAPIC_ASSERT_IRQ (VMM_IOC_BASE | 0x07)
344 344 #define VM_IOAPIC_DEASSERT_IRQ (VMM_IOC_BASE | 0x08)
345 345 #define VM_IOAPIC_PULSE_IRQ (VMM_IOC_BASE | 0x09)
346 346
347 347 #define VM_ISA_ASSERT_IRQ (VMM_IOC_BASE | 0x0a)
348 348 #define VM_ISA_DEASSERT_IRQ (VMM_IOC_BASE | 0x0b)
349 349 #define VM_ISA_PULSE_IRQ (VMM_IOC_BASE | 0x0c)
350 350 #define VM_ISA_SET_IRQ_TRIGGER (VMM_IOC_BASE | 0x0d)
351 351
352 352 #define VM_RTC_WRITE (VMM_IOC_BASE | 0x0e)
353 353 #define VM_RTC_READ (VMM_IOC_BASE | 0x0f)
354 354 #define VM_RTC_SETTIME (VMM_IOC_BASE | 0x10)
355 355 #define VM_RTC_GETTIME (VMM_IOC_BASE | 0x11)
356 356
357 357 #define VM_SUSPEND (VMM_IOC_BASE | 0x12)
358 358
359 359 #define VM_IOAPIC_PINCOUNT (VMM_IOC_BASE | 0x13)
360 360 #define VM_GET_PPTDEV_LIMITS (VMM_IOC_BASE | 0x14)
361 361 #define VM_GET_HPET_CAPABILITIES (VMM_IOC_BASE | 0x15)
362 362
363 363 #define VM_STATS_IOC (VMM_IOC_BASE | 0x16)
364 364 #define VM_STAT_DESC (VMM_IOC_BASE | 0x17)
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365 365
366 366 #define VM_INJECT_NMI (VMM_IOC_BASE | 0x18)
367 367 #define VM_GET_X2APIC_STATE (VMM_IOC_BASE | 0x19)
368 368 #define VM_SET_TOPOLOGY (VMM_IOC_BASE | 0x1a)
369 369 #define VM_GET_TOPOLOGY (VMM_IOC_BASE | 0x1b)
370 370 #define VM_GET_CPUS (VMM_IOC_BASE | 0x1c)
371 371 #define VM_SUSPEND_CPU (VMM_IOC_BASE | 0x1d)
372 372 #define VM_RESUME_CPU (VMM_IOC_BASE | 0x1e)
373 373
374 374 #define VM_PPTDEV_DISABLE_MSIX (VMM_IOC_BASE | 0x1f)
375 -#define VM_ARC_RESV (VMM_IOC_BASE | 0xfe)
376 375
377 376 #define VM_DEVMEM_GETOFFSET (VMM_IOC_BASE | 0xff)
378 377
379 378 #define VMM_CTL_DEV "/dev/vmmctl"
380 379
381 380 #endif
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